Patent Application
20210140030
The present invention relates to a frame-integrated mask. More specifically, the present invention relates to a frame-integrated mask which is used for forming pixels on a silicon wafer and has a mask formed integrally with a frame, thereby preventing deformation of the mask and realizing high resolution.
Recently, research is being carried out on an electroforming method a thin film manufacturing method. The electroforming method is performed by dipping an anode body and a cathode body in an electrolyte and electrodepositing a metal thin film on the surface of the cathode body by applying electricity, and thus ultra-thin films may be manufactured in a large quantity.
As a pixel deposition technique in an organic light-emitting diode (OLED) manufacturing process, a fine metal mask (FMM) method for positioning a thin metal mask (or a shadow mask) in contact with or very close to a substrate and depositing an organic material at desired locations is commonly used.
In a conventional OLED manufacturing process, after a mask thin film is prepared, a mask is welded and fixed to an OLED pixel deposition frame and then is used. In the fixing process, there is a problem in that the mask of a large area is not well aligned. Also, in the process of welding and fixing the mask to the frame, there is a problem in that the mask sags or twists with the load since the mask film is too thin and has a large area.
In an ultra-high-resolution OLED manufacturing process, small defects of several μm may lead to pixel deposition failure, and thus there is a need to develop technology that is capable of preventing deformation of a mask, such as sagging or twisting of a mask, and clearly aligning the mask.
Recently, a microdisplay which is applied to a virtual reality (VR) device has drawn attention. A microdisplay is required to provide a much smaller screen size than those of the existing displays and still realize high quality within the small screen. Therefore, smaller mask patterns than those of a mask used in the existing high-definition OLED manufacturing process and a finer alignment of the mask before a pixel deposition process are required.
Therefore, the present invention is devised to solve the above-mentioned problems of the related art and provides a frame-integrated mask capable of realizing ultra-high-resolution pixels of a microdisplay.
Moreover, the present invention provides a frame-integrated mask capable of enhancing stability of pixel deposition by allowing a mask to be clearly aligned.
The present invention provides a frame-integrated mask which is used in a process of forming pixels on a silicon wafer, the frame-integrated mask including: a mask including a mask pattern; and a frame connected to at least a part of a region of the mask excluding a region in which the mask pattern is formed, wherein the mask has a shape corresponding to the silicon wafer and is integrally connected to the frame.
The shape of the mask may be circular.
The frame may include: a connecting frame connected to the mask; and a support frame integrally connected to a lower portion of the connecting frame and supporting the mask and the connecting frame.
The connecting frame may have a circular ring shape.
A width of the mask adhered to the connecting frame may be constant along an outer circumferential direction of the mask.
The mask may be integrally connected to the frame in a state in which a tensile force is exerted on an outer circumference of the mask in a direction of the frame.
The mask and the frame may be made of an Invar material or a Super Invar material.
the frame-integrated mask is used as a fine metal mask (FMM) for organic light-emitting diode (OLED) pixel deposition, the mask is attached to a silicon wafer substrate on which pixels are to be deposited, and the frame is fixedly installed inside an OLED pixel deposition apparatus.
A resolution of the mask pattern may be higher than at least 2000 pixels per inch (PPI).
A width of the mask pattern gradually increases from an upper portion to a lower portion.
According to the present invention with the above-described configuration, it is possible to realize ultra-high-resolution pixels of a microdisplay.
In addition, according to the present invention, it is possible to improve stability of pixel deposition by allowing a mask to be clearly aligned.
The following detailed descriptions of the invention will be made with reference to the accompanying drawings illustrating specific embodiments of the invention by way of example. These embodiments will be described in detail such that the invention can be carried out by one of ordinary skill in the art. It should be understood that various embodiments of the invention are different, but are not necessarily mutually exclusive. For example, a specific shape, structure, and characteristic of an embodiment described herein may be implemented in another embodiment without departing from the scope of the invention. In addition, it should be understood that a position or placement of each component in each disclosed embodiment may be changed without departing from the scope of the invention. Accordingly, there is no intent to limit the invention to the following detailed descriptions. The scope of the invention is defined by the appended claims and encompasses all equivalents that fall within the scope of the appended claims. In the drawings, like reference numerals denote like functions, and the dimensions such as lengths, areas, and thicknesses of elements may be exaggerated for clarity.
Hereinafter, to allow one of ordinary skill in the art to easily carry out the invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to
A target substrate 900, on which the organic material source 600 is to be deposited, e.g., a glass substrate, may be provided between the magnet plate 300 and the deposition source supply 500. The FMM 100 for enabling deposition of the organic material source 600 per pixel may be positioned in contact with or very close to the target substrate 900. The magnet 310 may generate a magnetic field and the FMM 100 is brought in contact with or very close to the target substrate 900 due to the attraction by the magnetic field.
The FMM 200 needs to be aligned before being in contact with the target substrate 900. One mask or a plurality of masks may be coupled to the frame 800. The frame 800 may be fixedly installed in the OLED pixel deposition apparatus 200 and the mask may be coupled to the frame 800 through separate attachment and welding processes.
The deposition source supply 500 may supply the organic material source 600 while horizontally reciprocating, and the organic material source 600 supplied from the deposition source supply 500 may pass through patterns PP of the FMM mask 100 and be deposited on a surface of the target substrate 900. The organic material source 600 deposited through the patterns of the FMM mask 100 may serve as pixels 700 of an OLED.
To prevent non-uniform deposition of pixels 700 due to shadow effect, the pattern of the FMM mask 100 may have a sloped shape S [or a tapered shape S]. The organic material source 600 passing through the patterns in diagonal directions along sloped surfaces may also contribute to deposition of the pixels 700 and thus the pixels 700 may be deposited to a uniform thickness.
In
Accordingly, the present invention is directed to provide a frame-integrated mask which, rather than being used in a pixel formation process for the target substrate 900 of a large area, allows for a pixel formation process on a silicon wafer of 200 mm, 300 mm, or 450 mm such that ultra-high-resolution pixels are formed.
For example, currently, quad high definition (QHD) image quality is 500 to 600 pixels per inch (PPI), and a size of each pixel is about 30 to 50 μm, and a 4K UHD or 8K UHD image quality has a resolution of up to 860 PPI or up to 1600 PPI, which is higher than the QHD image quality. A microdisplay directly applied to a VR device or a microdisplay inserted into a VR device is aimed at realizing ultra-high resolution of approximately 2000 PPI or above and has a pixel size of about 5 to 10 μm. In the case of a silicon waver, a finer and more precise process is possible compared to a glass substrate by utilizing technologies developed in a semiconductor process, and hence the silicon wafer may be employed as a substrate of a high-resolution microdisplay. In addition, the present invention is characterized by a frame-integrated mask that allows for formation of pixels on the silicon wafer.
The present invention is characterized in that a mask 20 has a shape corresponding to a silicon wafer in order to perform a pixel deposition process on the silicon wafer as a target substrate 900 [see
Referring to
The mask 20 is preferably made of an Invar or Super Invar material and may have a circular shape to correspond to the circular silicon wafer. The mask 20 may have a size corresponding to a silicon wafer of 200 mm, 300 mm, 450 mm, or the like.
A conventional mask has a shape of rectangle, polygon, or the like to correspond to a substrate of a large area. In addition, a frame also has a shape of rectangle, polygon, or the like to correspond to the mask. Since the mask has angled corners, there may be a problem in that stress is concentrated on the corners. Concentration of stress may cause different force to act on only a portion of the mask, which may twist or distort the mask, leading to a failure of pixel alignment. In particular, at an ultra-high resolution of 2000 PPI or above, stress concentration on the corners of the mask should be avoided.
Accordingly, as the mask 20 of the present invention has a circular shape, the mask 20 does not have any corners. Since there is no corner, it is possible to solve the problem that different force acts on a specific portion of the mask 20, and the stress may be uniformly distributed along a circular edge. Accordingly, the mask 20 is not twisted or distorted and contributes to clear pixel alignment, and mask patterns PP of 2000 PPI or above may be implemented. The present invention performs a pixel deposition process by matching a circular silicon wafer having a low coefficient of thermal expansion and the circular mask 20 in which the stress is uniformly distributed along the edge, so that pixels with a size of approximately 5 to 10 μm may be deposited.
Referring to (a) of
That is, in this specification, the display pattern DP does not indicate a single pattern and should be understood as a group of a plurality of pixel patterns PP corresponding to a single display. Hereinafter, the pixel pattern PP will be used interchangeably with the mask pattern PP.
The mask pattern PP may have a substantially tapered shape, and the pattern width may be a several to several tens of μm, and preferably of approximately 5 to 10 μm (resolution of 2000 PPI or above). The mask pattern PP may be formed by patterning through a photoresist (PR) [see
The frame 30 may be connected to the mask 20 or to at least a part of the plated film 20. In more detail, the mask support portion 20b, which is a region other than the mask body portion 20a that is a region where the mask pattern PP is formed in the mask 20, may be connected to the frame 30.
The frame 30 preferably has a shape surrounding the edge of the mask 20 such that the mask 20 is supported taut without sagging or twisting.
In more detail, the frame 30 may include a connecting frame 31 connected to the mask 20 and a support frame 35 integrally connected to the connecting frame 31 at a lower portion of the connecting frame 31 and supporting the mask 20 and the connecting frame 31.
The connecting frame 31 is preferably in a circular shape such that it corresponds to the shape of the mask 20 and can be connected to the edge [the mask support portion 20b] of the mask 20, and the connecting frame 31 has a hollow shape or a ring shape so as not to cover the mask pattern PP of the mask body portion 20a. That is, the connecting frame 31 may have a circular ring shape. Meanwhile, if the support frame 35 is integrally connected to the connecting frame 31 at the lower portion of the connecting frame 31, the support frame 35 may have various shapes, such as a circular ring shape, a rectangular ring shape, and the like, as long as a center portion of the support frame 350 is empty. In the present invention, the support frame 35 is illustrated as having a rectangular ring shape.
Referring to
Alternatively, the mask 20 may be integrally connected to the frame 30 [the connecting frame 31] in a state in which a tensile force F is exerted on an outer circumference [the mask support portion 20b] of the mask 20 in a direction of the frame. The direction of the frame may correspond to a direction perpendicular to a circumferential tangent of the mask 20 or a radial direction. The tensile force F may be caused by electroforming process conditions by which the mask 20 is integrally electrodeposited on the frame 30 and by shrinkage of the mask 20 due to a temperature difference caused by a temperature drop to room temperature after electrodeposition at a temperature higher than the room temperature. Since the tensile force F is exerted on the outer circumference of the mask 20 in a radial direction, the tensile force F may prevent the stress from being concentrated on a specific portion of the outer circumference of the mask 20, and enable the mask 20 and the frame 30 to be connected to each other while kept taut, thereby contributing to maintaining the alignment of the mask patterns PP.
In addition, in the frame-integrated mask 10 of the present invention, the mask 20 is integrally connected to the frame 30 and thus the alignment of the mask 20 may be completed by only a process of moving and installing the frame 30 in the OLED pixel deposition apparatus 200.
Referring to (a) of
As a conductive material, a metal may have metal oxides on the surface thereof and impurities may be introduced during a metal substrate manufacturing process, a polycrystalline silicon substrate may have an intervening product or a grain boundary, and a conductive polymer substrate may have a high probability of containing impurities and have low strength and acid resistance. Elements which hinder uniform generation of an electric field on the surface of the mother plate 40, e.g., the metal oxides, the impurities, the intervening product, and the grain boundary, are referred to as “defects”. Due to the defects, an electric field may not be uniformly applied to the cathode body made of the above-described material and thus a part of the plated film 20 may be non-uniformly formed. In addition, in the case of a polycrystalline substrate material, a position of a pattern formed on the mask may be changed due to the non-uniformity between the grains by a heat treatment process for reducing a coefficient of thermal expansion of an electroformed plated film, which may lead to the change in a deposition position of a pixel.
In implementing ultra-high-resolution pixels of an ultra-high definition (UHD) or higher level, non-uniformity of the plated film 20 and plated film patterns PP may exert bad influence on deposition of pixels. An FMM mask or a shadow mask may have a pattern width of several to several tens of μm, and preferably, approximately 5 to 10 μm (resolution of 2000 PPI or above), and thus even defects of several μm may take up a significant proportion of the size of the mask.
In addition, a process for removing, for example, metal oxides and impurities may be additionally performed to remove defects from the cathode body made of the above-described material, and in this process, other defects, e.g., etching of the cathode material, may be caused.
Therefore, the present invention may use the substrate 41 made of monocrystalline silicon. To achieve conductivity, the substrate 41 may be highly doped at a concentration equal to or higher than 1019. The doping may be performed on the entire substrate 41 or on only the surface of the substrate 41.
The doped monocrystalline silicon has no defects and thus the uniform plated film 20 [or the mask 20] having no surface defects may be formed due to generation of a uniform electric field on a whole surface in an electroforming process. The uniform mask 20 may increase the resolution of OLED pixels. Moreover, since a process for removing or preventing defects is not additionally required, process costs may be reduced and productivity may be increased.
In addition, since the substrate 41 made of silicon is used, an insulator 45 may be formed, when necessary, by merely oxidizing or nitriding the surface of the substrate 41. The insulator 45 may prevent electrodeposition of the plated film 30 to form patterns PP of the plated film 20.
Subsequently, referring to (b) of
The plated film 20 may be formed from an exposed surface of the substrate 41 in the electroforming process, which will be described below, and the generation of plated film 20 is prevented in a region where the insulator 45 is to be disposed, so that the patterns PP may be formed. Since the patterns can be formed in the process of generating the plated film 20, the mother plate 40 may also be referred to as a “mold” or a “cathode body”.
Subsequently, referring to (c) of
A plating solution is an electrolyte and may serve as a material of the plated film 20 to constitute a mask body portion 20a and a mask support portion 20b. According to an embodiment, when an Invar thin film made of an iron (Fe)-nickel (Ni) alloy is manufactured as the plated film 20, a mixture of a solution including Ni ions and a solution including Fe ions may be used as the plating solution. According to another embodiment, when a Super Invar thin film made of a Fe—Ni-cobalt (Co) alloy is manufactured as the plated film 20, a mixture of a solution including Ni ions, a solution including Fe ions, and a solution including Co ions may be used as the plating solution. The Invar thin film or the Super Invar thin film may be used as an FMM mask or a shadow mask in an OLED manufacturing process. Since the Invar thin film has a very low thermal expansion coefficient of approximately 1.0×10−6PC or the Super Invar thin film also has a very low thermal expansion coefficient of approximately 1.0×10−7° C., mask patterns may not be easily deformed by heat energy and thus the Invar thin film or the Super Invar thin film may be commonly used in a high-resolution OLED manufacturing process. The plating solution for a desired plated film 20 is not particularly limited and the following description will be focused on manufacturing of the Invar thin film 20.
Since the plated film 20 grows in thickness from the surface of the substrate 41 as the plated film 20 is electrodeposited, the plated film 20 is preferably formed such that it does not grow beyond a top surface of the insulator 45. That is, the thickness of the plated film 20 may be less than the thickness of the insulator 45. Since the plated film 20 is electrodeposited by filling up pattern spaces of the insulator 45, the plated film 20 may be formed with a tapered shape which is reverse to the shape of the pattern of the insulator 45.
Since the insulator 45 has an insulation property, a magnetic field is not formed between the insulator 45 and the anode body, or only a weak magnetic field in which plating is difficult to perform is formed. Thus, a part of the mother plate 40 where the plated film 20 is not formed and which corresponds to the insulator 45 constitutes a pattern of the plated film 20, a hole, or the like. In other words, each of the insulators 45 which are patterned 46 may form a mask pattern PP that corresponds to R, G, or B of the mask body portion 20a. A shape of a vertical cross-sectional surface of the mask pattern PP may be sloped in a substantially tapered shape, and a slope angle may be approximately 45° to 65°.
Alternatively, heat treatment may be performed on the plated film 20 after the plated film 20 is formed. The heat treatment may be performed at a temperature of 300° C. to 800° C. Generally, an Invar thin plate produced by electroforming has a higher coefficient of thermal expansion as compared to an Invar thin plate produced by rolling. Thus, by performing heat treatment on the Invar thin plate, the coefficient of thermal expansion can be lowered. In this heat treatment, slight deformation may occur in the Invar thin plate. Hence, when heat treatment is performed in a state where the mother plate 40 [or the substrate 41] and the mask 20 are attached to each other, the shape of the mask pattern PP formed in a space portion occupied by the insulator 45 of the mother plate 40 is maintained constant and the minute deformation due to the heat treatment may be advantageously prevented. In addition, even when the heat treatment is performed on the mask 20 having the mask pattern PP after the mother plate 40 [or the substrate 41] is separated from the plated film 20, there is an effect of lowering the coefficient of thermal expansion of the Invar thin film.
Therefore, as the coefficient of thermal expansion of the mask 100 is further lowered, the mask 20 capable of preventing deformation of the μm-scale pattern PP and depositing ultra-high-resolution OLED pixels may be advantageously manufactured.
Subsequently, referring to (a) of
An adhesive portion 50 may be formed on the frame 30 [the connecting frame 31] in contact with the plated film 20. An epoxy resin adhesive or the like may be used as an adhesive of the adhesive portion 50. At least a part of the edge of the plated film 20 may be adhesively fixed on the frame 30 [the connecting frame 31] by the adhesive portion 50.
Then, referring to (b) of
Then, referring to (c) of
In the case of the structure which has undergone the step shown in (c) of
Thus, the present invention may perform processes, such as (d) to (f) of
Referring to (d) of
When the plated film 20 is adhered to the adhesive portion 50 in step (a) of
Subsequently, referring to (e) of
Then, referring to (f) of
Subsequently, the release film 20d separated from the plated film 20 is peeled off (P). The release film 20d is not adhered to the frame 30 by removal of the adhesive portion 50 and is separated from the plated film 20, and thus may be immediately peeled off.
Then, referring to (g) of
(a) to (c) of
Referring to (d) of
Then, referring to (a) of
An adhesive portion 50 may be formed on an upper portion of the frame 30 [a connecting frame 31] in contact with the first plated film 20′. An epoxy resin adhesive or the like may be used as an adhesive of the adhesive portion 50. At least a part of the edge of the plated film 20 may be adhesively fixed on the frame 30 [the connecting frame 31] by the adhesive portion 50. An edge portion of the first plated film 20′ attached to the adhesive portion 50 is later removed, and hence is referred to as a “release film” 20d [see (e) of
Then, referring to (b) of
After the first plated film 20a and 20b and the second plated film 20c are formed, heat treatment may be performed on the first plated film 20a and 20b and the second plated film 20c.
Then, referring to (c) of
Subsequently, referring to (d) of
Meanwhile, the adhesive portion 50 remains on the frame-integrated mask which has undergone the step of (d) of
Referring to (e) of
Then, referring to (f) of
Subsequently, the release film 20d separated from the first plated film 20′ is peeled off. The release film 20d is not adhered to the frame 30 by removal of the adhesive portion 50 and is separated from the plated film 20′, and thus may be immediately peeled off.
Then, referring to (g) of
In order to ensure rigidity of the frame 30 and to have a coefficient of thermal expansion similar to that of the mask 20, the frame 30 is preferably made of a metal material, such as Invar, Super Invar, SUS, Ti, or the like, which has conductivity, and more preferably, the same Invar or Super Invar material as that of the mask 20. Also, it is preferable to use a material having a small thermal strain in order to prevent deformation of the frame 30 due to heat in the OLED pixel deposition process.
Referring to
Referring to
The support frame 35 may further include a protruding portion 37 which can be inserted into the recess 801, and the manufactured frame-integrated mask 10′ may be inserted into the recess 801 of the frame 800 fixedly installed inside the OLED pixel deposition apparatus 200. The recess 801 may be formed in a shape that corresponds to the support frame 35 or the protruding portion 37 formed on a plurality of frame-integrated masks 10′.
The recess 801 of the pre-installed frame 800 may serve as a guide rail, so that alignment of the mask may be completed by simply inserting and sliding the manufactured frame-integrated mask 10′ into the recess 801 and sliding the frame-integrated mask 10′. In one example, the rectangular-shaped support frame 35 may be firmly fixed without moving. In another example, in a case where a pair of linear support frames 35 in parallel with each other is provided, the support frames 35 may be inserted into the recess 801 in a sliding manner, and the plurality of frame-integrated masks 10′ may be pushed and arranged in a sliding manner.
As such, the frame-integrated mask 10 or 10′ of the present invention includes the mask 20 having a shape that corresponds to a silicon wafer, so that stress is uniformly distributed over the edge of the mask 20, thereby providing ultrafine mask patterns PP, and ultra-high-resolution pixels at 2000 PPI or above may be realized in a microdisplay. Also, in the frame-integrated mask 10 or 10′ of the present invention, the mask 20 is integrally formed with the frame 30 and is integrally connected to the connecting frame 31 having a shape corresponding to the mask 20 such that the stress can be uniformly distributed, thereby preventing deformation of the mask 20 and achieving clear alignment. Also, in the frame-integrated mask 10 or 10′ of the present invention, the mask 20 is integrally connected to the frame 30, and hence alignment of the mask 20 may be completed through processes of moving the frame 30 to the OLED pixel deposition apparatus 200 and installing the frame 30.
While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2017-0067396 | May 2017 | KR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/KR2018/004272 | 4/12/2018 | WO | 00 |
