The present invention relates to display uniformity correction. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
The embodiments disclosed herein are mainly described in terms of particular device and system provided in particular implementations. However, one of ordinary skill in the art will readily recognize that this method and system will operate effectively in other implementations. For example, the circuits and devices usable with the present invention can take a number of different forms. The present invention will also be described in the context of particular methods having certain steps. However, the method and system operate effectively for other methods having different and/or additional steps not inconsistent with the present invention.
According to the exemplary embodiment, a method and system for display uniformity correction is provided. The display uniformity correction may include measuring non-uniformity characteristics, such as bias, gain, and backlight leakage, of a flat-panel display screen. Thereafter, compensation data configured to correct the non-uniformity characteristics is created. The compensation data may be considered a complement to the non-uniformity data. The compensation data is stored in a small memory in the flat-panel, and is preferably compressed by storing the compensation data for only a subset of the pixels comprising the flat-panel. As display data is received and the flat-panel is scanned to display an image, the compensation data is decompressed by reading only the compensation data surrounding a current pixel location from the memory, and then performing real-time interpolation on the compensation data to generate correction data for the current pixel. The interpolated correction data is then overlaid and superimposed on the display data to create uniformity corrected display data. The uniformity corrected display data is then displayed on the display screen, thereby providing improved image quality.
Conventional components of the display device 100 for producing a picture on the display screen 128 include a data receive block 102, a timing receive block 104, a timing control (TCON) block 108, a backlight control (B/L CTL) block 110, a source driver 112, a gate driver 114, a LCD power control 116, a backlight power supply inverter (BLPS) 118, a backlight source 120, a backlight reflector 126, and a register block 124. In accordance with the exemplary embodiment, the display device 100 is further provided with a pixel process pipeline 106 that enhances the incoming display data 130 to improve display picture quality, as explained further below.
In one embodiment, the display screen 128 is capable of displaying display data at 8-bit resolution, meaning that 256 shades of grayscaling can be displayed. As those with ordinary skill in the art will readily understand, the term “grayscale” may apply not only to monochromatic displays but also to color displays where the brightness or perceived luminance of a colored region is to vary across a pre-determined intensity range.
The data receive block 102 receives the input display data 130, which in one embodiment comprises frames of RGB (Red, Green, Blue) digital pixel data having 10-bits for each RGB component, and outputs the display data 130 to the pixel process pipeline 106. The timing receive block 104 receives timing signals 132 from a display controller (not shown) and outputs the timing signals to the timing control block (TCON) 108, the backlight control block 110, and the pixel process pipeline 106. The timing signals 132 may include a pixel clock (PCLK) signal, a display enable (DE) bit, a horizontal sync (HS) signal, and a vertical sync (VS) signal. The timing control block (TCON) 108 generates further internal timing control signals for the pixel process pipeline 106, the source driver 112, the gate driver 114, and the LCD power control 116.
The LCD power control 116 may include a DC-to-DC converter and generates relatively high voltage for the source driver 112 and gate driver 114. The backlight control block 110 generates backlight control signals, which are output to the backlight power supply inverter 118. The backlight power supply inverter 118 generates high voltage for backlight lighting, which is supplied to the backlight source 120 and backlight reflector 126. The backlight reflector 126, in turn, distributes the light from the backlight source 120 as evenly as possible. The value of the high voltage depends on the type backlight source 120, e.g., CCFL (Cold Cathode Fluorescent Lamps) or LED (Light Emitted Diode). Necessary electric power is supplied by a power supply line 122 from a host computer system (not shown). The LCD power control 116 and the backlight power supply inverter 118 convert the voltage from the power supply line 122 to meet the requirements of the source driver 112, gate driver 114, and the backlight source 120. All necessary parameters for the above operations are given from a register value in the register block 124, which are written and read through a control interface (CTL INTF) signal by system software or one of peripherals from a computer system (not shown).
As explained above, characteristics of the display screen 128 that may cause non-uniformity include variations in brightness (bias shift and gain error) and black levels. Bias shift, gain error and black level leakage are non-uniformity characteristics that may occur in the display screen 128 and are briefly explained with respect to
In accordance with the exemplary embodiment, the pixel process pipeline 106 shown in
According to one embodiment, the compensation data 136 is created and stored during a configuration stage, which could occur for example, during manufacturing/testing of the display device 100 and/or the display screen 128. During the configuration stage, non-uniformity characteristics of the display screen 128 are measured using well-known methods, and compensation data for correcting the non-uniformity characteristics is determined. The compensation data 136 is compressed to reduce storage space requirements by storing the compensation data 136 only for a subset of pixel locations comprising the display screen 128 in one or more memories (described below) of the display device 100. According to one aspect of the exemplary embodiment, the subset of pixel locations is defined by dividing the display screen into a pixel grid and storing the compensation data 136 only for points comprising the pixel grid, as shown in
Adjacent points at row and column intersections of the pixel grid 400 are used to define a matrix of shapes 402 across the display screen 128 that encompass multiple pixels of the display screen 128. In an exemplary embodiment, the shapes 402 defined by the points at the row and column intersections are blocks, which are bounded by four grid points. For example, pixel P at location (X, Y) of the display screen 128 falls within a block defined by the four points labeled An, An−1, Bn, and Bn−1. In alternative embodiments, the points may be selected to define shapes 402 other than blocks, such as rectangles, circles, and polygons for example. In each example, each type of shape 402 should encompass multiple rows and columns of pixels.
According to the exemplary embodiment, the compensation data 136 is compressed to reduce storage space requirements by storing the compensation data 136 only for the grid points of the pixel grid 400 that define shapes 402. In one embodiment, values for the compensation data 136 may be stored specifically for each grid point (e.g., Bn, Bn−1, Bn−2, . . . , An−n; An, An−1, An−2, . . . , An−n). However, in a preferred embodiment, only the differences between compensation data 136 values between adjacent grid points are stored for each grid point. These difference values may also be referred to as differential values.
Referring again to
In step 304, the pixel process pipeline 106 overlays the display data 130 with the uniformity correction data 610 to produce uniformity corrected display data 138. Finally, in step 306, the pixel process pipeline 106 outputs the uniformity corrected display data 138 for display on the display screen 128.
According to the method and system of the exemplary embodiment, providing uniformity corrected display data 138 that compensates for the non-uniformities in the display characteristics of the display device effectively improves overall image quality of the display device, even with increasing sizes of display devices. Consequently, the exemplary embodiment may also increase production yields of display devices for manufacturers.
The GLUT block 502 performs gamma correction on the RGB display data 130 to control the overall brightness of the image and outputs gamma corrected display data 508. The GLUT block 502 may be optionally configured to perform white balance control also. Although gamma correction of RGB the display data 130 provided by the GLUT block 502 is shown as a part of the pixel process pipeline 106, gamma correction functions and/or functions of the FRC 506 are optional and may be performed outside the pixel process pipeline 106.
As described above, the display uniformity controller 504 increases uniformity of the display screen 128 by applying and overlaying compensation data 136 on to the display data. More specifically, the display uniformity controller 504 interpolates the compensation data 136 to generate uniformity correction data 610 (shown in
According to the exemplary embodiment, the data width of display data 130 input to, and output from, inside modules of the pixel process pipeline 106 may be changed by data processing. For example, the GLUT block 502 may increase the data width of the incoming display data 130 so that the display uniformity controller 504 may perform more precise display uniformity correction. In the embodiment shown, the display data 130 is input to the GLUT 502 as 8 or 10-bit RGB, but the GLUT block 502 outputs the gamma corrected display data 508 as 12-bit RGB. The display uniformity controller 504 also outputs the uniformity corrected display data 138 as 12-bit RGB. Thereafter, the FRC 506 is used to reduce the data width of the uniformity corrected display data 138 to match the data width of the source driver 112 prior to display. In one embodiment, the FRC 506 uses a static dither or dynamic dither algorithm and converts the 12-bit uniformity corrected display data 138 to 8-bit output uniformity corrected display data 138′ for display.
Referring to
The display uniformity controller (DUC) 504 also may include means for generating gain uniformity correction data 610b for correcting premeasured gain error of a display device. For example, the DUC 504 may include a gain uniformity correction (GUC) generator 604 and gain compensation data 136b, which compensates for display gain non-uniformity. The GUC generator 604 retrieves the gain compensation data 136b corresponding to the current pixel location and interpolates the gain compensation data 136b to produce the gain uniformity correction data 610b.
The display uniformity controller (DUC) 504 may also include means for generating black-level uniformity correction data 610c for correcting premeasured backlight leakage of the display screen 128. For example, the DUC 504 may include a black level correction (BLC) generator 606 and black level compensation data 136c, which compensates black level non-uniformity. The BLC generator 606 retrieves the black level compensation data 136c corresponding to the current pixel location and interpolates the black level compensation data 136c to produce the black level uniformity correction data 610c.
The display uniformity controller (DUC) 504 also preferably includes means for summing the display data 130 with the bias uniformity correction data 610a, the gain uniformity correction data 610b, and the black level uniformity correction data 610c to produce the uniformity corrected display data 138. For example, the display uniformity controller (DUC) 504 may include an adder 608, which is coupled to the BUC generator 602, the GUC generator 604, and the BLC generator 606, for performing the summation. The uniformity corrected display data 138 may be considered as a complement of the non-uniformity pattern. Overlaying display data 130 with the uniformity correction data 610 to produce the uniformity corrected display data 138 significantly reduces the non-uniformity characteristics of the display screen.
In one embodiment, the BUC generator 602, the GUC generator 604, and the BLC generator 606 are implemented as hardware components. However, the BUC generator 602, the GUC generator 604, and the BLC generator 606 may be implemented as software components, or a combination of hardware and software. Although the BUC generator 602, the GUC generator 604, and the BLC generator 606 are shown as separate components, the functionality of each may be combined into a lesser or greater number of components. Also, in one embodiment, the different types of compensation data, collectively referred to as compensation data 136 in
The details of the operation of bias uniformity correction (BUC) generator 602, the gain uniformity correction (GUC) generator 604, and the black level correction (BLC) generator 606 of
According to the exemplary embodiment, the gain uniformity correction (GUC) generator 604 generates the gain uniformity correction data 610b through an interpolation and a multiplication operation; the bias uniformity correction (BUC) generator 602 generates the bias uniformity correction data 610a through an interpolation and addition/subtraction operation; and the black level correction (BLC) generator 606 generates black level uniformity correction data 610c through an interpolation and a multiplication operation, as described below.
Inputs to the pattern generator 804 are the timing signals 132, which include the pixel clock (PCLK) signal, the display enable (DE) bit, the horizontal sync (HS) signal, and the vertical sync (VS) signal. The numbers of horizontal sync (HS) signals, vertical sync (VS) signals, and the pixel clock (PCLK) signal locate a current pixel P (X, Y) position to be rendered. Inputs to the multiplier 808 include the R, G, B independent gamma corrected display data 508 from the GLUT 502.
The GUC 604, which includes separate RGB GUC blocks (as shown in
A description of how the gain compensation data 136b shown in
Given P (X, Y), the pattern generator 804 reads from the data memory 802 the gain compensation data 136b, which are preferably stored as different values, for the four corners (An, An−1, Bn, and Bn−1) defining the pixel block 902 in which P (X, Y) lies. The actual compensation data 136b to be applied to P (X, Y) is determined by interpolating the gain compensation data 136b of the four surrounding corners (An, An−1, Bn, and Bn−1). The compensation data for the four corners of the block 902 is interpolated in the Y direction first along the column lines of the pixel block 902 (e.g., between points Bn−1 and An−1 to calculate Cn−1 color and between points Bn and An to calculate Cn), followed by interpolation in the X direction along the pixels of the scan line on which the current pixel P (X, Y) lies (e.g., between points Cn and Cn−1).
Linear interpretation between the grid points is achieved by calculating vertical differential values and horizontal differential values (dAn, dBn, and dCn) from the compensation data 136b stored for grid points An, An−1, Bn, and Bn−1. For example, between the points Cn−1 and Cn, the pattern generator 804 calculates the differential value dCn between neighboring pixels of the scan line between the points Cn−1 and Cn. That is, for each pixel of the scan line to be rendered, a delta dCn is calculated between the current pixel and the previous pixel. The pattern generator 804 outputs each dCn value to the data accumulator 806, where the dCn values are accumulated until P (X, Y) is reached along the scan line.
The data accumulator 806 generates an interpolated gain correction data Cn for the current pixel P (X, Y), where Cn=dCn+Cn−1. Thus, the data accumulator 806 iteratively adds the compensation data of the previous pixel to calculate the compensation data for the current pixel. The gain correction data Cn interpolated from the summation of the dCn's is then applied to P (X, Y) by being input to the multiplier 808 for multiplication with the gamma corrected RGB display data 508. In the exemplary embodiment, both the output from the multiplexer 812 and the data register 814 are 12 bits. Based on the above, it can be seen that calculation of the gain compensation data 610b through linear interpolation is performed through a multiplication operation.
This section describes the details of the interpolation process. In operation, before interpolation, initial value Cn−1 is input to the multiplexer 812, then input to the data register 814 for storage. For the next pixel in the scan line, the current correction value Cn is input to the adder 810. The dCn for the current pixel is input to the adder 810, and these are added by the adder 810 prior to being input to the multiplexer 812.
The pattern generator 804 loads Rs, Gs, and Bs data before display screen scan start. In parallel to the screen scan, the pattern generator 804 fetches R, G, and B gain compensation data 136b for the current block from the data memory 802. Referring again to
Referring to
where Cn-1=An-1·(1−y)+Bn-1·(y) and dCn=dAn-1·(1−y)+dBn-1·(y)
P(X, Y) is accumulated every PCLK by GUC data accumulator 806 and stored in data register 814 and P(X, Y) is given by:
The first 2 bytes specify pattern grid start point (PGSP) SX and SY. The bias compensation data 136a value of PGSP starting point is zero. The first 4-bit of a data line provides a delay count of the interpolation start. It is treated as pattern start right shift number. The 4-bit bias compensation data 136a provides a horizontal differential value from the previous (left) grid point. The 4-bit bias compensation data 136a may be defined as the following:
Referring to
The pattern generator 1104 outputs Cn-1 (7-bit) and dCn (4-bit), which is calculated value from An-1, Bn-1, dAn, dBn, and y (y=Y mod 8):
where Cn-1=An-1·(1−y)+Bn-1·(y) and dCn=dAn-1·(1−y)+dBn-1·(y)
P(X, Y) is accumulated every PCLK by BUC data accumulator 1106 and stored in the data register 1112 and P(X, Y) is given by:
P(X,Y)=Cn-1+dCn·(x) and x=X mod 8
For each pixel of the scan line to be rendered, the delta dCn is calculated between the current pixel and the previous pixel. The pattern generator 1104 outputs each dCn value to the data accumulator 1106, where the dCn values are accumulated until P(X, Y) along the scan line is reached. The data accumulator 1106 generates an interpolated bias correction data Cn for the current pixel P (X, Y), where Cn=dCn+Cn−1. Thus, the data accumulator 1106 iteratively adds the compensation data of the previous pixel to calculate the compensation data for the current pixel. The bias correction data Cn interpolated from the summation of the dCn's by the data register 1112 is then output as the bias uniformity correction data 610a and applied to P (X, Y). In the exemplary embodiment, the output from the BUC 602 is 9 bits.
Based on the equations, it can be seen that calculation of the bias compensation data 610a through linear interpolation is performed using only addition and subtraction.
The BLC 606, which includes separate RGB BLC blocks (as shown in
A description of how the black-level compensation data 136c is fetched from the data memory 1402 is provided in conjunction with
[(1920/64)+1]×[(1080/64)+1]×3/2=31×18×1.5=837 Bytes
Given P (X, Y), the pattern generator 1404 reads from the data memory 1402 the black-level compensation data 136c for the four corners (An, An−1, Bn, and Bn−1) defining the pixel block 1502 in which P (X, Y) lies. The actual compensation data 136c to be applied to P (X, Y) is determined by interpolating the black-level compensation data 136c of the four surrounding corners (An, An−1, Bn, and Bn−1). The compensation data for the four corners of the block 1502 is interpolated in the Y direction first along the column lines of the pixel block 1502 (e.g., between points Bn−1and An−1), followed by interpolation in the X direction along the pixels of the scan line on which the current pixel P (X, Y) lies (e.g., between points Bn and Bn−1, and Cn and Cn−1).
Linear interpretation between the grid points is achieved by calculating vertical differential values and horizontal differential values (dAn, dBn, and dCn) from the compensation data 136c stored for grid points An, An−1, Bn, and Bn−1. For each pixel of the scan line to be rendered, a delta dCn is calculated between the current pixel and the previous pixel. The pattern generator 1404 outputs each dCn value to the data accumulator 1406, where the dCn values are accumulated until P(X, Y) along the scan line is reached. The data accumulator 1406 generates an interpolated black-level correction data Cn for the current pixel P (X, Y), where Cn=dCn+Cn−1. Thus, the data accumulator 1406 iteratively adds the compensation data of the previous pixel to calculate the compensation data for the current pixel. The black-level correction data Cn interpolated from the summation of the dCn's is then applied to P (X, Y) by being input to the multiplier 1408 for multiplication with the complement value of gamma corrected RGB display data 508. In the exemplary embodiment, both the output from the data register 1414 and the multiplier 1408 are 9 bits. Based on the above, it can be seen that calculation of the black-level compensation data 610b through linear interpolation is performed through a multiplication operation.
This section describes the details of the interpolation process. In operation, before interpolation, initial values Cn−1 are input to the multiplexer 1412, then input to the data register 1414 for storage. For the next pixel in the scan line, the correction value Cn is input to the adder 1410. The Cn−1 for the current pixel is input to the multiplexer 1412, and the dCn is added to the Cn−1 of the previous pixel by the adder 1410 prior to being input to the multiplexer 1412.
The pattern generator 1404 loads Rs, Gs, and Bs data before display screen scan start. In parallel to the screen scan, the pattern generator 1404 fetches R, G, and B black level compensation data 136c for the current block from the data memory 1402. In an exemplary embodiment, each grid point stores the black-level compensation data 136c as 4-bit differential data. D1 shows that when a current block 1502 is located on the beginning of a line, the 4-bit black-level compensation data 136c provides a vertical differential value from the above grid (Note: The first data of the first line is zero). D2 shows that when a current block 1502 is not on the beginning of the line; the 4-bit black-level compensation data 136c provides a horizontal differential value from the previous (left) grid point. The 4-bit black-level compensation data 136c may be defined as the following:
Referring to
where Cn-1=An-1·(1−y)+Bn-1·(y) and dCn=dAn-1·(1−y)+dBn-1·(y)
P(X, Y) is accumulated every PCLK by BLC accumulator 1406 and P(X, Y) is given by:
The following section describes the operation of the gamma lookup table (GLUT) 502 shown in
where gamma is an exponent of the power function. By convention, “input” and “output” may be both scaled to the range 0 . . . 1, with 0 representing black and 1 representing maximum white (or red, etc). Normalized in this way, the power function may be described by a single number, the exponent “gamma”.
To display the display data 130 correctly, the intensity on the display screen 128 needs to be directly proportional to the sample values. This is done with a lookup table (often called a LUT) that is loaded with a mapping that implements a power function with gamma values, thus providing “gamma correction” for the gamma encoded in the display data and/or the gamma inherent in the display screen 128. The LUT in
Referring to both
Where gamma changes smoothly across the display screen 128, a 12-bit output is needed from the GLUT 502 to provide adequate conversion. With any less than that, sometimes contour bands or Mach bands may appear in the darker areas of the image, where two adjacent sample values are still far enough apart in intensity for the difference to be visible. Conventional gamma lookup tables do not utilize an interpolator module 1704. Instead, all gamma values would need to be stored as a 12-bit value, which would require a 4K memory.
According to the exemplary embodiment, although the received display data 130 is 10 bits, the display data used to access the table memory module 1702 is reduced to 8-bits so that only 256 addresses are required in the table memory module 1702, but each address is capable of storing 10-bit gamma compensation data 508. During operation of the display device 100, the interpolator module 1704 converts the 10-bit data gamma compensation data 1752 into 12 bit data for each of red, green, and blue to produce more precise correction in intensity, while saving storage space. Accordingly, the GLUT 502 is capable of receiving input display data 130 having a first bit length (e.g., 10 bits), uses only a subset of the display data 130 (e.g., 8-bits) as an index to the table memory 1702 to reduce the size of the table memory 1702, and performs interpolation on the gamma compensation data 1752 retrieved from the table memory 1702 to produce gamma corrected display data 508 having a larger bit length (e.g., 12-bits) than the input display data 130.
According to a further aspect of the exemplary embodiment, the GLUT table memory module 1702 is configured as two memories, an odd MSB address memory 1702a for storing odd most significant bit addresses, and an even MSB address memory 1702b for storing even most significant bit addresses. The odd and even MSB address memories 1702a and 1702b are capable of 8-bit address input and may include 128 addresses and 10-bit gamma compensation data 1752 for RGB each. As the names imply, gamma compensation data 1752 having odd addresses are stored in the odd MSB 1702a, and the gamma compensation data 1752 having even addresses is stored in the even MSB 1702b. In this embodiment, the total size of the table memory module 1702 is 960 bytes (3(RGB)×2 (modules)×128 (addresses)×10 bits).
When a display data 130 address is received, a portion of the display data 130 is used to access the table memory model 1702, and the odd and even MSB address memories 1702a and 1702b are read in parallel to retrieve a first gamma compensation data 1752 value stored at an odd address and a second gamma compensation data 1752 value stored at an even address. According to this aspect of the exemplary embodiment, splitting the table memory and module 1702 into two increases the speed of the memory reads to keep better pace with the speed of the display data 130. In this embodiment, the gamma compensation data 1752 values can be read from the table memory module 1702 at the same pixel clock speed for real time interpolation. Although in an alternative embodiment, the table memory module 1702 could be implemented as a single memory, two serial memory reads would be required to obtain the gamma compensation data 1752 values stored at odd and even addresses, respectively, which would result in decreased performance. Otherwise, the table memory would need to be read at a rate two times faster than the pixel clock speed.
The MSB address module 1700 only inputs the 7-bit MSB block address 1720 of the MSB part 1716 directly to the odd MSB 702a. The 7-bit MSB block address 1720 is also input to an adder 1730 and a multiplexer 1714 of the MSB address module. The 1-bit MSB E/O 1722 (bit 2) of the MSB part 1716 is used as input to the multiplexer 1714 and a multiplexer control 1712, which may be located outside of the MSB address module 1700. The output of multiplexer 1714 is an 8-bit address used for accessing the even MSB memory 1702b. As shown, the gamma compensation data 1752 output from both the odd and even address memories 1702a and 1702b is 10 bits in length.
Data addressing of the even MSB 1702b is performed as follows. The adder 1730 adds 1 to the 7-bit MSB block address 1720, and outputs the resulting value as an 8-bit address 1732. This 8-bit address is then input to the multiplexer 1714 along with the original MSB block address 1720 and the MSB E/O bit 1722. The multiplexer 714 then checks the value of the MSB E/O bit 1722 to determine if the address in the MSB part 1716 is odd or even. If the value of the MSB E/O 1722 is one, then the address is odd and the multiplexer 1714 outputs the generated 8-bit address 1732 as an 8-bit MSB even address 1734, which is used to read a gamma compensation value from the even MSB 1702b. If the value of the MSB E/O bit 1722 is zero, then the address is even and the multiplexer outputs the 7-bit MSB block address 1720 as the 8-bit MSB even address 1734, which is used to read a gamma compensation value from the even MSB 1702b. The generated 8-bit address 1732 is discarded in this case. Although only seven bits are required to access the memory, an additional one bit value is added to access the even MSB 1702b because when the last address (i.e., the maximum data address EL 1724), of the MSB part 1716 is received, an additional even address is needed to perform the interpolation, so one bit is added by the adder 1730 to generate an 8-bit even address to access the even MSB 1702b. The even last (EL) data 1724 in the even table memory 1702b may contain white balance control data.
The 10-bit gamma compensation data 1752 values output in parallel from the odd and even address memories 1702a and 1702b are received by the interpolator module 1704. As stated previously, lower address regions of the display data 130 typically contain the most noise and require finer gamma compensation than high address regions of the display data 130. Accordingly, the GLUT 502 of the exemplary embodiment is capable of determining whether the display data 130 comprises a low or high address. Since portions of the display data 130 are used as an index to the table memory 1702 and the table memory 1702 stores gamma compensation data 1752 values from low to high addresses, it can also be determined whether the gamma compensated data 1752 values from the odd and even addresses originated from low address regions or high address regions of the table memory module 1702. In response to detecting that the display data comprises a low address, a right shift is performed on the gamma correction data values, thereby decreasing the values of the gamma correction data prior to performing interpolation on the gamma compensation data values, which originated from the low address regions. Performing a right shift or otherwise decreasing gamma correction data values for low display data addresses results in finer interpolation performed on those gamma compensation data 1752 values from low odd and even addresses.
According to the exemplary embodiment, the interpolator module 1704 comprises a most significant bit data multiplexer 1706, a most significant data subtractor 1708, a multiplier 1710, and an adder 1711. The MSB data multiplexer 1706 converts the 10-bit data from the table memory module 1702 into the 12-bit upper and base values 1726 and 1728, and interpolation is then performed between the upper and base values 1726 and 1728 with input from LSB part 1718 of the input data 130, as described below.
The multiplexer control 1712 controls the MSB data multiplexer 1706. The multiplexer control 712 determines if the display data address is low or high (and therefore, whether the gamma compensated data 1752 values from the odd and even addresses originated from low address regions or high address regions of the table memory module 1702) by examining bits 9:8 of the display data 130. There were four possible value of the contents of bits 9:8. 00, 01, 10, and 11. A low address is detected when bits 9:8 have the value 00.
If low address high precision mode is enabled, the multiplexer control 1712 sends a low address signal 1740 to the MSB data multiplexer 1706 when the multiplexer control 1712 detects a low address (e.g., MSB part 1716 bits 9:8=00. In response, the MSB data multiplexer 1706 shifts the gamma compensated data 1752 output of the table memory module 1702 2-bits right, fills bits 9 and 8 with zeros. In the other case where the MSB part 1716 bits (9:8) are not equal to 0 (=High Address), the multiplexer control 712 does not send the low address signal 1740 to the MSB data multiplexer 1706. In absence of the low address signal 1740, the MSB data multiplexer 1706 concatenates two LSB zero bits to the right of the output of the table memory module 1702. The MSB data multiplexer 1706 outputs the 12-bit upper and lower base 1726 and 1728, as shown in
After the MSB data multiplexer 1706 outputs the 12-bit upper and base values 1726 and 1728, interpolation between the upper and base values 1726 and 1728 is performed to generate the gamma corrected display data 508 as follows. First, the delta value 1754 is generated by subtracting the base value 1728 from the upper value 1726 using subtracter 1708. Next, the LSB part 1718 is multiplied with the delta value 1754 using multiplier 1710, generating multiplier output 1756. The multiplier output 1756 is then input to an adder 1711 with the base value 1728, the addition of which generates the 12-bit gamma corrected display data 508.
In accordance with this aspect of the exemplary embodiment, the FRC 506 compensates for the aforementioned characteristics by performing static and dynamic dithering to provide constant energy both spatially within each frame, and temporally across adjacent frames of the display data. As used herein, the term frame rate control (FRC) refers to the technique of varying the duty cycle at which pixels on the display screen 128 are stimulated in order to generate varying levels of pixel intensity. The result of FRC is commonly referred to as grayscale images but may also refer to color images. FRC can be performed through a variety of levels of limits of pixels on the display screen 128. Sixteen level FRC is described here, but the exemplary embodiment is applicable to other FRC levels.
The frame rate controller (FRC) 506 of the exemplary embodiment preferably includes a data separator 2000, a high/low generator 2002, a multiplier 2004, a comparator 2006, a pixel sequence LUT 2008, and a multiplexer 2010.
The data separator receives the uniformity corrected display data 138. The incoming uniformity corrected display data 138 is 12-bits, meaning that 0 to 4095 shades of gray can be displayed. However, if the display panel data width is 8-bits, the difference between gray levels between two pixels may be much smaller than 256 gray levels, i.e., in the four thousands. Therefore, conventional methods of using input 8- or 10-bit display data fail to provide adequate gray level correction. According to a further aspect of the exemplary embodiment, the bit-width of the output display data, preferably the uniformity corrected display data 138, is increased by increasing frame numbers, e.g., from four to sixteen, to provide for the 12-bit width display data equivalent. The FRC 506 performs a static dither or dynamic dither algorithm on all 12-bits of the uniformity corrected incoming display data 138, and then reduces the data width of the uniformity corrected display data 138 to match the data width of the source driver 112 prior to display by outputting 8-bit dithered uniformity corrected display data 138′.
Referring to
In response to receiving the integer part, Din_int, the High/low generator 2002 generates a data out high value, Do_hi=Din_int+1 (which is a higher energy version of the upper bits of the display data 138), and a data out low value, Do_lo=Din_int. The multiplexer 2010 receives the Do_hi and the Do_lo values and determines which to output as the 8-bit dithered uniformity corrected display data 138′ as follows.
The Multiplier 2004 receives as input the fraction part (Din_f) and an input frame counter value (Fc). The Multiplier 2004 then multiplies the fraction part (Din_f) with the frame counter (Fc), and multiplies the fraction part (Din_f) with the frame counter plus 1 (Fc+1). In one embodiment, the multiplier 2004 outputs the frame count Fc, the multiplied values Fc×Din_f and (Fc+1)×Din_f as ((Fc+1)×Din_f) mod 16, and (Fc×Din_f) mod 16 (or ignore the carry and keep the 4 bits).
The pixel sequence LUT 2008 contains a pattern of sequence numbers (Seq_No.) 2014 and outputs one of the sequence numbers 2014 based on a horizontal pixel counter (Hcnt) and a vertical line counter (Vcnt) values received from the TCON 108.
According to the exemplary embodiment, the sequence numbers 2014 are stored in the sequence number pattern 2100 in a manner that improves distribution of display energy. The sequence numbers 2014 are arranged in the sequence number pattern 2100 such that dither patterns can be derived from the pixel sequence LUT 2008 that evenly distribute energy between the pixels in each frame, and distribute energy between adjacent frames. One key is that the sequence numbers 2014 themselves are evenly distributed within the pattern 2100/LUT 2008. Another key is that the current point and next point (or previous point) have the same distance relation for the dither patterns 2104 between adjacent frames.
The following is a process for storing sequence numbers 2014 in the LUT 2008 to provide distribution of energy that is spatially and temporally even within the sequence number pattern 2100. The process begins by identifying a starting point for the 4×4 pattern 2100, and storing a first sequence number, e.g., 0, in the starting point of the pattern 2100. In this embodiment, the pattern starting point is the storage location in the upper-left corner of the pattern 2100, at coordinate P (0, 0).
Next, a set of candidate points is generated from the last storage location to determine the storage location of the next sequence number, e.g., 1. The candidate points are generated by moving two positions straight from the last storage location (both vertically and horizontally), then one position to the side (both vertically and horizontally). Another way of stating the same thing is moving one square in any direction then diagonally one position away from its starting position. According to the exemplary embodiment, four candidate points are generated. Only the candidate points falling within the boundary of the 4×4 pattern 2100 are retained, the others are discarded. To generate all possible candidate points within the pattern 2100, the moves are calculated from not only the last storage location within the pattern 2100, but also from storage locations located in symmetrical positions of at least two 4×4 patterns located at coordinates immediately adjacent to the pattern 2100, as shown in
After the four candidate locations are determined, one of the four open candidate points is randomly chosen as the storage location for the next sequence number. In the example shown in
Next, four candidate points are determined for the next sequence number, starting from the storage location of the last sequence number using the process above (only empty locations qualify for candidate storage locations). This process is repeated until all sixteen sequence numbers are stored in the pattern 2100. By storing the sequence number 2014 in the LUT 2008 in this manner, the distributed energy is spatially even.
Referring again to
The comparator 2006 uses the table of
The multiplexer 2010 receives the code 2012 from the comparator 2006 and the Do_hi and Do_low values from the high/low generator 2002. If the output Code 2012 equals 1, then the multiplexer 2010 selects Do_hi to output as the 8-bit dithered uniformity corrected display data 138′. If Code 2012 equals 0, the multiplexer 2010 selects Do_lo to output as the 8-bit dithered uniformity corrected display data 138′.
A method and system for display uniformity correction has been disclosed. The present invention has been described in accordance with the embodiments shown, and one of ordinary skill in the art will readily recognize that there could be variations to the embodiments, and any variations would be within the spirit and scope of the present invention. For example, the embodiments are operable with color spaces other than RGB, such as YUV, CMYK, and YcbCr, for instance, and any transformation thereof. In addition, the embodiments can be implemented using hardware, software, a computer readable medium containing program instructions, or a combination thereof. Software written according to the present invention is to be either stored in some form of computer-readable medium such as memory or CD-ROM, or is to be transmitted over a network, and is to be executed by a processor. Consequently, a computer-readable medium is intended to include a computer readable signal, which may be, for example, transmitted over a network. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
The present application is related to co-pending patent application U.S. application Ser. No. ______ entitled “Display Uniformity Correction”, and U.S. application Ser. No. ______ entitled “Gamma Uniformity Correction Method and System”, filed on the same date as the present application and assigned to the same assignee.