Patent Application
20050114808
The invention relates to design checking computer software and particularly to a framework for accurate design rule checking.
One way to check the performance of individual elements of a design is to dynamically simulate the design or the relevant elements in each environment in which it must operate. Another way to check the operation of individual parts is to calculate ratios or simple formulas based on a few parameters of the part being analyzed. In VLSI, these ratios may for example be capacitance, FET sizes, or some simple combinations of these.
In accordance with an embodiment, a method for accurate design rule evaluation is provided. The method includes constructing sample design portions in a simulator, sweeping simulated design parameters independently, generating a hypermatrix of results of the sweeping, and storing the hypermatrix in memory.
In accordance with another embodiment, a system for accurate design rule checking is provided. The system includes means for constructing sample design portions in a simulator, means for sweeping simulated design parameters independently, and means for generating a hypermatrix of results of the sweeping.
In engineering, there is a need for computer software that checks designs to determine if the designs meet certain quality requirements. In Very Large Scale Integrated (“VLSI”) technology, for example, the settings for individual latches need to be checked under nominal conditions, as well as under voltage, temperature, and frequency extremes.
One way to check the performance of individual elements of a design is to dynamically simulate the entire design or the relevant elements of the design in each environment in which the design must operate. Although this tends to provide the most accurate results, simulations are time consuming for large or complex designs. In VLSI circuit design, a widely used open source language for simulation software programs is known as “SPICE.”
Another way to check the operation of individual parts is to calculate ratios or simple formulas based on a few parameters of the part being analyzed. In VLSI, these ratios may for example be capacitance, field effect transistor (“FET”) sizes, or some simple combinations of these. Due to the complexity of many of these checks, the simple formulas typically do not yield the required accuracy. In order to yield the required accuracy of the check, the formulas and the parameters of the formulas become intractable to derive. For example, to set a VLSI latch requires information about the sizes (gate widths) of the FETs driving the latch, the size of the passFETs, the width of the clock pulse enabling the passFETs, the capacitances of the latch input and the latch node, and the size of the feedback FETs holding the charge on the latch node. These are typically too many parameters to model using a hand-derived formula.
In accordance with one embodiment of the invention, a method for accurately and quickly checking a design for quality requirements is provided. To achieve required accuracy and performance, all of the operating conditions to be checked are simulated ahead of time. In a latch-setting example, a sample latch is constructed in a simulator. Each of the required parameters is swept independently to generate a hypermatrix or lookup table of simulated performance results. These hypermatrices need be generated only once or very infrequently. During the checking of an individual design, the parameters swept to generate the hypermatrix are extracted by design checking software. In the parameter extraction process, the design is analyzed to find parasitics (for example capacitance, resistance, inductance) and other characteristics of the design, including FET gate widths and lengths. These parameter values are then supplied as indices, i.e., addresses, to the hypermatrix to look up the result, which is used to judge whether the circuit is designed to perform properly.
In one embodiment, hypermatrices are, for example, generated for resolving FET contentions, charging and discharging capacitors and storage nodes, propagating noise, and finding trip points and noise margins of static gates. With these hypermatrices, i.e., multi-dimensional lookup tables, implementations of the present embodiments can check large and complex VLSI designs quickly and accurately.
Other embodiments may include, for example, applications of method 300 to civil engineering or mechanical engineering design. Simulations can, for example, be run on various structural beam widths, lengths, heights, structural types, and/or materials, by sweeping these parameters in the simulations, generating hypermatrices, and then applying the hypermatrices to real designs. Important parameters, for example structural beam widths, can then be extracted from the design and used as indices to retrieve the pregenerated results in the hypermatrices, in similar fashion as in VLSI applications. The retrieved results may then be used to evaluate the real designs.
