FRAMEWORK FOR CODING AND DECODING LOW RANK AND DISPLACEMENT RANK-BASED LAYERS OF DEEP NEURAL NETWORKS

TECHNICAL FIELD

At least one of the present embodiments generally relates to a method or an apparatus for deep neural networks.

BACKGROUND

Deep Neural Networks (DNNs) have shown state of the art performance in variety of domains such as computer vision, speech recognition, natural language processing, etc. This performance however comes at the cost of massive computational cost as DNNs tend to have a huge number of parameters often running into millions, and sometimes even billions. This leads to prohibitively high inference complexity—the computational cost of applying trained DNN to test data for inference. This high inference complexity is the main challenge in bringing the performance of DNNs to mobile or embedded devices with resource limitations on battery size, computational power, and memory capacity, for example.

SUMMARY

Drawbacks and disadvantages of the prior art may be addressed by the general aspects described herein, which are directed intra prediction mode partitioning in encoding and decoding.

According to a first aspect, there is provided a method. The method comprises steps for obtaining information representative of a displacement rank of a deep neural network; obtaining vector information representative of weights and non-linearities of matrices for the deep neural network; obtaining parameters characterizing a matrix operator for the deep neural network; and, including in a bitstream said information representative of the displacement rank, vector information of non-linearities, and parameters characterizing a matrix operator; and, transmitting said bitstream.

According to a second aspect, there is provided a method. The method comprises steps for parsing a bitstream for information representative of a layer of a deep neural network; using said information to generate rank vectors representative of weights and non-linearities of said deep neural network; and decoding said rank vectors to obtain weights and non-linearities information for said deep neural network

According to another aspect, there is provided an apparatus. The apparatus comprises a processor. The processor can be configured to convey information needed to compress and decompress a deep neural network by executing any of the aforementioned methods.

According to another general aspect of at least one embodiment, there is provided a device comprising an apparatus according to any of the decoding embodiments; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, or (iii) a display configured to display an output representative of a video block.

According to another general aspect of at least one embodiment, there is provided a non-transitory computer readable medium containing data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a signal comprising video data generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, a bitstream is formatted to include data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out any of the described decoding embodiments or variants.

These and other aspects, features and advantages of the general aspects will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows one embodiment of an encoding method under the general aspects described.

FIG. 2 shows one embodiment of a decoding method under the general aspects described.

FIG. 3 shows one embodiment of an apparatus for encoding or decoding using intra prediction mode extensions.

FIG. 4 shows a generic, standard encoding scheme.

FIG. 5 shows a generic, standard decoding scheme.

FIG. 6 shows a typical processor arrangement in which the described embodiments may be implemented.

DETAILED DESCRIPTION

Deep Neural Networks (DNNs) have shown state of the art performance in variety of domains such as computer vision, speech recognition, natural language processing, and other areas. This performance however comes at the cost of massive computational cost as DNNs tend to have a huge number of parameters often running into millions, and sometimes even billions. This leads to prohibitively high inference complexity—the computational cost of applying trained DNN to test data for inference. This high inference complexity is the main challenge in bringing the performance of DNNs to mobile or embedded devices with resource limitations on battery size, computational power, and memory capacity.

The general aspects described here apply to the context of a standard for compressing pre-trained DNN which contain layers encoded/compressed using Low Displacement Rate, as detailed in application titled “Computationally Efficient Low Displacement Rank Based Deep Neural Network Compression”.

The LDR (Low Displacement Rank) approximation allows for replacing the original layer weight matrices of the pre-trained DNN as the sum of small number of structured matrices. This decomposition into sum of structured matrices leads to simultaneous compression, and low inference complexity thereby enabling the power of Deep Learning in the resource limited devices.

At the decoder side, the inference of such layer can be performed in two ways, depending on the requirements of the decoded DNN:

- Reconstruction of the layers in their original structure
- Direct inference of the layer in its LDR form.

There are no existing compression frameworks for DNN, which require a syntax to specify LDR type layers for decoding or inferring the network. Under the general aspects described herein, several embodiments of a syntax structure as well as the decoding process of an LDR layer are provided.

Let W_kdenote the k^thlayer of a pre-trained DNN with weight matrices {W₁, . . . , W_L}, biases {b₁, . . . , b_L}, and non-linearities {g₁, . . . , g_L}. With these weights, biases, and non-linearities, the output of k^thlayer y^k+1is written as [where y¹=x is the input to the DNN]

y
^k+1
=g
_k(W_ky^k+b_k) (1)

In a prior application, it is proposed to approximate W_kwith LDR matrix Ŵ_k, which has low rank r_k<<min {m, n}, then it implies that

L
_A,B(Ŵ_k)=W_k−AW_kB=G_kH_k^T,

where A, B are square matrices of size m×m, n×n respectively, G_kis a m×r_kmatrix, H_kis n×r_kmatrix, and m, n are the number of rows and columns of the original weight matrix W_k. Here, the displacement r_kis a parameter of choice. A small r_kimplies more compression and computational efficiency.

This resulting bitstream a then contains a coded version of the matrices G_kand H_k^T, information related to the operators A and B, the potential bias vectors {b₁, . . . , b_L}, and the description of non-linearities which are sent.

At inference, the decoded matrices can be applied directly, instead of a reconstructed Ŵ_kwhich denotes decoded matrix computed back to its original structure.

This requires signaling and describing the type of layer, so that the proper matrix operations are performed at inference.

Under the general aspects described herein, it is proposed to define a syntax structure that conveys the information required to decode and perform inference of an LDR encoded layer.

In the following, consider the example of using circulant matrices as operator A and B

It can be demonstrated that, when using the above equation, Ŵ can be expressed as:

$\hat{W} = \sum_{j = 1}^{r} Z_{e, m, m} (g_{j}) {Z_{f, n, m} ({Jh}_{j})}^{T} {J (I_{n} - {eZ}_{f}^{m})}^{- 1}$

Where r is the displacement rank, Z_f=(I_n-1^f) is the f-circulant matrix, g_jand h_jare the r vectors of the above G and H. The operator Z_f,n,mis defined as follows:

for a vector

$v = {(v_{1}, \dots, v_{m})}^{T}, Z_{f, n, m} (v) = {(z_{i, j})}_{1 \leq i < m 1 \leq j < n}, with$

$z_{i, j} = {\begin{matrix} v_{i - j + 1} if i \geq j \\ f^{k} v_{m - l} if j - i - 1 = km + l, 0 \leq l \leq m - 1, k \geq 0 \end{matrix}$

J_ndenotes the n×n reflection matrix, i.e., all the anti-diagonal entries are 1 as follows:

$J_{n} = [\begin{matrix} 0 & \dots & 1 \\ ⋮ & ⋱ & ⋮ \\ 1 & \dots & 0 \end{matrix}]$

As for Low Rank approximation, LDR requires storing the weights included in G and H. In addition, it requires getting the circulant parameters e and f.

Hence, the information required to perform inference includes:

- The displacement rank r
- The r vectors g_jand h_jor the matrices G and H
- The parameters e and f that characterize the matrices Z_eand Z_f

Low Rank Factorization can be obtained (at the encoder) using the well-known Singular Value Decomposition (SVD) method which states that for any matrix Aϵ custom-character ^m×n:

- W=UΣV^T. U and V can be decomposed as U=[U₁U₂] and V=[V₁V₂], and Σ is a diagonal matrix containing the real non-negative singular values of A in decreasing order. Hence, Σ can be decomposed as

$Σ = [\begin{matrix} Σ_{1} & 0 \\ 0 & Σ_{2} \end{matrix}] \cdot U_{1}, V_{1}^{T}$

and Σ₁are of size m×r, r×n and r×r, respectively.

- r is a parameter of choice. If it is equal to the actual rank of W there is equality, else, the resulting operator Ŵ consists in an approximation of W.
- A common way of storing Ŵ can also be written as Ŵ=GH^T, where G and H^T, of size m×r and r×n, correspond to the multiplication of U₁, V₁^Tby the square root of the diagonal values of Σ₁.

The exemplary parsing process described in Table 1 would be performed, the parsed syntax elements are represented in bold.

TABLE 1

parsing process of a layer

layer(layerIdx, sizeInput, sizeOutput) {

layer_—type_—idx
u(8)

has_—biases_—flag
u(1)

adaptive_—bitdepth_—flag
u(1)

if(AdaptiveBitDepth) {

Layer_—bit_—depth_—weights
ue(v)

if(EnableDeltaQp)

delta_—qp_—weights
ue(v)

if(HasBiases){

if(EnableDeltaQp)

delta_—qp_—biases
u(8)

if(AdaptiveBitDepth) {

Layer_—bit_—depth_—weights

}

if (LayerTypeIdx == TYPE_CONVOLUTION) {

nb_—channels
u(10)

kernel_—size
u(8)

}

else if (LayerTypeIdx ==TYPE_FULLY_CONNECTED ){

...

}

Else if

(LayerTypeIdx ==TYPE_LOW_DISPLACEMENT_RANK ){

e_—parameter
u(8)

f_—parameter
u(8)

rank
u(8)

reconstruct_—original_—shape_—flag
u(1)

for(r=0; r<rank;r++){

for(n=0; n< sizeInput;n++){ /*parse vector h_r*/

Coefficient_coding( )

}

for(m=0; m< sizeoutput;m++){ /*parse vector g_r*/

Coefficient_coding( )

}

}

}

else if (LayerTypeIdx ==TYPE_LOW_RANK ){

rank
u(8)

reconstruct_—original_—shape_—flag
u(1)

for(r=0; r<rank;r++){

for(n=0; n< sizeInput;n++){ /*parse vector h_r*/

Coefficient_coding( )

}

for(m=0; m< sizeoutput;m++){ /*parse vector g_r*/

Coefficient_coding( )

}

}

In Table 1, the syntax elements are coded using exemplary types of coding elements described below.

ae(v): context-adaptive arithmetic entropy-coded syntax element.

b(8): byte having any pattern of bit string (8 bits). The parsing process for this descriptor is specified by the return value of the function read_bits(8).

u(n): unsigned integer using n bits. When n is “v” in the syntax table, the number of bits varies in a manner dependent on the value of other syntax elements. The parsing process for this descriptor is specified by the return value of the function read_bits(n) interpreted as a binary representation of an unsigned integer with most significant bit written first.

ue(v): unsigned integer 0-th order Exp-Golomb-coded syntax element with the left bit first.

In the following, the different syntax elements introduced in Table 1 are described.

layer_type_idx specifies the type of the current layer LayerTypeIdx as specified in Table 2.

has_biases_flag equal to 0 specifies that the current layer does not contain any bias vector. has_biases_flag equal to 1 specifies that the current coding layer contains biases.

adaptive_bitdepth_flag equal to 0 specifies that the current layer is quantized using the same QP as the rest of the network. adaptive_bitdepth_flag equal to 1 specifies that the current layer is coded using a specific qp.

bit_depth_weights specifies the bit depth of the weights of the current layer.

bit_depth_biases specifies the bit depth of the weights of the current layer.

e_parameter specifies the parameter e of the circulant operator

$Z_{e} = (\begin{matrix} e \\ I_{n - 1} \end{matrix})$

f_parameter similarly specifies the parameter e of the circulant operator Z_f

rank specifies the low displacement rank.

reconstruct_original_shape equal to 0 specifies that the LDR layer is parsed and the factorized representation is kept. Reconstruct_original_shape equal to 1 triggers the construction of the layer in its original shape sizeInput×sizeOutput.

For example, for a convolution layer, the function coefficient_coding( ) will correspond to the decoding processes adopted in a compression standard for deriving the weights of the different layers.

Specification of LayerTypeIdx, an exemplary table specifying indexes of types of layers to be parsed, is given in Table 2.

TABLE 2

specification of LayerTypeIdx

LayerTypeIdx
Associated name

0
TYPE_FULLY_CONNECTED

1
TYPE_CONVOLUTION

2
TYPE_LOW_DISPLACEMENT_RANK

3
TYPE_LOW_RANK

4
TYPE_RECURRENT

5..
...

Then the decoding process for a layer coded in LDR mode can be expressed as the function described next. A decoder needs to know the syntax A, B for decoding. Inputs of a decoding stage are

- A layer index LayeIdx
- The size of the input sizeInput
- the size of the output sizeOutput
  
  The vectors g_rand h_rare the output of this process.

If LayerTypeIdx is equal to TYPE_LOW_DISPLACEMENT_RANK, the following applies:

The parameters e and f are parsed (e_circulant_parameter and f_circulant_parameter) as well as the transmitted rank.

The weights stored as rank vectors g_rand h_rare decoded using any method that can contain techniques such as inverse quantization, prectictive coding, as well as entropy decoding.

Several variants are possible:

- 1. As a variant, only LR could be considered in a future standard which would remove the entry TYPE_LOW_DISPLACEMENT_RANK in the proposed syntax table.
- 2. As another variant, only LDR can be considered.
- 3. As another alternative, it is possible to regroup LR and LDR layer types in the same structure at parsing, an additional flag can be added to indicate to a decoder to parse the circulant parameters e and f and to apply the LDR structure operations at inference.
- 4. Considering the above variant, specific values of e and f can trigger the low rank approximations.
- 5. In another embodiment, different operators A and B can be considered as operators. In the above description, the assumption made was that the Toeplitz operators Z were chosen, requiring transmission of the circulant parameters e and fin addition of the weights.

In table 3, the syntax is extended to enable a decoder to parse different structures:

TABLE 3

alternative syntax for extended operators

layer(layerIdx, sizeInput, sizeOutput) {

...

Else if

(LayerTypeIdx ==TYPE_LOW_DISPLACEMENT_RANK ){

rank

Idr_—operator_—idx

If (LDROperatorIdx == Toeplitz || LDROperatorIdx ==

Hankel){

e_—parameter
u(8)

f_—parameter
u(8)

}

Else If (LDROperatorIdx == Vandermonde){

f_—parameter
u(8)

parseDiagonal(sizeInput, sizeOutput)
...

}

Else If (LDROperatorIdx == Cauchy){

...
...

}

for(r=0; r<rank;r++){

for(n=0; n< sizeInput;n++){ /*parse vector h_r*/

Coefficient_coding( )

}

for(m=0; m< sizeoutput;m++){ /*parse vector g_r*/

Coefficient_coding( )

}

}

}

...

}

In this case, rank is always necessary and does not depend on the type of operators.

The syntax element Idr_operator_idx is then parsed to derive which set of parameters need to be parsed/decoded to decode the model, for instance, e_parameter and f_parameter in the case of Toeplitz-like matrices. For example, when Hankel-like operators are used, Z_eand Z_fare also involved. Their construction can then be derived using the same parameters, as described in Table 3, and knowing the type of operator LDROperatorIdx. However, Vandermonde operators, for example, require parsing a diagonal matrix, which would require an additional parsing module as described in Table 3. Other operators as Cauchy-like could be handled by such parsing architecture.

The generally described aspects are applicable to compression of deep neural networks. The described embodiments are designed to propose a syntax for the bitstream related to the MPEG7 standard, for example, for compressed representations of neural networks. However, the aspects described are equally applicable to other such standards. When a bitstream is described, it is to be understand that such a bitstream can be transmitted, conveyed, stored or otherwise used and nothing in this description shall be construed as limiting the use of the bitstream.

One embodiment of a method 100 using the general aspects described here is shown in FIG. 1. The method commences at Start block 101 and control proceeds to function block 110 for obtaining information representative of a displacement rank of a deep neural network. Control then proceeds from block 110 to block 120 for obtaining vector information representative of weights and non-linearities of matrices for the deep neural network. Control then proceeds from block 120 to block 130 for obtaining parameters characterizing a matrix operator for the deep neural network. Control then proceeds from block 130 to block 140 for including in a bitstream said information representative of the displacement rank, vector information of non-linearities, and parameters characterizing a matrix operator. Control then proceeds from block 140 to block 150 for transmitting said bitstream.

One embodiment of a method 200 using the general aspects described here is shown in FIG. 2. The method commences at Start block 201 and control proceeds to function block 210 for parsing a bitstream for information representative of a layer of a deep neural network. Control then proceeds from block 210 to block 220 for using said information to generate rank vectors representative of weights and non-linearities of said deep neural network. Control then proceeds from block 220 to block 230 for decoding said rank vectors to obtain weights and non-linearities information for said deep neural network.

FIG. 3 shows one embodiment of an apparatus 300 for compressing, encoding or decoding a deep neural network in a bitstream. The apparatus comprises Processor 310 and can be interconnected to a memory 320 through at least one port. Both Processor 310 and memory 320 can also have one or more additional interconnections to external connections.

Processor 310 is also configured to either insert or receive parameters in a bitstream and, either compressing, encoding or decoding a deep neural network using the parameters.

This application describes a variety of aspects, including tools, features, embodiments, models, approaches, etc. Many of these aspects are described with specificity and, at least to show the individual characteristics, are often described in a manner that may sound limiting. However, this is for purposes of clarity in description, and does not limit the application or scope of those aspects. Indeed, all of the different aspects can be combined and interchanged to provide further aspects. Moreover, the aspects can be combined and interchanged with aspects described in earlier filings as well.

The aspects described and contemplated in this application can be implemented in many different forms. FIGS. 4, 5, and 6 provide some embodiments, but other embodiments are contemplated and the discussion of FIGS. 4, 5, and 6 does not limit the breadth of the implementations. At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting a bitstream generated or encoded. These and other aspects can be implemented as a method, an apparatus, a computer readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the methods described, and/or a computer readable storage medium having stored thereon a bitstream generated according to any of the methods described.

In the present application, the terms “reconstructed” and “decoded” may be used interchangeably, the terms “pixel” and “sample” may be used interchangeably, the terms “image,” “picture” and “frame” may be used interchangeably. Usually, but not necessarily, the term “reconstructed” is used at the encoder side while “decoded” is used at the decoder side.

Various methods are described herein, and each of the methods comprises one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and/or use of specific steps and/or actions may be modified or combined.

Various methods and other aspects described in this application can be used to modify modules, for example, the intra prediction, entropy coding, and/or decoding modules (160, 360, 145, 330), of a video encoder 100 and decoder 200 as shown in FIG. 4 and FIG. 5. Moreover, the present aspects are not limited to VVC or HEVC, and can be applied, for example, to other standards and recommendations, whether pre-existing or future-developed, and extensions of any such standards and recommendations (including VVC and HEVC). Unless indicated otherwise, or technically precluded, the aspects described in this application can be used individually or in combination.

Various numeric values are used in the present application. The specific values are for example purposes and the aspects described are not limited to these specific values.

FIG. 4 illustrates an encoder 100. Variations of this encoder 100 are contemplated, but the encoder 100 is described below for purposes of clarity without describing all expected variations.

Before being encoded, the video sequence may go through pre-encoding processing (101), for example, applying a color transform to the input color picture (e.g., conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to get a signal distribution more resilient to compression (for instance using a histogram equalization of one of the color components). Metadata can be associated with the pre-processing and attached to the bitstream.

In the encoder 100, a picture is encoded by the encoder elements as described below. The picture to be encoded is partitioned (102) and processed in units of, for example, CUs. Each unit is encoded using, for example, either an intra or inter mode. When a unit is encoded in an intra mode, it performs intra prediction (160). In an inter mode, motion estimation (175) and compensation (170) are performed. The encoder decides (105) which one of the intra mode or inter mode to use for encoding the unit, and indicates the intra/inter decision by, for example, a prediction mode flag. Prediction residuals are calculated, for example, by subtracting (110) the predicted block from the original image block.

The prediction residuals are then transformed (125) and quantized (130). The quantized transform coefficients, as well as motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. The encoder can skip the transform and apply quantization directly to the non-transformed residual signal. The encoder can bypass both transform and quantization, i.e., the residual is coded directly without the application of the transform or quantization processes.

The encoder decodes an encoded block to provide a reference for further predictions. The quantized transform coefficients are de-quantized (140) and inverse transformed (150) to decode prediction residuals. Combining (155) the decoded prediction residuals and the predicted block, an image block is reconstructed. In-loop filters (165) are applied to the reconstructed picture to perform, for example, deblocking/SAO (Sample Adaptive Offset) filtering to reduce encoding artifacts. The filtered image is stored at a reference picture buffer (180).

FIG. 5 illustrates a block diagram of a video decoder 200. In the decoder 200, a bitstream is decoded by the decoder elements as described below. Video decoder 200 generally performs a decoding pass reciprocal to the encoding pass as described in FIG. 4. The encoder 100 also generally performs video decoding as part of encoding video data.

In particular, the input of the decoder includes a video bitstream, which can be generated by video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors, and other coded information. The picture partition information indicates how the picture is partitioned. The decoder may therefore divide (235) the picture according to the decoded picture partitioning information. The transform coefficients are de-quantized (240) and inverse transformed (250) to decode the prediction residuals. Combining (255) the decoded prediction residuals and the predicted block, an image block is reconstructed. The predicted block can be obtained (270) from intra prediction (260) or motion-compensated prediction (i.e., inter prediction) (275). In-loop filters (265) are applied to the reconstructed image. The filtered image is stored at a reference picture buffer (280).

The decoded picture can further go through post-decoding processing (285), for example, an inverse color transform (e.g. conversion from YCbCr 4:2:0 to RGB 4:4:4) or an inverse remapping performing the inverse of the remapping process performed in the pre-encoding processing (101). The post-decoding processing can use metadata derived in the pre-encoding processing and signaled in the bitstream.

FIG. 6 illustrates a block diagram of an example of a system in which various aspects and embodiments are implemented. System 1000 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances, and servers. Elements of system 1000, singly or in combination, can be embodied in a single integrated circuit (IC), multiple ICs, and/or discrete components. For example, in at least one embodiment, the processing and encoder/decoder elements of system 1000 are distributed across multiple ICs and/or discrete components. In various embodiments, the system 1000 is communicatively coupled to one or more other systems, or other electronic devices, via, for example, a communications bus or through dedicated input and/or output ports. In various embodiments, the system 1000 is configured to implement one or more of the aspects described in this document.

The system 1000 includes at least one processor 1010 configured to execute instructions loaded therein for implementing, for example, the various aspects described in this document. Processor 1010 can include embedded memory, input output interface, and various other circuitries as known in the art. The system 1000 includes at least one memory 1020 (e.g., a volatile memory device, and/or a non-volatile memory device). System 1000 includes a storage device 1040, which can include non-volatile memory and/or volatile memory, including, but not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, magnetic disk drive, and/or optical disk drive. The storage device 1040 can include an internal storage device, an attached storage device (including detachable and non-detachable storage devices), and/or a network accessible storage device, as non-limiting examples.

System 1000 includes an encoder/decoder module 1030 configured, for example, to process data to provide an encoded video or decoded video, and the encoder/decoder module 1030 can include its own processor and memory. The encoder/decoder module 1030 represents module(s) that can be included in a device to perform the encoding and/or decoding functions. As is known, a device can include one or both of the encoding and decoding modules. Additionally, encoder/decoder module 1030 can be implemented as a separate element of system 1000 or can be incorporated within processor 1010 as a combination of hardware and software as known to those skilled in the art.

Program code to be loaded onto processor 1010 or encoder/decoder 1030 to perform the various aspects described in this document can be stored in storage device 1040 and subsequently loaded onto memory 1020 for execution by processor 1010. In accordance with various embodiments, one or more of processor 1010, memory 1020, storage device 1040, and encoder/decoder module 1030 can store one or more of various items during the performance of the processes described in this document. Such stored items can include, but are not limited to, the input video, the decoded video or portions of the decoded video, the bitstream, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.

In some embodiments, memory inside of the processor 1010 and/or the encoder/decoder module 1030 is used to store instructions and to provide working memory for processing that is needed during encoding or decoding. In other embodiments, however, a memory external to the processing device (for example, the processing device can be either the processor 1010 or the encoder/decoder module 1030) is used for one or more of these functions. The external memory can be the memory 1020 and/or the storage device 1040, for example, a dynamic volatile memory and/or a non-volatile flash memory. In several embodiments, an external non-volatile flash memory is used to store the operating system of, for example, a television. In at least one embodiment, a fast external dynamic volatile memory such as a RAM is used as working memory for video coding and decoding operations, such as for MPEG-2 (MPEG refers to the Moving Picture Experts Group, MPEG-2 is also referred to as ISO/IEC 13818, and 13818-1 is also known as H.222, and 13818-2 is also known as H.262), HEVC (HEVC refers to High Efficiency Video Coding, also known as H.265 and MPEG-H Part 2), or VVC (Versatile Video Coding, a new standard being developed by JVET, the Joint Video Experts Team).

The input to the elements of system 1000 can be provided through various input devices as indicated in block 1130. Such input devices include, but are not limited to, (i) a radio frequency (RF) portion that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a Component (COMP) input terminal (or a set of COMP input terminals), (iii) a Universal Serial Bus (USB) input terminal, and/or (iv) a High Definition Multimedia Interface (HDMI) input terminal. Other examples, not shown in FIG. 6, include composite video.

In various embodiments, the input devices of block 1130 have associated respective input processing elements as known in the art. For example, the RF portion can be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) downconverting the selected signal, (iii) band-limiting again to a narrower band of frequencies to select (for example) a signal frequency band which can be referred to as a channel in certain embodiments, (iv) demodulating the downconverted and band-limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets. The RF portion of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band-limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers. The RF portion can include a tuner that performs various of these functions, including, for example, downconverting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband. In one set-top box embodiment, the RF portion and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, downconverting, and filtering again to a desired frequency band. Various embodiments rearrange the order of the above-described (and other) elements, remove some of these elements, and/or add other elements performing similar or different functions. Adding elements can include inserting elements in between existing elements, such as, for example, inserting amplifiers and an analog-to-digital converter. In various embodiments, the RF portion includes an antenna.

Additionally, the USB and/or HDMI terminals can include respective interface processors for connecting system 1000 to other electronic devices across USB and/or HDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, can be implemented, for example, within a separate input processing IC or within processor 1010 as necessary. Similarly, aspects of USB or HDMI interface processing can be implemented within separate interface ICs or within processor 1010 as necessary. The demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, processor 1010, and encoder/decoder 1030 operating in combination with the memory and storage elements to process the datastream as necessary for presentation on an output device.

Various elements of system 1000 can be provided within an integrated housing, Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangement, for example, an internal bus as known in the art, including the Inter-IC (I2C) bus, wiring, and printed circuit boards.

The system 1000 includes communication interface 1050 that enables communication with other devices via communication channel 1060. The communication interface 1050 can include, but is not limited to, a transceiver configured to transmit and to receive data over communication channel 1060. The communication interface 1050 can include, but is not limited to, a modem or network card and the communication channel 1060 can be implemented, for example, within a wired and/or a wireless medium.

Data is streamed, or otherwise provided, to the system 1000, in various embodiments, using a wireless network such as a Wi-Fi network, for example IEEE 802.11 (IEEE refers to the Institute of Electrical and Electronics Engineers). The Wi-Fi signal of these embodiments is received over the communications channel 1060 and the communications interface 1050 which are adapted for Wi-Fi communications. The communications channel 1060 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 1000 using a set-top box that delivers the data over the HDMI connection of the input block 1130. Still other embodiments provide streamed data to the system 1000 using the RF connection of the input block 1130. As indicated above, various embodiments provide data in a non-streaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network.

The system 1000 can provide an output signal to various output devices, including a display 1100, speakers 1110, and other peripheral devices 1120. The display 1100 of various embodiments includes one or more of, for example, a touchscreen display, an organic light-emitting diode (OLED) display, a curved display, and/or a foldable display. The display 1100 can be for a television, a tablet, a laptop, a cell phone (mobile phone), or other device. The display 1100 can also be integrated with other components (for example, as in a smart phone), or separate (for example, an external monitor for a laptop). The other peripheral devices 1120 include, in various examples of embodiments, one or more of a stand-alone digital video disc (or digital versatile disc) (DVR, for both terms), a disk player, a stereo system, and/or a lighting system. Various embodiments use one or more peripheral devices 1120 that provide a function based on the output of the system 1000. For example, a disk player performs the function of playing the output of the system 1000.

In various embodiments, control signals are communicated between the system 1000 and the display 1100, speakers 1110, or other peripheral devices 1120 using signaling such as AV.Link, Consumer Electronics Control (CEC), or other communications protocols that enable device-to-device control with or without user intervention. The output devices can be communicatively coupled to system 1000 via dedicated connections through respective interfaces 1070, 1080, and 1090. Alternatively, the output devices can be connected to system 1000 using the communications channel 1060 via the communications interface 1050. The display 1100 and speakers 1110 can be integrated in a single unit with the other components of system 1000 in an electronic device such as, for example, a television. In various embodiments, the display interface 1070 includes a display driver, such as, for example, a timing controller (T Con) chip.

The display 1100 and speaker 1110 can alternatively be separate from one or more of the other components, for example, if the RF portion of input 1130 is part of a separate set-top box. In various embodiments in which the display 1100 and speakers 1110 are external components, the output signal can be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs.

The embodiments can be carried out by computer software implemented by the processor 1010 or by hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments can be implemented by one or more integrated circuits. The memory 1020 can be of any type appropriate to the technical environment and can be implemented using any appropriate data storage technology, such as optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory, as non-limiting examples. The processor 1010 can be of any type appropriate to the technical environment, and can encompass one or more of microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as non-limiting examples.

Various implementations involve decoding. “Decoding”, as used in this application, can encompass all or part of the processes performed, for example, on a received encoded sequence to produce a final output suitable for display. In various embodiments, such processes include one or more of the processes typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transformation, and differential decoding. In various embodiments, such processes also, or alternatively, include processes performed by a decoder of various implementations described in this application.

As further examples, in one embodiment “decoding” refers only to entropy decoding, in another embodiment “decoding” refers only to differential decoding, and in another embodiment “decoding” refers to a combination of entropy decoding and differential decoding. Whether the phrase “decoding process” is intended to refer specifically to a subset of operations or generally to the broader decoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Various implementations involve encoding. In an analogous way to the above discussion about “decoding”, “encoding” as used in this application can encompass all or part of the processes performed, for example, on an input video sequence to produce an encoded bitstream. In various embodiments, such processes include one or more of the processes typically performed by an encoder, for example, partitioning, differential encoding, transformation, quantization, and entropy encoding. In various embodiments, such processes also, or alternatively, include processes performed by an encoder of various implementations described in this application.

As further examples, in one embodiment “encoding” refers only to entropy encoding, in another embodiment “encoding” refers only to differential encoding, and in another embodiment “encoding” refers to a combination of differential encoding and entropy encoding. Whether the phrase “encoding process” is intended to refer specifically to a subset of operations or generally to the broader encoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Note that the syntax elements as used herein are descriptive terms. As such, they do not preclude the use of other syntax element names.

When a figure is presented as a flow diagram, it should be understood that it also provides a block diagram of a corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow diagram of a corresponding method/process.

Various embodiments may refer to parametric models or rate distotion optimization. In particular, during the encoding process, the balance or trade-off between the rate and distortion is usually considered, often given the constraints of computational complexity. It can be measured through a Rate Distortion Optimization (RDO) metric, or through Least Mean Square (LMS), Mean of Absolute Errors (MAE), or other such measurements. Rate distortion optimization is usually formulated as minimizing a rate distortion function, which is a weighted sum of the rate and of the distortion. There are different approaches to solve the rate distortion optimization problem. For example, the approaches may be based on an extensive testing of all encoding options, including all considered modes or coding parameters values, with a complete evaluation of their coding cost and related distortion of the reconstructed signal after coding and decoding. Faster approaches may also be used, to save encoding complexity, in particular with computation of an approximated distortion based on the prediction or the prediction residual signal, not the reconstructed one. Mix of these two approaches can also be used, such as by using an approximated distortion for only some of the possible encoding options, and a complete distortion for other encoding options. Other approaches only evaluate a subset of the possible encoding options. More generally, many approaches employ any of a variety of techniques to perform the optimization, but the optimization is not necessarily a complete evaluation of both the coding cost and related distortion.

The implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program). An apparatus can be implemented in, for example, appropriate hardware, software, and firmware. The methods can be implemented in, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants (“PDAs”), and other devices that facilitate communication of information between end-users.

Reference to “one embodiment” or “an embodiment” or “one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” or “in one implementation” or “in an implementation”, as well any other variations, appearing in various places throughout this application are not necessarily all referring to the same embodiment.

Additionally, this application may refer to “determining” various pieces of information. Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, or retrieving the information from memory.

Further, this application may refer to “accessing” various pieces of information. Accessing the information can include one or more of, for example, receiving the information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.

Additionally, this application may refer to “receiving” various pieces of information. Receiving is, as with “accessing”, intended to be a broad term. Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory). Further, “receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are listed.

Also, as used herein, the word “signal” refers to, among other things, indicating something to a corresponding decoder. For example, in certain embodiments the encoder signals a particular one of a plurality of transforms, coding modes or flags. In this way, in an embodiment the same transform, parameter, or mode is used at both the encoder side and the decoder side. Thus, for example, an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as others, then signaling can be used without transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter. By avoiding transmission of any actual functions, a bit savings is realized in various embodiments. It is to be appreciated that signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word “signal”, the word “signal” can also be used herein as a noun.

As will be evident to one of ordinary skill in the art, implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted. The information can include, for example, instructions for performing a method, or data produced by one of the described implementations. For example, a signal can be formatted to carry the bitstream of a described embodiment. Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting can include, for example, encoding a data stream and modulating a carrier with the encoded data stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium.

We describe a number of embodiments, across various claim categories and types. Features of these embodiments can be provided alone or in any combination. Further, embodiments can include one or more of the following features, devices, or aspects, alone or in any combination, across various claim categories and types:

- A process or device to convey information pertinent to perform encoding and decoding with deep neural network compression of a pre-trained deep neural network.
- A process or device to convey information pertinent to perform encoding and decoding with inserted information in a bitstream representative of parameters to implement deep neural network compression of a pre-trained deep neural network comprising one or more layers.
- A process or device to convey information pertinent to perform encoding and decoding with inserted information in a bitstream representative of parameters to implement deep neural network compression of a pre-trained deep neural network until a compression criterion is reached.
- A bitstream or signal that includes one or more of the described syntax elements, or variations thereof.
- A bitstream or signal that includes syntax conveying information generated according to any of the embodiments described.
- Creating and/or transmitting and/or receiving and/or decoding according to any of the embodiments described.
- A method, process, apparatus, medium storing instructions, medium storing data, or signal according to any of the embodiments described.
- Inserting in the signaling syntax elements that enable the decoder to determine coding mode in a manner corresponding to that used by an encoder.
- Creating and/or transmitting and/or receiving and/or decoding a bitstream or signal that includes one or more of the described syntax elements, or variations thereof.
- A TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) according to any of the embodiments described.
- A TV, set-top box, cell phone, tablet, or other electronic device that performs transform method(s) determination according to any of the embodiments described, and that displays (e.g. using a monitor, screen, or other type of display) a resulting image.
- A TV, set-top box, cell phone, tablet, or other electronic device that selects, bandlimits, or tunes (e.g. using a tuner) a channel to receive a signal including an encoded image, and performs transform method(s) according to any of the embodiments described.
- A TV, set-top box, cell phone, tablet, or other electronic device that receives (e.g. using an antenna) a signal over the air that includes an encoded image, and performs transform method(s).

FRAMEWORK FOR CODING AND DECODING LOW RANK AND DISPLACEMENT RANK-BASED LAYERS OF DEEP NEURAL NETWORKS

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