The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
One aspect of the exemplary embodiments is a method for solving a general reduction problem, which is generalized as a divide-and-conquer problem for solving a problem on an instance of size n, by dividing the instance into two or more smaller instances. In another exemplary embodiment, the outermost loop is parallelized, which results in a performance improvement on multi-processor systems.
The exemplary embodiments of the present invention present a framework to solve a general reduction problem, which is generalized as a divide-and-conquer problem. In particular, solving a problem on an instance of size n, by dividing it into two or more smaller instances. Each of these smaller instances is recursively solved, and the solutions are combined to produce a solution for the original instance. The exemplary embodiments consist of scalar and array privatization analysis, general reduction recognition and type classification, parallelization, and reduction coalescing and aggregation.
Concerning scalar and array privatization on analysis a compiler performs scalar and array privatization analysis. The compiler finds those scalar variables whose definitions and references are closed in a loop iteration. Furthermore a single array data-flow analysis is used to determine arrays involved in data dependences, to locate private arrays and to recognize reductions. Array data-flow analysis is a bottom-up inter-procedural analysis on the loops and procedures of the program, using the region-based analysis framework.
Concerning general reduction detection through pattern matching, the exemplary embodiments use a pattern matching algorithm to identify the MAXLOC/MINLOC reduction using the form of an “if structure”. The absolute value operations are fully supported. The exemplary embodiments start from the innermost loop. Taking the code segment 12 in
Concerning the registering of the reduction, the reduction is added to the reduction list of the top-most nesting level. For extreme reductions, a reduction set may be required. Taking the code segment 12 in
in which u denotes the array element and i,j . . . denote the corresponding indices.
In case the two elements are equal, the index is kept unchanged, which is compatible with sequential logic.
Concerning parallel reduction code generation, a parallelizer generates three steps for each reduction variable in the reduction list of the loop: initialization, partitioning of the code among processors for partial sum, and finally sum up each partial sum result. In addition, the code segment 12 of
Finally, in the exemplary embodiments, the partial results are collected and summed up together by the master thread. The code segment 18 for summing up the partial results is shown in
The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.