Patent Application
20200412303
This disclosure generally relates to systems and methods for implementing an amplifier with an improved stability for feedback operation, including but not limited to a frequency compensation of a two stage or a higher stage amplifier.
Negative feedback amplifiers are prevalent in electronic devices. For example, a negative feedback amplifier is implemented to track an input signal or control an output signal according to the input signal. A negative feedback amplifier with a higher unity gain bandwidth (UGB) may track the input signal or control the output signal according to the input signal with a higher frequency.
In general, an amplifier design is subject to various trade-offs. For example, higher open loop gain may increase a UGB, but may shift a location of a pole to decrease a phase margin. An amplifier with an insufficient phase margin (e.g., less than 50 degrees) may cause the amplifier in a negative feedback configuration to be unstable. Conversely, reducing the opening loop gain may help improve the stability, but may reduce the UGB. For another example, increasing a dynamic range or a load current supplied by an amplifier changes a transconductance or a gain of the amplifier that may alter the unity bandwidth or the phase margin.
Various embodiments disclosed herein are related to an apparatus for a negative feedback. In some embodiments, the apparatus includes an input sensing circuit to generate an input signal. In some embodiments, the apparatus includes a cascode circuit coupled to the input sensing circuit. In some embodiments, the cascode circuit includes a first transistor and a second transistor coupled to each other in series. In some embodiments, the cascode circuit is configured to generate a first amplified signal by amplifying the input signal from the input sensing circuit. In some embodiments, the apparatus includes an amplifier circuit coupled to an output of the cascode circuit. In some embodiments, the amplifier circuit is configured to generate a second amplified signal by amplifying the first amplified signal. In some embodiments, the apparatus includes an output circuit coupled to an output of the amplifier circuit. In some embodiments, the output circuit is configured to generate an output signal by amplifying the second amplified signal. In some embodiments, the apparatus includes a first capacitor disposed across the second transistor, and a second capacitor coupled between the output circuit and the cascode circuit.
In some embodiments, the first capacitor is coupled between a first electrode of the second transistor and a second electrode of the second transistor. In some embodiments, the second capacitor is coupled between an output of the output circuit and the second electrode of the second transistor. In some embodiments, the second electrode of the second transistor is the output of the cascode circuit. In some embodiments, the apparatus further includes a third capacitor coupled between the output of the output circuit and a third electrode of the second transistor. In some embodiments, the input sensing circuit is directly coupled to the third electrode of the second transistor.
In some embodiments, the cascode circuit further includes a pair of buffer transistors, a third transistor, and a fourth transistor. In some embodiments, the first transistor, the second transistor, the pair of buffer transistors, the third transistor, and the fourth transistor are coupled to each other in series.
In some embodiments, the first transistor and the second transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors. In some embodiments, the pair of buffer transistors include an N-type transistor and a P-type transistor coupled to each other in parallel.
In some embodiments, the apparatus further includes a fourth capacitor coupled between a first electrode and a second electrode of the fourth transistor. In some embodiments, the apparatus further includes a fifth capacitor coupled between the second electrode of the fourth transistor and the output of the output circuit. In some embodiments, the apparatus further includes a sixth capacitor coupled between a third electrode of the fourth transistor and the output of the output circuit. In some embodiments, the apparatus further includes another amplifier circuit coupled between the second electrode of the fourth transistor and another input of the output circuit. In some embodiments, the input sensing circuit and the cascode circuit form a folded cascode amplifier.
In some embodiments, the apparatus further includes a switch coupled to the first capacitor in series across the second transistor. In some embodiments, the apparatus further includes a frequency compensation controller coupled to the output circuit, where the frequency compensation controller is configured to sense load current through the output circuit and enable or disable the switch according to the load current. In some embodiments, the amplifier circuit is configured to adjust an amplification gain for amplifying the first amplified signal according to a voltage at the output of the output circuit. In some embodiments, the amplifier circuit includes an input transistor including a gate electrode coupled to the output of the cascode circuit. In some embodiments, the amplifier circuit includes a diode connected transistor including a source electrode coupled to a source electrode of the input transistor, and a drain electrode coupled to a gate electrode of the diode connected transistor. In some embodiments, the drain electrode of the diode connected transistor is coupled to an input of the output circuit. In some embodiments, the apparatus includes a resistor coupled between the source electrode of the diode connected transistor and the drain electrode of the diode connected transistor.
Various embodiments disclosed herein are related to an apparatus for a negative feedback. In some embodiments, the apparatus includes a cascode circuit including a first transistor and a second transistor coupled to each other in series. In some embodiments, the cascode circuit is configured to generate a first amplified signal by amplifying an input signal. In some embodiments, the apparatus includes an amplifier circuit coupled to an output of the cascode circuit. In some embodiments, the amplifier circuit is configured to generate a second amplified signal by amplifying the first amplified signal. In some embodiments, the apparatus includes an output circuit coupled to an output of the amplifier circuit. In some embodiments, the output circuit is configured to generate an output signal by amplifying the second amplified signal. In some embodiments, the apparatus includes a first capacitor and a switch coupled to each other in series between a gate electrode of the second transistor and a drain electrode of the second transistor. In some embodiments, the apparatus includes a second capacitor coupled between an output of the output circuit and the drain electrode of the second transistor.
In some embodiments, the apparatus includes a frequency compensation controller coupled to the output circuit, where the frequency compensation controller is configured to sense load current through the output circuit and enable or disable the switch according to the load current. In some embodiments, the apparatus includes a third capacitor coupled between the output of the output circuit and a source electrode of the second transistor. In some embodiments, the amplifier circuit is configured to adjust an amplification gain for amplifying the first amplified signal according to a voltage at the output of the output circuit.
Various embodiments disclosed herein are related to a method of controlling a negative feedback system. In some embodiments, the method includes amplifying, by a cascode circuit including a first transistor and a second transistor coupled to each other in series, an input signal to generate a first amplified signal. In some embodiments, the method includes amplifying, by an amplifier circuit coupled to an output of the cascode circuit, the first amplified signal to generate a second amplified signal. In some embodiments, the method includes amplifying, by an output circuit coupled to an output of the amplifier circuit, the second amplified signal to generate an output signal. In some embodiments, the method includes adjusting, by the amplifier circuit, an amplification gain for amplifying the first amplified signal according to a load current through the output circuit.
In some embodiments, the method includes sensing, by a frequency compensation controller coupled to the output circuit, the load current through the output circuit. In some embodiments, the method includes enabling or disabling, by the frequency compensation controller, a switch coupled to the first capacitor in series across the second transistor according to the load current.
Various objects, aspects, features, and advantages of the disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.
The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below.
For purposes of reading the description of the various embodiments below, the following descriptions of the sections of the specification and their respective contents may be helpful:
Disclosed herein are related to various aspects of an apparatus and a method for implementing a negative feedback system with an improved stability and bandwidth. In some embodiments, the apparatus includes a cascode circuit including a first transistor and a second transistor coupled to each other in series. In some embodiments, the cascode circuit generates a first amplified signal by amplifying an input signal. In some embodiments, the apparatus includes an amplifier circuit coupled to an output of the cascode circuit. In some embodiments, the amplifier circuit generates a second amplified signal by amplifying the first amplified signal. In some embodiments, the apparatus includes an output circuit coupled to an output of the amplifier circuit. In some embodiments, the output circuit generates an output signal by amplifying the second amplified signal. In some embodiments, the apparatus includes a first capacitor disposed across the second transistor, and a second capacitor coupled between the output circuit and the cascode circuit.
Advantageously, the disclosed system and method allow frequency compensation of a two stage amplifier or a higher stage amplifier such that a high UGB and an improved stability can be achieved. In particular, a capacitor across a cascode transistor of the cascode circuit allows a high gain at a first frequency (e.g., near DC) and reduces gain at a second frequency higher than the first frequency, in some embodiments. In some embodiments, a cascode transistor is a transistor that is located away from an AC ground (e.g., supply voltage rail or ground voltage rail) from two or more transistors connected to each other in series in a cascode structure. Moreover, the capacitor may be adaptively coupled or decoupled across the transistor, according to a load current through the output circuit. Hence, a dynamic range of the amplifier can be improved by enabling or disabling frequency compensation or suppression of gain by the capacitor according to the load current without sacrificing the stability of the negative feedback system. Accordingly, the disclosed amplifier can be implemented in a negative configuration with faster tracking or better control.
Referring to
In some embodiments, the high-gain amplifier 120 receives the input signal 105 and a feedback signal 155, and amplifies a difference between the input signal 105 and the feedback signal 155 to generate the output signal 145. In one configuration, the high-gain amplifier 120 includes a first input port to receive the input signal 105, a second input port coupled to an output port of the feedback amplifier 150 to receive the feedback signal 155, and an output port to provide the output signal 145. The output port of the high-gain amplifier 120 may be coupled to a load (or another device), and the high-gain amplifier 120 may drive, provide, or supply current or voltage to the load through the output port. For example, the first stage amplifier 130 amplifies a difference between the input signal 105 and the feedback signal 155, and amplifies the difference to generate an intermediate signal 135, and the second stage amplifier 140 amplifies the intermediate signal 135 to generate the output signal 145. In one aspect, the second stage amplifier 140 may be referred to as “an output circuit” that provides the output voltage, output current or both. The intermediate signal 135 and the output signal 145 may be in a single ended representation or in a differential representation.
In some embodiments, the feedback amplifier 150 receives the output signal 145 from the high-gain amplifier 120, and generates the feedback signal 155 according to the output signal 145. In one configuration, the feedback amplifier 150 includes an input port coupled to the output port of the high-gain amplifier 120 to receive the output signal 145 and the output port coupled to the second input port of the high-gain amplifier 120 to provide the feedback signal 155. In some embodiments, the feedback amplifier 150 receives the output signal 145 and amplifies the output signal 145 by a feedback factor (e.g., less than ‘1’, equal to ‘1’, or larger than ‘1’) to generate the feedback signal 155. In one aspect, through the negative feedback operation of the high-gain amplifier 120 and the feedback amplifier 150, the output signal 145 can track the input signal 105 or can be controlled according to the input signal 105, if a frequency of the input signal 105 is less than a UGB of the system 100. In one aspect, a high UGB (e.g., over 100 MHz or 1 GHz) of the system 100 with improved stability can be achieved through the disclosed feedback compensation as disclosed below.
Referring to
The transistors Tp1, Tp2, Tp3 operate together to sense a voltage difference between the input voltages Vin1, Vin2, in one or more embodiments. In one configuration, a source electrode of the transistor Tp1 is coupled to a supply voltage rail to receive a first reference voltage (e.g., VDD or 1.2V), and a gate electrode of the transistor Tp1 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbpcas1. In one configuration, a drain electrode of the transistor Tp1 is coupled to a source electrode of the transistor Tp2 and a source electrode of the transistor Tp3. In one configuration, a gate electrode of the transistor Tp2 is configured to receive the input voltage Vin1, and a drain electrode of the transistor Tp2 is directly or indirectly coupled to a node n11. In one configuration, a gate electrode of the transistor Tp3 is configured to receive the input voltage Vin2, and a drain electrode of the transistor Tp3 is directly or indirectly coupled to a node n21. In this configuration, the transistor Tp1 operates as a current source that supplies current to the source electrodes of the transistors Tp2, Tp3, according to the bias voltage Vbpcas1. In this configuration, the transistors Tp2, Tp3 operate as a differential pair input sensing circuit that senses a difference between the input voltages Vin1, Vin2, and steers current from the transistor Tp1 according to the sensed voltage difference to provide sensed current Ierr1 and Ierr2. For example, in response to the input voltage Vin1 being higher than the input voltage Vin2, more current is injected to the transistor Tp3 than the transistor Tp2. For another example, in response to the input voltage Vin2 being higher than the input voltage Vin1, more current is injected to the transistor Tp2 than the transistor Tp3.
In some embodiments, the transistors Tn11, Tn12, Tn13, Tn21, Tn22, Tn23, Tp11, Tp12, Tp13, Tp21, Tp22, Tp23 operate together to receive the sensed currents Ierr1 and Ierr2, and convert the sensed currents Ierr1 and Ierr2 into voltages at the nodes n12, n13, n22, n23. In one aspect, the transistors Tn11, Tn12, Tp11, Tp12 are coupled to each other in series and may operate together as a half circuit to receive the sensed current Ierr1 and convert the sensed current Ierr1 into corresponding voltages at the nodes n12, n13. The transistors Tn13 and Tp13 may operate together as a buffer between the nodes n12, n13. Similarly, the transistors Tn21, Tn22, Tp21, Tp22 are coupled to each other in series and may operate together as the other half circuit to receive the sensed current Ierr2 and convert the sensed current Ierr2 into corresponding voltages at the nodes n22, n23. The transistors Tn23 and Tp23 may operate together as buffer between the nodes n22, n23.
In one configuration, a source electrode of the transistor Tn11 is coupled to a ground voltage rail to receive a second reference voltage (e.g., GND or 0V), a gate electrode of the transistor Tn11 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbn1, and a drain electrode of the transistor Tn11 is coupled to a node n11. In one configuration, a source electrode of the transistor Tn12 is coupled to the node n11, a gate electrode of the transistor Tn12 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbncas1, and a drain electrode of the transistor Tn12 is coupled to the node n12. In this configuration, the sensed current Ierr1 is injected into the node n11, and the sensed current Ierr1 is converted into a voltage by the transistors Tn11, Tn12 at the node n12. In one aspect, the transistors Tn11, Tn12 are connected to each other in series to form a cascode structure or a cascode circuit with the transistor Tn12 being a cascode transistor to provide a high output impedance at the node n12 to render a high voltage gain between a voltage at the node n12 and the input voltage Vin1.
In one aspect, the transistors Tn13, Tp13 are coupled to each other in parallel between the nodes n12, n13. In one configuration, a source electrode of the transistor Tn13 is coupled to the node n12, a gate electrode of the transistor Tn13 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbncas2, and a drain electrode of the transistor Tn13 is coupled to the node n13. In one configuration, a source electrode of the transistor Tp13 is coupled to the node n13, a gate electrode of the transistor Tp13 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbpcas2, and a drain electrode of the transistor Tp13 is coupled to the node n12. In this configuration, the transistors Tn13, Tp13 operate as a pair of buffer transistors between the nodes n12, n13 to separate the voltages at the nodes n12, n13.
In one configuration, a source electrode of the transistor Tp11 is coupled to the supply voltage rail to receive the first reference voltage (e.g., VDD or 1.2V), a gate electrode of the transistor Tp11 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbp1, and a drain electrode of the transistor Tp11 is coupled to a node n14. In one configuration, a source electrode of the transistor Tp12 is coupled to the node n14, a gate electrode of the transistor Tp12 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbpcas1, and a drain electrode of the transistor Tp12 is coupled to the node n13. In this configuration, current flowing through the transistor Tn12 according to the sensed current Ierr1 at the node n11 may flow through the transistors Tp11, Tp12 or cause a corresponding amount of current to flow through the transistors Tp11, Tp12. In one aspect, the transistors Tp11, Tp12 are connected to each other in series to form a cascode structure or a cascode circuit with the transistor Tp12 being a cascode transistor to provide a high output impedance at the node n13 to render a high voltage gain between a voltage at the node n13 and the input voltage Vin1.
In some embodiments, the transistors Tn21, Tn22, Tn23, Tp21, Tp22, Tp23 are configured and operate in a similar manner as the transistors Tn11, Tn12, Tn23, Tp11, Tp12, Tp13, such that the transistors Tn11, Tn12, Tn13, Tp11, Tp12, Tp13 operate as the half circuit, and the transistors Tn21, Tn22, Tn23, Tp21, Tp22, Tp23 operate as the other half circuit. For example, the sensed current Ierr2 can be injected at the node n21 and converted into voltages at the nodes n22, n23 by the transistors Tn21, Tn22, Tn23, Tp21, Tp22, Tp23. Thus, duplicated description thereof is omitted herein for the sake of brevity.
Referring to
In some embodiments, the transistors Tn31, Tn32, Tn33, Tn41, Tn42, Tn43, Tp31, Tp32, Tp33, Tp41, Tp42, Tp43 operate together to receive the voltages Vpi1, Vpi2, Vni1, Vni2, and amplify the received voltages to generate output voltages Vout1, Vout2 at the nodes n33, n43. In one aspect, the transistors Tn31, Tn32, Tn33, Tp31, Tp32, Tp33 are coupled to each other in series and may operate together as a half circuit to receive the voltages Vni1, Vpi1, and amplify the voltages Vni1, Vpi1 to generate the output voltage Vout1 at the node n33. Similarly, the transistors Tn41, Tn42, Tn43, Tp41, Tp42, Tp43 are coupled to each other in series and may operate together as the other half circuit to receive the voltages Vni2, Vpi2, and amplify the voltages Vni2, Vpi2 to generate the output voltage Vout2 at the node n43.
In one configuration, a source electrode of the transistor Tn31 is coupled to the ground voltage rail to receive the second reference voltage (e.g., GND or 0V), a gate electrode of the transistor Tn31 is configured to receive the voltage Vni1, and a drain electrode of the transistor Tn31 is coupled to a node n31. In one configuration, a source electrode of the transistor Tn32 is coupled to the node n31, a gate electrode of the transistor Tn32 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbncas3, and a drain electrode of the transistor Tn32 is coupled to the node n32. In one configuration, a source electrode of the transistor Tn33 is coupled to the node n32, a gate electrode of the transistor Tn33 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbncas4, and a drain electrode of the transistor Tn33 is coupled to the node n33. In this configuration, the transistors Tn31, Tn32, Tn33 are connected to each other in series to form a cascode structure to amplify the voltage Vni1 to generate the output voltage Vout1 at the node n33.
In one configuration, a source electrode of the transistor Tp31 is coupled to the supply voltage rail to receive the first reference voltage (e.g., VDD or 1.2V), a gate electrode of the transistor Tp31 is configured to receive the voltage Vpi1, and a drain electrode of the transistor Tp31 is coupled to a node n35. In one configuration, a source electrode of the transistor Tp32 is coupled to the node n35, a gate electrode of the transistor Tp32 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbpcas3, and a drain electrode of the transistor Tp32 is coupled to the node n34. In one configuration, a source electrode of the transistor Tp33 is coupled to the node n34, a gate electrode of the transistor Tp33 is coupled to a bias device (not shown for simplicity) to receive a bias voltage Vbpcas4, and a drain electrode of the transistor Tp33 is coupled to the node n33. In this configuration, the transistors Tp31, Tp32, Tp33 are connected to each other in series to form a cascode structure to amplify the voltage Vpi1 to generate the output voltage Vout1 at the node n33. In one aspect, the transistors Tp31, Tp32, Tp33 are configured and operate as a counter part of the transistors Tn31, Tn32, Tn33.
In some embodiments, the transistors Tn41, Tn42, Tn43, Tp41, Tp42, Tp43 are configured and operate in a similar manner as the transistors Tn31, Tn32, Tn33, Tp31, Tp32, Tp33, such that the transistors Tn31, Tn32, Tn33, Tp31, Tp32, Tp33 operate as the half circuit, and the transistors Tn41, Tn42, Tn43, Tp41, Tp42, Tp43 operate as the other half circuit. In one aspect, the voltages Vni2, Vpi2 are amplified by the transistors Tn41, Tn42, Tn43, Tp41, Tp42, Tp43 to generate the output voltage Vout2 at the node n43. Thus, duplicated description thereof is omitted herein for the sake of brevity.
Referring to
The amplifier Ap can be or correspond to a component that receives the voltage at the node n13 of the first stage amplifier 140, and amplifies the voltage at the node n13 to generate the voltage Vpi1. In one configuration, the amplifier Ap is coupled between the node n13 and the gate electrode of the transistor Tp31. The amplifier Ap may be implemented or operate as a buffer or a level shifter to bias the transistor Tp31. In this configuration, the amplifier Ap may amplify the voltage at the node n13 according to an amplification gain of the amplifier Ap to generate the voltage Vpi1. The amplification gain may be predetermined or adjustable. In one aspect, the amplification gain is adaptively adjusted according to the output voltage Vout1 or according to the load current through the output circuit (e.g., the second stage amplifier 140) to improve stability. Detailed description on the implementation and the operation of the amplifier Ap is provided below with respect to
The amplifier An is a component that receives the voltage at the node n12 of the first stage amplifier 140, and amplifies the voltage at the node n12 to generate the voltage Vni1. In one configuration, the amplifier An is coupled between the node n12 and the gate electrode of the transistor Tn31. The amplifier An may be implemented or operate as a buffer or a level shifter to bias the transistor Tn31. In this configuration, the amplifier An may amplify the voltage at the node n12 according to an amplification gain of the amplifier An to generate the voltage Vni1. The amplification gain may be predetermined or adjustable. In one aspect, the amplification gain is adaptively adjusted according to the output voltage Vout1 or according to the load current through the output circuit (e.g., the second stage amplifier 140). The amplifier An may be implemented in a similar manner as the amplifier Ap with counterpart components (e.g., N-type transistors instead of P-type transistors or P-type transistors instead of N-type transistors).
The capacitors Cca1, Cca2, Ccm1, Ccm2 can be or correspond to components for providing feedback from the second stage amplifier 140 to the first stage amplifier 130. In some embodiments, the capacitors Cca1, Cca2, Ccm1, Ccm2 may be implemented as metal-insulator-metal capacitors, metal-oxide-metal capacitors or any capacitors. In one configuration, the capacitor Cca1 is coupled between the node n11 and the node n33, and the capacitor Ccm1 is coupled between the node n12 and the node n33. Similarly, in one configuration, the capacitor Cca2 is coupled between the node n14 and the node n33, and the capacitor Ccm2 is coupled between the node n13 and the node n33. In one aspect, the amplification gains of the amplifiers An and Ap may help improve the DC gain of the high-gain amplifier 120, but the amplifiers An and Ap may introduce or create poles that degrade the phase margin of the high-gain amplifier 120. In one aspect, the capacitors Cca1, Cca2, Ccm1, Ccm2 allow feedback to improve phase margin of the high-gain amplifier 120, thereby improving the stability of the system 100.
Referring to
In one aspect, the high-gain amplifier 120 implementing the connection between the first stage amplifier 130 and the second stage amplifier 140 as shown in
Advantageously, the capacitors Ccas1, Ccas2 across the cascode transistors Tn12, Tp12 may improve the stability of the system 100. In particular, the cascode structures of the first stage amplifier 130 and the second stage amplifier 140 may allow a high gain under no load or low current condition. Moreover, the capacitors Ccas1, Ccas2 with the capacitors Cca1, Cca2 may help improve the stability of the inner loop by pushing a non-dominant pole to a higher frequency under high current and/or high slew-rate conditions. Moreover, under large load current, the capacitors Ccas1, Ccas2 with the capacitors Ccm1, Ccm2 may help improve the stability of the inner loop by introducing a zero, under high current, and/or high slew-rate conditions. In one implementation, a capacitor may be added between the node n12 and the ground voltage rail and another capacitor may be added between the node n13 and the supply voltage rail to help improve stability. However, such implementation may not have an effect of improving the stability of the inner loop, for example, by pushing the non-dominant pole to a higher frequency according to the capacitors Ccas1, Ccas2 as shown in
Referring to
In one aspect, the frequency compensation controller 610 may detect a load current through the second stage amplifier 140 (or the output circuit), and configure the switches SW1, SW2 to improve stability of the system 100. The frequency compensation controller 610 may detect current through the second stage amplifier 140 (or the output circuit) by implementing another current path mirroring the second stage amplifier 140, and detecting a current flow through the another current path. Alternatively, the frequency compensation controller 610 may detect a disturbance at one or more of the voltages Vbncas3, Vbpcas3, and detect a current through the second stage amplifier 140 according to the detected disturbance. In response to the frequency compensation controller 610 detecting a low load current less than a predetermined threshold through the second stage amplifier 140 (or in response to detecting a low slew rate), the frequency compensation controller 610 may disable the switches SW1, SW2 such that an electrode of the capacitor Ccas1 is electrically decoupled from the cascode transistor Tn12 and an electrode of the capacitor Ccas2 is electrically decoupled from the cascode transistor Tp12. In response to the frequency compensation controller 610 detecting a high load current over a predetermined threshold through the second stage amplifier 140 (or in response to detecting a high slew rate), the frequency compensation controller 610 may enable the switches SW1, SW2 such that the capacitor Ccas1 is electrically coupled across the cascode transistor Tn12 and the capacitor Ccas2 is electrically coupled across the cascode transistor Tp12. Accordingly, the UGB of the system 100 and the stability of the system 100 may be improved, by increasing a transconductance of the output circuit (or the second stage amplifier 140) under low load current or low slew rate conditions, and by decreasing a transconductance of the output circuit (or the second stage amplifier 140) under a high load current or high slew rate conditions.
Referring to
In one configuration, the resistor R1 includes a first electrode coupled to the supply voltage rail to receive the first reference voltage (e.g., VDD or 1.2V) and a second electrode coupled to a node na2. In one configuration, the transistor Tpa1 includes a source electrode coupled to the node na2, a gate electrode to receive the input voltage VIn_A, and a drain electrode coupled to a node na1. In one configuration, the transistor Tpa2 includes a source electrode coupled to the node na2, a gate electrode coupled to a node na3, and a drain electrode coupled to the node na3 to form a diode-connected configuration. In one configuration, the resistor R0 includes a first electrode coupled to the node na2 and a second electrode coupled to the node na3. In one configuration, the transistor Tpa3 includes a source electrode coupled to the supply voltage rail to receive the first reference voltage (e.g., VDD or 1.2V), a gate electrode coupled to the node na1, and a drain electrode coupled to the node na3. In one configuration, the capacitor Ca is coupled between the node na1 and the node na3. In one configuration, the transistor Tna1 includes a source electrode coupled to the ground voltage rail to receive the second reference voltage (e.g., GND or 0V), a gate electrode to receive the bias voltage Vbncas1, and a drain electrode coupled to the node na1. In one configuration, the transistor Tna2 includes a source electrode coupled to the ground voltage rail to receive the second reference voltage (e.g., GND or 0V), a gate electrode to receive the bias voltage Vbncas1, and a drain electrode coupled to the node na3.
In this configuration, a voltage gain of the amplifier 700 is adaptively adjusted according to a load current through the output circuit (or the second stage amplifier). The transistor Tpa1 may sense the input voltage VIn_A (e.g., a voltage at the node n13 of
Referring to
In one approach, the system 100 amplifies 810 an input signal to generate a first amplified signal. In one aspect, the first stage amplifier 130 may include a first transistor (e.g., Tn11) and a second transistor (Tn12) coupled to each other in series in a cascode structure, where the second transistor operates as a cascode transistor. In one approach, a current corresponding to the input signal may be injected to a node between the first transistor and the second transistor, and converted into a voltage by a high output impedance at the cascode transistor to amplify the input signal.
In one approach, the system 100 amplifies 820 the first amplified signal to generate a second amplified signal by amplifying the first amplified signal. In one implementation, an additional amplifier (e.g., amplifier Ap or amplifier An) may be implemented between the first stage amplifier 130 and the second stage amplifier 140 to increase the gain further. In one aspect, the additional amplifier may have an adjustable gain. The additional amplifier may amplify the first amplified signal according to a predetermined gain to generate the second amplified signal. In one approach, the system 100 amplifies 830 the second amplified signal to generate an output signal. In one approach, the second stage amplifier 140 may include transistors having a cascode structure to amplify the second amplified signal with a high gain to generate the output signal.
In one approach, the system 100 adjusts 840 an amplification gain for amplifying the first amplified signal, for example, according to a load current through the output circuit (or the second stage amplifier). The additional amplifier may detect the load current by sensing a voltage at an output of the additional amplifier or at an input of the output circuit. The additional amplifier may reduce the gain of the additional amplifier, in response to detecting the load current exceeding a predetermined threshold. The additional amplifier may increase the gain of the additional amplifier, in response to detecting the load current not exceeding the predetermined threshold. Accordingly, the UGB of the system 100 and the stability of the system 100 may be improved, by increasing a gain of the additional amplifier under low load current or low slew rate conditions, and by decreasing a gain of the additional amplifier under a high load current or high slew rate conditions.
Having discussed specific embodiments of the present solution, it may be helpful to describe aspects of the operating environment as well as associated system components (e.g., hardware elements) in connection with the methods and systems described herein. Referring to
The network devices 906 may be operably coupled to the node 992 via local area network connections. The node 992, which may include a router, gateway, switch, bridge, modem, system controller, appliance, etc., may provide a local area network connection for the communication system. Each of the network devices 906 may have an associated antenna or an antenna array to communicate with the communication devices 902 in its area. The communication devices 902 may register with a particular network device 906 to receive services from the communication system (e.g., via a SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communications), some communication devices 902 may communicate directly via an allocated channel and communications protocol. Some of the communication devices 902 may be mobile or relatively static with respect to the network device 906.
In some embodiments a network device 906 includes a device or module (including a combination of hardware and software) that allows communication devices 902 to connect to a wired network using Wi-Fi, or other standards. A network device 906 may be configured, designed, and/or built for operating in a wireless local area network (WLAN). A network device 906 may connect to a router (e.g., via a wired network) as a standalone device in some embodiments. In other embodiments, a network device can be a component of a router. A network device 906 can provide multiple devices 902 access to a network. A network device 906 may, for example, connect to the devices 902 through a wired Ethernet connection, a wireless Wi-Fi connection, or both. A network device 906 may be built and/or configured to support a standard for sending and receiving data using one or more radio frequencies. Those standards, and the frequencies they use may be defined by the IEEE (e.g., IEEE 802.11 standards). A network device may be configured and/or used to support public Internet hotspots, and/or on an internal network to extend the network's Wi-Fi signal range.
In some embodiments, the network devices 906 may be used for (e.g., in-home or in-building) wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency based network protocol and/or variations thereof). Each of the communication devices 902 may include a built-in radio and/or is coupled to a radio. Such communication devices 902 and/or network devices 906 may operate in accordance with the various aspects of the disclosure as presented herein to enhance performance, reduce costs and/or size, and/or enhance broadband applications. Each communication devices 902 may have the capacity to function as a client node seeking access to resources (e.g., data, and connection to networked nodes such as servers) via one or more network devices 906.
The network connections may include any type and/or form of network and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communication network, and a computer network. The topology of the network may be a bus, star, or ring network topology. The network may be of any such network topology as known to those ordinarily skilled in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same types of data may be transmitted via different protocols.
The node 992, the communications device(s) 902 and network device(s) 906 may be deployed as and/or executed on any type and form of computing device, such as a computer, network device or appliance capable of communicating on any type and form of network and performing the operations described herein.
The central processing unit 921 is any logic circuitry that responds to and processes instructions fetched from the main memory unit 922. In many embodiments, the central processing unit 921 is provided by a microprocessor unit, such as: those manufactured by Intel Corporation of Santa Clara, Calif.; those manufactured by International Business Machines of White Plains, N.Y.; or those manufactured by Advanced Micro Devices of Sunnyvale, Calif. The computing device 900 may be based on any of these processors, or any other processor capable of operating as described herein.
Main memory unit 922 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the microprocessor 921, such as any type or variant of Static random access memory (SRAM), Dynamic random access memory (DRAM), Ferroelectric RAM (FRAM), NAND Flash, NOR Flash and Solid State Drives (SSD). The main memory 922 may be based on any of the above described memory chips, or any other available memory chips capable of operating as described herein. In the embodiment shown in
A wide variety of I/O devices 930a-930n may be present in the computing device 900. Input devices include keyboards, mice, trackpads, trackballs, microphones, dials, touch pads, touch screen, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye-sublimation printers. The I/O devices may be controlled by an I/O controller 923 as shown in
Referring again to
Furthermore, the computing device 900 may include a network interface 918 to interface to the network 904 through a variety of connections including, but not limited to, standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56 kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet-over-SONET), wireless connections, or some combination of any or all of the above. Connections can be established using a variety of communication protocols (e.g., TCP/IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax and direct asynchronous connections). In one embodiment, the computing device 900 communicates with other computing devices 900′ via any type and/or form of gateway or tunneling protocol such as Secure Socket Layer (SSL) or Transport Layer Security (TLS). The network interface 918 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem or any other device suitable for interfacing the computing device 900 to any type of network capable of communication and performing the operations described herein.
In some embodiments, the computing device 900 may include or be connected to one or more display devices 924a-924n. As such, any of the I/O devices 930a-930n and/or the I/O controller 923 may include any type and/or form of suitable hardware, software, or combination of hardware and software to support, enable or provide for the connection and use of the display device(s) 924a-924n by the computing device 900. For example, the computing device 900 may include any type and/or form of video adapter, video card, driver, and/or library to interface, communicate, connect or otherwise use the display device(s) 924a-924n. In one embodiment, a video adapter may include multiple connectors to interface to the display device(s) 924a-924n. In other embodiments, the computing device 900 may include multiple video adapters, with each video adapter connected to the display device(s) 924a-924n. In some embodiments, any portion of the operating system of the computing device 900 may be configured for using multiple displays 924a-924n. One ordinarily skilled in the art will recognize and appreciate the various ways and embodiments that a computing device 900 may be configured to have one or more display devices 924a-924n.
In further embodiments, an I/O device 930 may be a bridge between the system bus 950 and an external communication bus, such as a USB bus, an Apple Desktop Bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 900 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a FibreChannel bus, a Serial Attached small computer system interface bus, a USB connection, or a HDMI bus.
A computing device 900 of the sort depicted in
The computer system 900 can be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile telephone or other portable telecommunications device, media playing device, a gaming system, mobile computing device, or any other type and/or form of computing, telecommunications or media device that is capable of communication. The computer system 900 has sufficient processor power and memory capacity to perform the operations described herein.
In some embodiments, the computing device 900 may have different processors, operating systems, and input devices consistent with the device. For example, in one embodiment, the computing device 900 is a smart phone, mobile device, tablet or personal digital assistant. In still other embodiments, the computing device 900 is an Android-based mobile device, an iPhone smart phone manufactured by Apple Computer of Cupertino, Calif., or a Blackberry or WebOS-based handheld device or smart phone, such as the devices manufactured by Research In Motion Limited. Moreover, the computing device 900 can be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile telephone, any other computer, or other form of computing or telecommunications device that is capable of communication and that has sufficient processor power and memory capacity to perform the operations described herein.
Although the disclosure may reference one or more “users”, such “users” may refer to user-associated devices, for example, consistent with the terms “user” and “multi-user” typically used in the context of a multi-user multiple-input and multiple-output (MU-MIMO) environment.
Although examples of communications systems described above may include devices and network devices operating according to PAM4 DFE protocol, it should be understood that embodiments of the systems and methods described can operate according to other standards.
It should be noted that certain passages of this disclosure may reference terms such as “first” and “second” in connection with devices, mode of operation, transmit chains, antennas, etc., for purposes of identifying or differentiating one from another or from others. These terms are not intended to merely relate entities (e.g., a first device and a second device) temporally or according to a sequence, although in some cases, these entities may include such a relationship. Nor do these terms limit the number of possible entities (e.g., devices) that may operate within a system or environment.
It should be understood that the systems described above may provide multiple ones of any or each of those components and these components may be provided on either a standalone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture. The article of manufacture may be a floppy disk, a hard disk, a CD-ROM, a flash memory card, a PROM, a RAM, a ROM, or a magnetic tape. In general, the computer-readable programs may be implemented in any programming language, such as LISP, PERL, C, C++, C #, PROLOG, or in any byte code language such as JAVA. The software programs or executable instructions may be stored on or in one or more articles of manufacture as object code.
While the foregoing written description of the methods and systems enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The present methods and systems should therefore not be limited by the above described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the disclosure.
