Patent Application
20120062299
(Invention A): The present invention relates to technique to compare second frequency signal (in this first frequency signal predetermined time delayed signal) with first frequency signal (detecting signal), specifically, relates to the frequency detection apparatus (and frequency detection methods) which can judge that frequency of first frequency signal reached predetermined value.
(Invention B): For example, the present invention relates to technique to detect, (a) input current (input current of the electric circuit such as power inverter circuits), (b) the input voltage, (c) output current, (d) output voltage, (e) reactor voltage, (f) reactor current, (g) voltage between terminals of the electric switch, (h) switch current, (i) diode (commutation diode, rectifier diode) voltage , and (k) diode current, specifically, the present invention relates to a good controlled electric circuit controller (and an electric circuit control method). Even more particularly, the present invention relates to an electric circuit comprising the frequency detecting circuit which converts a detection level into frequency signal, specifically, relates to an electric circuit controller (and an electric circuit control method) which can judge changes (frequency of the frequency signal having changed in a predetermined level or the frequency of the cover detecting signal having reached the predetermined value) such as current or the voltage by simple structure.
(Invention C): The present invention relates to the delay circuit (and a delay circuit system) comprising a plurality of impedance circuits connected to a gland in the path of the input signal, specifically, relates to a delay circuit (and a delay circuit system) which minute delay can be generated and can perform a circuit design easily.
(Invention A): A technique to detect that frequency of the measuring signal reached reference frequency is known conventionally. In this technique, at first the periodic signal of the reference is generated, and, then, the phase of this reference periodic signal and the phase of the measuring signal are compared. In this kind of technique, Recursive Discrete Fourier Transform may be used (patent document 1). Also, an AFC (Automatic Frequency Control) loop may be used (patent document 2).
(Invention B): As shown in
The periodic signal generation circuit 92 inputs an output signal from power converters 91, and converts this voltage value into a periodic signal. Driving signal generation circuit 93 has average calculation circuit. Average calculation circuit counts signal input from the periodic signal generation circuit 92. Average calculation circuit calculates mean value of predetermined period of output voltage. Driving signal generation circuit 93 drives an electric switch of power converters 91 depending on a calculation result of the averaging circuit.
(Invention C): The delay circuits are usually comprised of a large number of delay elements performed series connection of, the delayed signals are acquired by a tap provided between each elements. Detecting circuit integrates input signal of rectangular wave, when capacitor voltage to comprise integrating circuit reached the threshold, delayed signals occur.
Method to generate delayed signals is shown in
Selective circuit 82 selects one or more lines from a plurality of lines (line group 83). Different signal (original signal SO, delayed signals S1, S2, . . . , either of SN) of the delay time is thereby taken out.
(Invention A): In each conventional technique, reference signal generator, phase detector are necessary. Thus, there is problem that overall circuit is complicated.
(Invention B): As mentioned earlier, using the power conversion equipment 9 of
That is, by the conventional control (control of the voltage-controlled power conversion equipment and control of the current control type power conversion equipment), instantaneous value of the voltage and instantaneous value of the current peak cannot be detected. Thus, highly precise control was not able to be simplified.
(Invention C): A delay formative element must be used more than 1000 to raise resolution with the delay circuit of
In reality, it is not easy to set the delay time precisely (e.g., setting a large number of delay every several nanoseconds). In manufacturing process of integrated circuit, delay formative elements 81 (1)-81 (N) 1,000 or more must be made on semiconductor substrate as described above. Distance between each delay formative elements must be the same as possible as described above, besides. Also, length of each lines from each delay formative element to selective circuit 82 must be made the same as much as possible as described above. Thus, pattern design of integrated circuit is extremely difficult.
(Object of “invention A”): Object of “invention A”(the frequency detection apparatus and frequency detection methods) is to compare second periodic signal (signal which delayed from measurement signal for predetermined time)with first periodic signal (measurement signal), and is to judge that the frequency have dropped in predetermined value of the low level side.
(Object of “invention B”): Object of “invention B” is that change (frequency of measurement signal having risen to predetermined value of the high pass side) of the control parameter can be determined in simple structure and highly precise control provides the power conversion equipment which it is possible for.
Other objects of “invention B” are to provide control method of the power conversion equipment. Other objects of “invention B” is that change (frequency of measurement signal having fallen to predetermined value of drop direction side) of the control parameter can be determined in simple structure and highly precise control provides the power conversion equipment which it is possible for. Other object of “invention B” is to provide control method of the power conversion equipment.
(Object of “invention C”): Object of “invention C” is accuracy generates high delay and to provide delay circuit that circuit design is easy and delay circuit system.
(Invention A): In the frequency detection apparatus comprising the delayed signal output circuit and judgment circuit, the delayed signal output circuit outputs second periodic signal which delayed in first periodic signal that frequency changes at time for predetermined time, the judgment circuit inputs first periodic signal and second periodic signal, the judgment circuit detects it whether first period period of a signal was included for second period period of a signal and/or whether above second period period of a signal was included for above first period period of a signal, and judge signal is output,
The delayed signal output circuit outputs second periodic signal which delayed in first periodic signal that frequency changes at time for predetermined time, the judgment circuit inputs first periodic signal and second periodic signal, detects whether first period included period of a signal for period of a signal in second period, and judgment signal is output, and/or, the judgment circuit detects whether second period included period of a signal for period of a signal in first period, and judgment signal is output.(???????????)
The delayed signal output circuit can be comprised by analog circuit. Also, the delayed signals output circuit can be comprised by a digital circuit. In delay time, it can be set appropriately. The first periodic signal (measuring signal) is typically a narrow width pulse string, rectangular wave, serrulation wave, triangular wave, sine wave.
Pulse separation changes when first periodic signal is narrow width pulse string.
When the narrow width pulse string of first periodic signal is an original or negative pulse, the judgment circuit detects whether the narrow width pulse of first periodic signal and the narrow width pulse of second periodic signal are input alternately. And the judgment circuit is judged to be it whether second period period of a signal is included for first period period of a signal.
Alternatively, the judgment circuit is judged to be it whether first period period of a signal is included for second period period of a signal. For example, the judgment circuit detects only a positive pulse or a negative pulse as first periodic signal, and a positive pulse and the case including two pulses of the negative pulse can output judgment signal to one period a narrow width pulse string.
The judgment circuit can be judged when first periodic signal is squarewave whether first period includes period of a signal by an edge (a positive going edge or a negative-going edge) in second period for period of a signal. Alternatively, the judgment circuit can be judged whether period of a signal is included by the edge in first period for period of a signal in second period. The judgment circuit can be judged when first periodic signal is serrulation wave whether first period includes period of a signal by an edge (or a maximum of the serrulation amplitude of wave) in second period for period of a signal. Alternatively, the judgment circuit can be judged whether the period of first pulse is included for period of a signal in second period.
When first periodic signal is a triangular wave and a sine wave, the judgment circuit can be judged whether period of a signal is included by a peak (a maximum and a minimum) in second period for period of a signal in first period. Also, the judgment circuit can be judged whether first period includes period of a signal by a zero point in second period for period of a signal. The judgment circuit can be judged whether period of a signal is included by a zero point in first period for period of a signal in second period. In “invention A”, it can be determined to have changed into a predetermined level of the high pass side by frequency. In “invention A”, it can be determined to have reached the set value of the rise direction side by frequency. The frequency at that time is reciprocal of the delay time. Thus, when delay time is determined by at least one detection level, that frequency changes in a predetermined level of the high pass side or frequency changed into a predetermined level of the low level side can be detected.
(2) The frequency detection apparatus as claimed in (1), wherein, the judgment circuit detects time when first period included period of a signal for period of a signal in second period, thereby, judges that the frequency of first periodic signal changed in a predetermined level of the high pass side or that it rose to the predetermined value, and/or, the judgment circuit detects time when second period included period of a signal for period of a signal in first period, thereby, judges that the frequency of first periodic signal changed in a predetermined level of the low level side or that it dropped in predetermined value, a frequency detection apparatus.
In the frequency detection apparatus of “invention A”, time A tau can delay first periodic signal by delayed signals output circuit. And, as for the spacing of the narrow width pulse (or edges) of first periodic signal, it is with Δτ/i(an integer positive in i=1,2, . . . , J, J) when period of a signal was included in second period for period of a signal in first period.
And, as for the spacing such as the narrow width pulse of second periodic signal, the edge, it is with jΔτ(an integer positive in j=1/I, . . . , one-third, half, 1, I) when period of a signal was included in first period for period of a signal in second period.
When the frequency of first periodic signal changed in a predetermined level of the high pass side, first period includes period of a signal in second period for period of a signal.
Alternatively, period of a signal is included in second period for period of a signal in first period when the frequency of first periodic signal reached place set value of the rise direction side. When the frequency of first periodic signal changed in a predetermined level of the low level side, second period includes period of a signal in first period for period of a signal.
Alternatively, second period includes period of a signal in first period for period of a signal when the frequency of first periodic signal reached the place set value of the drop direction side. Thus, in “invention A”, the frequency of first periodic signal dropped, and the lower limit was reached, or it is distinguished, and it can be determined whether frequency rises, and the upper limit was reached.
In “invention A”, as for the judgment circuit, first periodic signal is a narrow width pulse string. This narrow width pulse string includes a positive pulse and two pulses of the negative pulse in period. When the distance of the pulse of these pluses and minus is 180 degrees, or, when the duty of first periodic signal is 50%, it can be detected whether the half period of first periodic signal was included for the half period of second periodic signal. Alternatively, it can be detected whether in this case the half period of second periodic signal was included for the half period of first periodic signal.
For example, it is supposed that first periodic signal (measuring signal) is supposed to be a narrow width pulse string, and this narrow width pulse string also includes a positive pulse and two pulses of the negative pulse in frequency, and, even more particularly, it is supposed that the spacing of the pulse of these pluses and minus is 180 degrees. In this case, the judgment circuit can determine both positive pulse and negative pulses as a pulse (an equivalent pulse) of the same property. The judgment circuit outputs the judgment signal which responded to a judgement result.
Also, the judgment circuit can detect both positive going edge and negative-going edges as an edge (an equivalent edge) of the same property when first periodic signal is squarewave, and a duty is 50%. Even more particularly, the judgment circuit can detect the both sides of a positive pulse and the negative pulse as a pulse (an equivalent pulse) of the same property when first periodic signal is a triangular wave and a sine wave, and the spacing of a maximum of the magnitude and the minimum is 180 degrees.
A frequency detection apparatus as claimed in (2), wherein
the judgment circuit, when that period of a signal was included for period of a signal in second period in first period was detected, that the frequency of first periodic signal changes into a predetermined level of the high pass side depending on the detected number of times or it rose to the predetermined value is judged.
When period of a signal detected that it was included for period of a signal in second period in first period, the judgment circuit performs the judgment that responded to the number of times.
By first detection, the period is delay time Δτ/1,
By second detection, period is delay time Δτ/2,
By the detection of a thing of a beginning, period is delay time Δτ/I
It is thereby judged the frequency of first periodic signal changes into a predetermined level of the high pass side or to have reached the place set value of the rise direction side.
(4) When, as for the judgment circuit, Δτ meets a lower formula, T1+T2+ . . . TJ<=Δτ<T1+T2+ . . . TJ+TJ+1 (an integer positive in Tk (k=J, k-th pulse of first periodic signal as for . . . , 3,2,1), J),
When period of a signal detected that it was included for period of a signal in first period in second period, It is judged that the frequency of the Δτ=J, . . . , 3,2,1) first periodic signal changes into a predetermined level of the high pass side (1/j) in delay time or period rose to the predetermined value.
The specific handling of judgment circuit is as follows:
As for the judgment circuit, period judges that the frequency of first above periodic signal changed into a predetermined level of the high pass side by a certain delay time Δτ/J in first detection. Alternatively, the judgment circuit judges that period reached the value with the frequency of first above periodic signal by the delay time Δτ/J that there is in first detection. The judgment circuit judges that the frequency of first periodic signal changed into a predetermined level of the high pass side by delay time Δτ/(J−1) with the period (or having reached the place set value of the rise direction side) in second detection. The judgment circuit judges that the frequency of first periodic signal changed into a predetermined level of the high pass side by delay time Δτ with the period (or having reached the place set value of the rise direction side) in the detection of the J joint likewise.
(5) A frequency detection apparatus as claimed in (1),
wherein the delay circuit inputs first periodic signal, and second periodic signal is output, is initialized.
(6)(1) A frequency detection apparatus to assume a frequency detection apparatus as claimed in (5) either hot 1 unit, wherein,
the R units (first—the Rth) are connected in parallel, in which first periodic signal is common,
a delay time Δτ1 to first periodic signal of second periodic signal in first unit,
a delay time Δτ1 to first periodic signal of second periodic signal in second unit, . . .
a delay time Δτ1 to first periodic signal of second periodic signal in the R-th unit, are different each other.
(7) A frequency detecting device that the frequency detecting apparatus discribed in either of (1)-(5) is defind as one unit, wherein,
1st-Rth units are connected to in parallel,
A delay time Δτ to first periodic signal of second periodic signal in each unit is the same, the phase of each first periodic signal in 1st-Rth unit is different by 2π/R.
(8) The first periodic signal is performed voltage—frequency conversion of. A frequency detection apparatus as claimed in claim 1, wherein, first periodic signal is performed voltage-frequency conversion of.
(9) A frequency detection methods that second periodic signal delaying to first periodic signal from first periodic signal that frequency changes at time for predetermined time is generated, and this is output,
The frequency detection methods including judging that the frequency of the above first periodic signal changes into a predetermined level of the low level side by detecting time when that the frequency of the above first periodic signal changes into a predetermined level of the high pass side by detecting time when first period included period of a signal for period of a signal in second period or it rose to the predetermined value is judged and/or period of a signal was included for period of a signal in above first period in above second period or it dropped in predetermined value.
(10) When that period of a signal was included for period of a signal in second period in first period was detected, depending on the number of times, period is Δτ/i by the detection of i turn eyes the frequency of first above periodic signal in delay time
(an integer positive in i=1,2, . . . , I, I) Well, the frequency detection methods as claimed in (9) including judging that frequency of first periodic signal F1 changes in a predetermined level of the high pass side or the place set value of the rise direction side was reached.
(11) In a case of T1+T2+ . . . TJ<=Δτ<T1+T2+ . . . TJ+TJ+1, including judging that the frequency of first above periodic signal changes in a predetermined level of the high pass side by delay time or period reached the place set value of the rise direction side in j-th detection when that second period included period of a signal for period of a signal in first period was detected or it is frequency detection methods as claimed in (10)(9).
(12) Whenever first periodic signal is input, and second periodic signal is output, a frequency detection methods as claimed in either of (9)-(11) including the deference of second periodic signal being initialized.
(13) A frequency detection method as claimed in either of (9)-(12) including first periodic signal being performed voltage-frequency conversion of.
(Invention B): (1) The electric circuit controller comprising driving signal generation circuit, periodic signal generation circuit and the frequency detecting circuit, wherein
the driving signal generation circuit drives at least one electric switch included in the electric circuit,
the periodic signal generation circuit detects an electric information (voltage/current/electric power/phase) changing than the electric switch being driven more than one or one, and a periodic signal is generated from at least one electric information chosen by these detecting signals, and this is output as first periodic signal,
the delayed signals generation circuit outputs second periodic signal which retarded first periodic signal for predetermined time,
the judgment circuit detects whether first periodic signal and second periodic signal are input, and period of a signal was included for period of a signal in above second period in above first period and/or whether period of a signal was included for period of a signal in above first period in above second period, and judgment signal is output.
The periodic signal generation circuit can detect the following quantity of electricity as “current flowing or the voltage in the appointed part or voltage drop in an appointed part”.
Input current, input voltage, output current, output voltage, electric reactor voltage, electric reactor current, electric switch voltage, electric switch current, diode voltage, diode current.
The electric circuit controller of “invention B” may be the voltage-controlled, and even current control type is preferable. The electric switch comprising a power circuit is semiconductor switch such as a bipolar transistor, the FET transistor. The periodic signal which periodic signal generation circuit produces is typically a narrow width pulse string, a rectangular wave, serrulation wave, a triangular wave, a sine wave. Delayed signals generation circuit may be an analog circuit, and it may be a digital circuit. In delay time, it is set appropriately.
The spacing of the pulse changes when first periodic signal which periodic signal generation circuit produces is a narrow width pulse string. When the narrow width pulse string of first periodic signal is an original or negative pulse, the judgment circuit monitors whether the narrow width pulse of first periodic signal and the narrow width pulse of second periodic signal are input alternately. And the judgment circuit can be judged whether period of a signal is included in second period for period of a signal in first period. Alternatively, the judgment circuit can be judged whether period of a signal is included in first period for period of a signal in second period. For example, the judgment circuit detects only a positive pulse in a positive pulse and the case including two pulses of the negative pulse as first periodic signal, and a narrow width pulse string can output judgment signal in one period.
The judgment circuit can monitor an edge (a positive going edge and a negative-going edge) when first periodic signal is squarewave. The judgment circuit can be judged whether period of a signal is included in second period for period of a signal or whether first period includes period of a signal in first period for period of a signal in second period.
The judgment circuit monitors an edge (a positive going edge and a negative-going edge) when first periodic signal is serrulation wave or a maximum of the serrulation amplitude of wave can be watched. The judgment circuit can be judged whether period of a signal is included in second period for period of a signal or whether first period includes the period of first pulse for period of a signal in second period.
The judgment circuit can monitor, for example, a peak (a maximum and a minimum) and a zero point when first periodic signal is a triangular wave and a sine wave. The judgment circuit can be judged whether period of a signal is included in second period for period of a signal or whether first period includes period of a signal in first period for period of a signal in second period. In “invention B”, it can be determined to have reached the predetermined value by frequency. The frequency at that time is reciprocal of the delay time.
Thus, in a certain control system, delay time can detect the frequency when frequency reached the predetermined value when it is determined by at least one detection value.
That is, in this case current corresponding to the frequency and value (peak (maximum and minimum)) of the voltage can be detected.
(2) An electric circuit controller as claimed in (1), wherein, the electric signal are selected from below group:
The input voltage of the electric circuit,
The input voltage of the electric circuit,
Voltage emerging to an element comprising the electric circuit or equipment, the element or above equipment current flowing,
The output voltage of the electric circuit,
The output current of the electric circuit.
(3) The electric circuit controller which was described in (1) or (2), wherein,
it is retarded without being based on the change of the electric information or the delayed signals generation circuit retards first periodic signal based on at least one of the above electric information, and an above second periodic signal is output.
(4) An electric circuit controller as claimed in (1), wherein,
that the frequency of the above first periodic signal dropped in predetermined value because the frequency detecting circuit judges that the frequency of the above first periodic signal rose to the predetermined value because the judgment circuit detects time when period of a signal was included for period of a signal in above second period in first period and/or above judgment circuit detects time when period of a signal was included for period of a signal in above first period in above second period is judged.
In “invention B”, the frequency detecting circuit can delay a periodic signal by delayed signals generation circuit only at a certain time Δτ. In this case, first period includes period of a signal in second period for period of a signal when the spacing of the edge of the periodic signal is Δτ. Alternatively, period of a signal is included in first period for period of a signal in this sometimes second period. When when period of a signal was included in second period for period of a signal in first period, the frequency of first periodic signal rose to the predetermined value. When when period of a signal was included in first period for period of a signal in second period, the frequency of first periodic signal dropped to a place set value of the drop direction side. Thus, as for the frequency detecting circuit, the frequency of first periodic signal rose, and the above place set value was reached, or it can draw a sharp line whether it drops, and the above place set value was reached.
Note that the spacing of a narrow width pulse and the edge of first periodic signal is as follows when period of a signal was included in second period for period of a signal in first period.
Δτ/i (i=1,2, . . . , J, J is an integer)
Also, the spacing of a narrow width pulse and the edge of second periodic signal is as follows when period of a signal was included in first period for period of a signal in second period.
jΔτ(j=1/I, . . . , ⅓, ½, 1, I is ingeger)
The first periodic signal is a narrow width pulse string. This narrow width pulse string may include a positive pulse and a negative pulse of the 180 degrees spacing in one period. Also, the duty of first periodic signal may be 50%. In these cases, the judgment circuit can be detected whether the half period of first periodic signal was included for the half period of second periodic signal and/or whether the half period of second periodic signal was included for the half period of first periodic signal.
For example, the judgment circuit can judge the both sides of a positive pulse and the negative pulse as a pulse (an equivalent pulse) of the same property in a positive pulse of the 180 degrees spacing and the case including the negative pulse in one period a narrow width pulse string.
Also, both positive going edge and negative-going edges is done with the edge (an equivalent edge) of the same property, and the judgment circuit can be judged when the duty of first periodic signal is 50%. Even more particularly, the judgment circuit can judge the both sides of a positive pulse and the negative pulse as a pulse (an equivalent pulse) of the same property when first periodic signal is a triangular wave and a sine wave, and the spacing of a maximum of the magnitude and the minimum is 180 degrees.
(5) An electric circuit controller as claimed in (1)-(2), wherin,
the judgment circuit, when that first period included period of a signal for period of a signal in second period was detected, that the frequency of first periodic signal changes in a predetermined level of the high pass side by the i-th detection by delay time with the period or the frequency of the above first periodic signal reached the place set value of the rise direction side depending on the number of times is judged.
the delay time Δτ/i (an integer positive in i=1,2, . . . , I, I):
(6) An electric circuit controller as claimed in either from (1) to (5) including the judgment circuit judging that the frequency of the above first periodic signal changes in a predetermined level of the high pass side in Δτ(j=J, . . . , 3,2,1) (1/j) in delay time or period reached the place set value of the rise direction side in j-th detection when that period of a signal was included for period of a signal in above first period in second period was detected in a case of T1+T2+ . . . +TJ<=Δτ<T1+T2+ . . . +TJ+TJ+1 (an integer positive in J).
(7) Whenever the delay circuit inputs first periodic signal, and second periodic signal is output, an electric circuit controller as claimed in either from (1) from to (7) including what is initialized.
(8) A frequency detecting circuit comprising an electric circuit controller as claimed in either of hot is done with 1 unit, and it is the electric circuit controller comprising the frequency detecting circuit that it is made a common use of in an above first periodic signal, and R unit is connected from first unit in parallel, and it is, and in the delay time to first periodic signal of second periodic signal in first unit in the delay time to first periodic signal of second periodic signal in Δτ1 and second unit Δτ2, . . .
An electric circuit controller of the description including ΔτR being different in the delay time to first periodic signal of second periodic signal in the R unit.
(9) A frequency detecting circuit comprising an electric circuit controller as claimed in (1)-(7) is done with 1 unit, and it is the electric circuit controller comprising the frequency detecting circuit that it is made a common use of in an above first periodic signal, and R unit is connected from first unit in parallel, and it is, and in the delay time to first periodic signal of second periodic signal in first unit in the delay time to first periodic signal of second periodic signal in Δτ1 and second unit Δτ2, . . .
an electric circuit controller of the description including ΔτR being different in the delay time to first periodic signal of second periodic signal in the R unit.
(10) Because the electric circuit is AC/DC power inverter circuit of current control type or the voltage-controlled or DC/DC power inverter circuit, and the electric information is characterized by being chosen voltage appearing to the input voltage of the electric circuit, the input voltage of the above electric circuit, an element comprising an above electric circuit or the equipment, an above element or above equipment by current flowing, the output voltage of the above electric circuit, the group of the output current of the above electric circuit, an electric circuit controller as claimed in either from (1) to (9).
(11) A periodic signal is generated from an electric information of at least one that an electric information (voltage/current/electric power/a phase) changing by the drive of the electric switch of at least one included in the electric circuit is detected more than one or one, and was chosen by these measuring signal, and it is a method to control an electric circuit by detecting the frequency of the note periodic signal, and in detection of the above frequency,
The electric circuit control method including it is detected whether second periodic signal which retarded first periodic signal for predetermined time is generated, and first periodic signal and above second periodic signal are input, and period of a signal was included for period of a signal in above second period in above first period and/or whether period of a signal was included for period of a signal in above first period in above second period, and judgment signal is output, and driving an above electric switch depending on the judgement result.
(12) The electric circuit control method as claimed in (11) including being chosen voltage appearing to the input voltage of the electric circuit, the input voltage of the electric circuit, an element comprising an above electric circuit or the equipment, an above element or above equipment as the electric information by current flowing, the output voltage of the above electric circuit, the group of the output current of the above electric circuit.
(13) Including it is retarded without being based on the change of the electric information or first periodic signal is retarded based on at least one of the above electric information, and outputting an above second periodic signal or it is an electric circuit control method as claimed in (12) (11).
(14) An electric circuit control method as claimed in either from (11) to (13) including judging that the frequency of the above first periodic signal changes in a predetermined level of the low level side because the frequency of the above first periodic signal detects time when that it changes or the place set value of the rise direction side was reached is judged and/or a predetermined level of the high pass side included period of a signal for period of a signal in above first period in above second period by detecting time when first period included period of a signal for period of a signal in second period or the place set value of the drop direction side was reached.
(15) An electric circuit control method as claimed in either from (11) to (14) including the frequency of the above first periodic signal judging that the frequency of first periodic signal changes in a predetermined level of the high pass side in Δτ/i (an integer positive in i=1,2, . . . , I, I) in delay time or period reached the place set value of the rise direction side by the i-th detection depending on the number of times when that first period included period of a signal for period of a signal in second period was detected.
(16) The first period period of a signal,
T1+T2+ . . . +TJ<=Δτ<T1+T2+ . . . +TJ+TJ+1 (an integer positive in J) An electric circuit control method as claimed in either from (11) to (15) including judging that the frequency of the above first periodic signal changes in a predetermined level of the high pass side in Δτ=J, . . . , 3,2,1) (1/j) in delay time or period reached the place set value of the rise direction side in j-th detection when that second period included period of a signal for period of a signal in first period was detected in case.
(Invention C): (1) The delay circuit including the delay time when an above detecting circuit generates by one end is connected to the input signal path of the detecting circuit, and other end is a delay circuit having an impedance circuit connected to a gland, and a plurality of electric switches to change the overall impedance of the above impedance circuit into when an on control signal or an off control signal was input, respectively, be included in an above impedance circuit, and changing the impedance of the above impedance circuit by the combination of the ON state of the electric switch of plural above or the off state changing.
(2) The delay circuit as claimed in (2) including the thing including impedance (a resistance ingredient, a capacity ingredient, an inductance ingredient) that the electric switch of plural at least above has the impedance circuit and/or the impedance due to the electric wiring.
(3) The impedance circuit including the thing including a resistance element, a capacitative element, one of the inductance elements or combinations thereof or it is a delay circuit as claimed in (2) (1).
(4) A delay circuit as claimed in either from (2) to (3) including the electric switch being a gate electric switch (the buffer with the control terminal)
(5)(1) The delay circuit system including the thing comprising the delay control circuit which sends out an ON-OFF control signal to a delay circuit as claimed in (4) either hot and each electric switch.
(6) The delay circuit including the delay time when an above detecting circuit generates by one end is connected to the input signal path of the detecting circuit, and other end is a delay circuit having a plurality of impedance circuit element connected to a gland, and open position is formed between an above input signal path and an above gland when an on control signal was input, and the electric switch which forms impedance between an above input signal path and an above gland when an off control signal was input be included in each impedance circuit element, respectively, and changing the impedance of the above impedance circuit by the combination of the ON state of each electric switch or the off state changing.
(7) The delay circuit as claimed in (6) including the thing including impedance (a resistance ingredient, a capacity ingredient, an inductance ingredient) that at least electric switch has the impedance circuit element and/or the impedance due to the electric wiring.
(8) The impedance circuit element including the thing including a resistance element, a capacitative element, one of the inductance elements or combinations thereof or it is a delay circuit as claimed in (7) (6).
(9) A delay circuit as claimed in either from (6) including impedance is P unit comprised delay circuit in Z (1), Z (2), . . . , impedance circuit element of Z (N), respectively, and being represented unit delay time as τ zero in Tk (Z(k))=(P+1) k−1 τ0(k=1,2, . . . . , N) Tk in delay time by each impedance circuit element to (8).
(10) A delay circuit as claimed in either from (6) to (10) including the electric switch being a gate electric switch (the buffer with the control terminal)
(11) A delay circuit as claimed in either from (6) to (10) including the impedance circuit element includes a buffer, and the gland side being provided with the buffer than the electric switch.
(12) The detecting circuit is a delay circuit as claimed in either from (6) to (11) including the thing including the CR integrating circuit comprising capacitive elements and a resistance element, capacitive elements and resistance elements.
(13) (6) The delay circuit system including the thing comprising the delay control circuit which sends out an ON-OFF control signal to a delay circuit as claimed in (12) either hot and each electric switch. When frequency conversion is made, and voltage and the current of all parts are detected in an AC/DC converter, DC/DC converter, boost chopper, depression chopper, and (output current, output voltage, output power, input current, output voltage, input power) to control listing and input is controlled, the delay circuit system of “invention C” is particularly effective.
(Invention A): By “invention A” configuration simple (a frequency detection apparatus and frequency detection methods), second periodic signal (the signal which retarded measuring signal for predetermined time) can be compared with the measuring signal (first periodic signal). That frequency rose to predetermined value is thereby determined. Also, that frequency dropped to predetermined value is determined
(Invention B): The input current in the electric circuits such as power inverter circuits electric by simple structure, input voltage, output current, output voltage, voltage appearing to the electric reactor, an above electric reactor current flowing, voltage appearing to the above electric switch, an above electric switch current flowing, voltage appearing to the diode (a commutation diode, a rectifier diode), an above diode changes (that the frequency of the periodic signal rose to the predetermined level is detected with high accuracy.) such as the current flowing Also, that frequency of the measuring signal dropped to a predetermined value is detected.
(Invention C): According to “invention C”, setting of the delay time is enabled with high accuracy. Because it is not necessary, as for the delay circuit of “invention C”, the selective circuit (multiplexer) to select the signal which delayed appropriately from in delayed signals a lot (more than 1,000) does not have to keep a fixed lines length from each delay formative element to selective circuit 82. Also, the limit of the design is relaxed without serially-connecting a large number of delay circuit elements. Also, simplification of the circuit can be planned.
After, in “invention C”, having considered floating resistance such as the circuit wiring, floating capacitance, value of the floating inductance, it becomes easy to determine delay time (i.e., a circuit design becomes easy).
Because the production by the semiconductor process is easy, and the third state buffer of the same specifications also has little variation of the input impedance, it is preferable in “invention C”. A resistance element, a capacitative element, one or combinations of the inductance element thereof can be connected to these third state buffers.
(Invention C) According to the present invention, setting of the delay time is enabled with high accuracy. In delay circuit of the present invention, selective circuit (multiplexer) to select signal which delayed from delayed signals appropriately a lot (more than 1,000) is not necessary. Thus, it is not necessary to keep a fixed lines length from each delay formative element to selective circuit 82. Limit of design is relaxed without serially-connecting a large number of delay circuit elements. Also, simplification of circuit can be planned.
According to the present invention, after having considered floating resistance such as circuit wiring, floating capacitance, value of floating inductance, it becomes easy to determine the delay time (thus, circuit design becomes easy).
Production in semiconductor process is easy, and, in the third state buffer of the same specification, as for these, it is also preferable in the present invention because there is little variation of input impedance.
11, 21, 31, 41A, 41B, 51A, 51B, 61A, 61B Delayed Signals Output Circuit
12, 22, 32, 42, 52, 62 Judgment Circuit
121,321 Counters
43, 53, 63 Control circuits
54 Distributing Circuits
65 Range Selective Circuits
UA, UB Frequency Detection Apparatus Unit
11, 21 Power Converters
12, 22 Control Circuits
13, 13A, 13B, 23 Periodic Signal Generation Circuit
14, 24 Frequency Detecting Circuits
15, 25 Driving Signal Generation Circuit
16, 16A, 16B Delay Control Circuit
17 Phase Shift Circuit
17 Range Selective Circuits
111 Electric Switches
112 Electric Reactors
113 Current Detecting Resistance
114 Commutation Diodes
115 Capacitors
141,241 Delayed Signals Generation Circuit
142,241 Judgment Circuit
81 Power Supplies
82 Loads
1 Delay Circuit
11 Detecting Circuits
12 Impedance Circuits
13 Control Circuits
14 Input Buffers
15 Input Signal Paths
SWk Electric Switch
Z (k) Impedance
Bk Buffer
r Resistance
TBk Third State Buffer
(Invention A): A frequency detection apparatus of “invention A” and the embodiment of frequency detection methods are described below.
In first embodiment, as shown in
First periodic signal F1 and 2nd periodic signal F2 are set, as depicted above, so that period shortens according to a harmonic progression.
The interval between the narrow width pulses of 1st and 2nd: 1 sec
The interval between the narrow width pulses of 2nd and 3rd: ½ sec
The interval between the narrow width pulses of 3rd and 4th: ⅓ sec
The judgment circuit 12 inputs 1st periodic signal F1 and 2nd periodic signal F2. Judgment circuit 12 detects whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2, and a detection result is output as judgment signal. “Period of 1st periodic signal F1 is included in period of 2nd periodic signal F2” and “Two consecutive narrow width pulses of 1st periodic signal F1 are located between two consecutive narrow width pulses of 2nd periodic signal F2” are equivalent. A former pulse may be piled up in the former narrow width pulse among two narrow width pulses to continue of 2nd periodic signal F2 among two consecutive narrow width pulses of 1st periodic signal F1. In this case, period of 1st periodic signal F1 is included in period of 2nd periodic signal F2. Also, period of 1st periodic signal F1 may not be included in period of 2nd periodic signal F2. Also, a later narrow width pulse may be piled up in the later narrow width pulse among two narrow width pulses to continue of 2nd periodic signal F2 among two consecutive narrow width pulses of 1st periodic signal F1. In this case, period of 1st periodic signal F1 may be included in period of 2nd periodic signal F2. Also, it may not be included.
It can be monitored whether a narrow width pulse of 1st periodic signal F1 and a narrow width pulse of 2nd periodic signal F2 are detected in 1st embodiment alternately. And it can be detected whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2. That is, in
In 1st embodiment, as shown in
But, after “6th narrow width pulse of 1st periodic signal F1”, “7th narrow width pulse of 1st periodic signal F1” is detected. Thus, judgment circuit 12 judges that there is not alternating characteristics at this time (“upper bound detection” of
In
In other words, in
Note that the spacing of narrow width pulse “of 5th narrow width pulse” and “6th of” 2nd periodic signal F2 has a long than Δτ and the spacing of 6th narrow width pulse “of 6th narrow width pulse” and “2nd periodic signal F2 of the” 1st periodic signal F1 is Δτ. There is 7th narrow width pulse “of the” 1st periodic signal F1 to the left by all means than 6th narrow width pulse “of” 2nd periodic signal F2. From this, it is clear that judgment circuit 12 can detect a time of when period of 1st periodic signal F1 shortened than Δτ.
As mentioned earlier, in 1st embodiment, frequency of “1st periodic signal F1” rises according to a harmonic progression. The frequency of “2nd periodic signal F2” becomes similarly higher, too. The case that frequency of “1st periodic signal F1” rose to as follows was described to make plain in 1st embodiment (
“1 Hz, ½ Hz, ⅓ Hz, . . . ”
However, the frequency of 1st periodic signal F1 may really rise as follows.
“25*106 Hz (25*106+1) Hz (25*106+2) Hz, . . . ”
Also, for example, the frequency of 1st periodic signal F1 may rise as follows.
“25*106 Hz (25*106+10) Hz (25*106+20) Hz, . . . ”
As described earlier, in 1st embodiment, only Δτ can delay 2nd periodic signal F2 to 1st periodic signal F1. That a narrow width pulse interval of 1st periodic signal F1 became shorter than Δτ (in in a time when the period that was longer than Δτ shortened than Δτ namely a time of when a narrow width pulse of 6th or 7th was input) can be thereby detected.
Note that 1st periodic signal F1 can generate the periodic signal of the arbitrary waveform by passing a waveform shaping circuit. In the example above, a time of when period of 1st periodic signal F1 was included in period of 2nd periodic signal F2 can be detected. That is, judgment circuit 12 can detect “as” in a time of when frequency of 1 “periodic signal F1 rose to the predetermined value in a time of when period of the” 1st periodic signal F1 shortened than Δτ.
In the example above, the detection (a judgment) by judgment circuit 12 showed the case that was once. However, detection by judgment circuit 12 can do a judgment (the judgment of the time of when it was shorter period) like the above by multiple times, or 2nd, 3rd, . . . , I-th detection of the I joint in “invention A”.
That is, judgment circuit 12 can detect what included period of 1st periodic signal F1 in period of 2nd periodic signal F2. And that frequency of 1st periodic signal F1 reached the predetermined value can be judged what joint the detection is.
In this case, as shown in
In
Note that only detection of 1st is performed unless shortest period “of the” 1st periodic signal F1 becomes lower than half of longest period “of the” 1st periodic signal F1 (unless maximum frequency “of the” 1st periodic signal F1 is as above 2 times of smallest frequency “of the” 1st periodic signal F1). When a change of the frequency is small, the detection after 2nd by judgment circuit 12 does not have to consider. For example, the detection after 2nd joint is not done when frequency of 1st periodic signal F1 changes in the range of 40 MHz from 25 MHz.
In 2nd embodiment, as for judgment circuit 22, Δτ has following relation in during starting (at the time of detection processing initiation) of frequency detection apparatus 2 as indicated in
T1≦Δτ<T1+T2
Also, it is set the frequency of 1st periodic signal F1 is proportional from frequency 13 Hz at time, and to go low, and period gets longer according to a harmonic progression. Also, it is set the frequency of 1st periodic signal F1 is proportional from frequency 13 Hz at time, and to go low, and period gets longer according to a harmonic progression. Also, as shown in
First periodic signal F1 and 2nd periodic signal F2 are as follows, as depicted above, because it is set so that period gets longer in a harmonic progression from frequency 13 Hz:
Judgment circuit 22 inputs 1st periodic signal F1 and 2nd periodic signal F2. Judgment circuit 22 detects whether period of 2nd periodic signal F2 was included in period of 1st periodic signal F1, and judgment signal is output. “Period of 2nd periodic signal F2 is included in period of 1st periodic signal F1” and “Two consecutive narrow width pulses of 2nd periodic signal F2 are located between two consecutive narrow width pulses of 1st periodic signal F2” are equivalent. A former narrow width pulse may be piled up in the former narrow width pulse among two narrow width pulses to continue of 1st periodic signal F1 among two consecutive narrow width pulses of 2nd periodic signal F2. Also, a later narrow width pulse may be piled up in the later narrow width pulse among two narrow width pulses to continue of 1st periodic signal F1 among two consecutive narrow width pulses of 2nd periodic signal F2. These are permitted in a judgment whether or not period of 2nd periodic signal F2 was included in period of 1st periodic signal F1.
In this embodiment, it is monitored whether a narrow width pulse of 1st periodic signal F1 and a narrow width pulse of 2nd periodic signal F2 are detected alternately. It is thereby detected whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2. That is, as shown in
In this embodiment, as shown in
“The 1st narrow width pulse of 1st periodic signal F1”,
“2nd narrow width pulse of 1st periodic signal F1”,
“1st narrow width pulse of 2nd periodic signal F2”,
“3rd narrow width pulse of 1st periodic signal F1”,
“2nd narrow width pulse of 2nd periodic signal F2”,
“4th narrow width pulse of 1st periodic signal F1”,
“3rd narrow width pulse of 2nd periodic signal F2”,
“5th narrow width pulse of 1st periodic signal F1”,
“4th narrow width pulse of 2nd periodic signal F2”,
“6th narrow width pulse of 1st periodic signal F1”,
“5th narrow width pulse of 2nd periodic signal F2.”
However, judgment circuit 22 determines that there are not alternating characteristics when 6th narrow width pulse of,” 2nd periodic signal F2 was detected (“lower limit detection” of
That is, when, in a time of when alternating characteristics with a narrow width pulse of 1st periodic signal F1 and the narrow width pulse of 2nd periodic signal F2 disappeared, 6th narrow width pulse of 2nd periodic signal F2 was input into judgment circuit 22 in
In other words, in
As mentioned earlier, in 2nd embodiment, frequency of 1st periodic signal F1 depends on the harmonic progression, and it goes low. Thus, the frequency of 2nd periodic signal F2 goes low in a harmonic progression, too. Frequency of 1st periodic signal F1 described a case to go low like “ 1/13 Hz, 1/12 Hz, 1/11 Hz, . . . ” to make plain in 2nd embodiment (
As described earlier, in “invention A”, only Δτ delays 2nd periodic signal F2 to 1st periodic signal F1. That a narrow width pulse interval of 1st periodic signal F1 was delay time for longer than Δτ can be thereby detected. In other words, a time when a narrow width pulse interval of 1st periodic signal F1 was for longer than Δτ in delay time can be detected.
Note that 1st periodic signal F1 comprising narrow width pulses can generate the periodic signal of the arbitrary waveform by passing a waveform shaping circuit. In the example above, a time when period of 2nd periodic signal F2 was included in period of 1st periodic signal F1 was detected. That is, by a time when it was for longer than Δτ period of 1st periodic signal F1 which judgment circuit 22 had a shorter than Δτ in during starting (at the time of detection processing initiation) of frequency detection apparatus 2, predetermined value can judge that it dropped frequency of 1st periodic signal F1.
That is, in 2nd embodiment, Δτ has next relation in during starting of frequency detection apparatus 2 as indicated in
In 2nd embodiment, detection by judgment circuit 22 can do a judgment (the judgment of the time when it was shorter period) like the above by multiple times or 2nd, 3rd, . . . , detection of the J joint. That is, in during starting (at the time of detection processing initiation) of frequency detection apparatus 2, Δτ may be T1+T2+TJ<=Δτ<T1+T2+TJ+TJ+1 (2) in delay time (in the case of (1) expression at the time of J=2). Here, in Tk (k=1,2, . . . , J, J+1), k-th pulse of 1st periodic signal, J are positive integers.
For example, in the case of J=3, as for judgment circuit 22, frequency of 1st periodic signal F1 judges that frequency dropped in predetermined value by the detection (a time when the period when it was shorter than Δτ/2 was for longer than Δτ/2) of 1st joint. Also, as for judgment circuit 22, frequency of 1st periodic signal F1 judges that frequency dropped in predetermined value by the detection (a time when the period when it was shorter than Δτ was for longer than Δτ) of 2nd joint.
In
In
Judgment circuit 22 detects that 8th narrow area pulse and 9th narrow area pulse of 2nd periodic signal F2 are included between 9th narrow area pulse and 10th narrow area pulse of 1st periodic signal F1. That is, that frequency of 1st periodic signal F1 changes in a predetermined level of the low level side by the detection of 2nd joint more or the place set value of the drop direction side was further reached is judged. The period when the detection of 2nd joint was shorter than Δτ is a time when it was for longer than Δτ.
Note that, in 2nd embodiment, only the detection of 1st joint is performed like 1st embodiment unless the shortest period of 1st periodic signal F1 becomes lower than half of the longest period (unless the smallest frequency of 1st periodic signal F1 is as above 2 times of maximum frequency). When a change of the frequency is small because it is it, the detection after 2nd joint by judgment circuit 22 does not have to consider. For example, the detection after 2nd joint is not done when frequency of 1st periodic signal F1 changes in the range of 26 MHz from 25 MHz.
The 1st periodic signal F1 that frequency changes at time (it gets longer dynamically or it shortens) is input, and delayed signals output circuit 31 outputs 2nd periodic signal F2 where only Δτ retarded this 1st periodic signal F1 for predetermined time.
In this embodiment, as shown in
Also, as shown in
When the period of “6th narrow width pulse of 1st periodic signal F1” shortens than Δτ by the process that frequency increases, it is shown (an upper bound). Also, it is shown (a lower limit) when the period of “the eleventh narrow width pulse of 1st periodic signal F1” becomes for longer than Δτ by the process when frequency decreases.
In
In
Counter 321 inputs 1st periodic signal F1 and 2nd periodic signal F2, and a record (an increment) does the number of times that period of 1st periodic signal F1 was included in period of 2nd periodic signal F2. With this, a record (a decrement) does what included period of 2nd periodic signal F2 in period of 1st periodic signal F1.
In this embodiment, as shown in
In
When it is for longer than Δτ/2 the period of “the narrow width pulse of 1st periodic signal F1” by the process when frequency also decreases (lower limit 1st) and when it “is further for longer than Δτ “a narrow width pulse of 1st periodic signal F1” period, it is shown” (lower limit 2nd). In
In
As far as, in 3rd embodiment, the shortest period of 1st periodic signal F1 does not become lower than half of the longest period like 1st embodiment (as far as maximum frequency of 1st periodic signal F1 does not become lower than half of the smallest frequency), only the detection of 1st joint is performed. Thus, the detection after 2nd joint does not have to consider when a change of the frequency is small. For example, the detection after 2nd joint by judgment circuit 22 is not done when frequency of 1st periodic signal F1 changes in the range of 25-40 MHz.
The 1st periodic signal F1 input into 1st unit UA and 2nd unit UB inputs the common 1st periodic signal F1. Also, it is different from ΔτB in delay time to 1st periodic signal F1 of 2nd periodic signal F2B in ΔτA and 2nd unit UB in delay time to 1st periodic signal F1 of 2nd periodic signal FA2 in 1st unit UA. However, it is ΔτA <ΔτB. With frequency detection apparatus 4 of
F1 vs. it is done, and π can be delayed.
First unit UA (frequency detecting circuit 5A) consists of delayed signals output circuit 51A and judgment circuit 52. It is not illustrated, but the delay control circuit can be provided in the preceding paragraph of delayed signals output circuit 51A. Also, 2nd unit UB (frequency detecting circuit 5B) consists of delayed signals output circuit 51B and judgment circuit 52. It is not illustrated, but it is possible to provide the delay control circuit in the preceding paragraph of delayed signals output circuit 51B.
Delay time to 1st periodic signal F1 of 2nd periodic signal FA2 in 1st unit UA (frequency detecting circuit 5A) is assumed ΔτA. Delay time to 1st periodic signal F1 of 2nd periodic signal FB2 in 2nd unit UB (frequency detecting circuit 5B) is assumed ΔτB. It is different from ΔτB in ΔτA and delay time by delay time (ΔτA <ΔτB).
First unit UA, a subsequent stage of 2nd unit UB are provided with common synthetic circuit 55. First unit UA, listing of 2nd unit UB are synthesized. As for frequency detection apparatus 5 of
Note that, in
In
It may be the same as ΔτB in delay time to 1st periodic signal FB1 of ΔτA and 2nd periodic signal FB2 in delay time to 1st periodic signal FA1 of 2nd periodic signal FA2.
Also, ΔτB may be different from ΔτA in these delay time.
Frequency detection apparatus 6 of
Note that, in
(Invention B):
Frequency detecting circuit 104 consists of delayed signals output circuit 1041 and judgment circuit 1042. Periodic signal generation circuit 103 detects 1st signal group of electric circuit 101 as voltage signal F1, and it is output to judgment circuit 1042. Δτ is set to delayed signals output circuit 1041 in delay time, and delayed signals output circuit 1041 outputs 2nd periodic signal F1 that Δτ delayed to 1st voltage signal F1 to judgment circuit 105. First periodic signal F3 and 2nd periodic signal F2 are input, and judgment circuit 105 detects whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2. Also, judgment circuit 105 detects whether period of 2nd periodic signal F2 was included in period of 1st periodic signal F1. Driving signal generation circuit 105 generates control signal VGs from this judgment circuit signal, and this is sent out to an electric switch of electric circuit 101.
In
In “invention B” the electric information included in electric circuit 101, for example, input current, Input voltage, Output current, Output voltage, Voltage emerging to an electric reactor, The electric reactor current flowing, Voltage emerging to the electric switch, The electric switch current flowing, It is current flowing with voltage emerging to a diode (a commutation diode, a rectifier diode), the diode . These voltage and current can be adopted as electrical signal in
Control circuit 12 has periodic signal generation circuit 13 and frequency detecting circuit 14 and driving signal generation circuit 15 and delay control circuit 16. Periodic signal generation circuit 13 detects voltage Vi corresponding to circuit current i of power converters 11, and a detection level is converted into periodic signal F1. Periodic signal generation circuit 13 can be comprised, for example, from an analog voltage controlled oscillator (VCO).
Frequency detecting circuit 14 consists of delayed signals generation circuit 141 and judgment circuit 142. Delay control circuit 16 detects output voltage eO of power converters 11 through analog-to-digital converter 17, and delayed signals generation circuit 141 can output delay control sincerity DLY (eO). When delayed signals generation circuit 141 works by analog input, analog-to-digital converter 17 is unnecessary in
Delayed signals generation circuit 141 outputs 2nd periodic signal F2 where only Δτ retarded 1st periodic signal F1 for predetermined time. The predetermined time Δ tau (it is time depending on DLY (eO) and, as for this time, is smaller than initial period of 1st periodic signal F1.) Judgment circuit 142 inputs 1st periodic signal F1 and 2nd periodic signal F2, and it is detected whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2, and judgment signal is output. Also, judgment circuit 142 detects whether period of 2nd periodic signal F2 was included in period of 1st periodic signal F1, and judgment signal is output.
As for driving signal generation circuit 15, the control terminal of an electric switch comprising power converters 11 can output control signal VGs. The electric circuit controller of “invention B” can apply to three-phase power converter 11 as shown in
Based on these electric information group, a control signal is output to the electric switch of each aspect to comprise power conversion equipment 1.
As for power converters 11, it is electric switch 111 and electric reactor 112 from current detecting resistance 113 and commutation diode 114 and capacitor 115.
Electric switch 11 and electric reactor 112 and current detecting resistance 113 are performed series connection of sequentially by the input side, and commutation diode 114 is connected to a T-head character between electric switch 11 and electric reactor 112, and capacitor 115 is connected to an output side.
Control circuit 12 is the same as electric circuit controller 12 shown in
As shown in STs of
That is, judgment circuit 141 outputs judgment signal SQ when frequency f1 of 1st periodic signal F1 reached predetermined threshold fSH (approximately 40 MHz). Here, when Δτ was reached in the period when period of 1st periodic signal F1 supported when “predetermined threshold fSH (approximately 40 MHz) was reached” (it is
In
Electric reactor current iL is adopted as a circuit current of
, each delayed signals generation circuit 141 is the same. In
Control circuit 12 of
As shown in
Note that electric reactor current iL of
In
Control circuit 12 of power conversion equipment 1 is provided with range selective circuit 18. Each frequency detecting circuit 14A, 14B have the common 1st periodic signal F1. This 1st periodic signal F1 is sent to 1st unit, either of 2nd unit (frequency detecting circuit 14A, 14B) whether it belongs to a low level whether frequency of 1st periodic signal F1 belongs to high pass.
In
ΔτB may be the same in delay time to 1st periodic signal FB1 of ΔτA and 2nd periodic signal FB2 in 2nd unit (frequency detecting circuit 14B) in delay time to 1st periodic signal FA1 of 2nd periodic signal FA2 in 1st unit (frequency detecting circuit 14A). Also, it may be different.
Converter 1 of
Power conversion equipment 1 of
Here, periodic signal generation circuit 13 outputs frequency detecting circuit 14A and 1st periodic signal F1 which are common to frequency detecting circuit 14B. The 1st unit (frequency detecting circuit 14A) consists of delayed signals generation circuit 141 and judgment circuit 142. A preceding paragraph of delayed signals generation circuit 141 is provided with delay control circuit 16A. The 2nd unit (frequency detecting circuit 14B) consists of delayed signals generation circuit 141 and judgment circuit 142. A preceding paragraph of delayed signals generation circuit 141 is provided with delay control circuit 16B.
In
The signal state of all parts of power conversion equipment 1 is shown, and a state 1st periodic signal F1 and 2nd periodic signal FA2 are proportional to
When “period shrank than ΔτA”, it is time beyond the frequency factory automation corresponding to ΔτA.
And, as for (when it fell from frequency fB), driving signal generation circuit 15 outputs the control signal that an electric switch becomes the ON to power conversion 11 when period grew big than ΔτB (cf. VGs of
For example, delay control circuit 16A, 16B change ΔτA, ΔτB so that listing of control circuit 12 has a characteristic of the A (eO-Er)-EB. ΔτA, ΔτB are set to delay control circuit 16A, each delayed signals generation circuit 141 of 16B. In A, in transmission coefficient, eO, as for the output voltage of power converters 11, the Er, reference voltage, Er are bias voltage. By the change of this delay characteristic, the frequency threshold when it changes changes, for example, into the side that is smaller than ΔτA as shown in a figure of of circuit current i of
Circuit current i of
“The frequency threshold when period of 1st periodic signal F1 changes in the side that is smaller than ΔτA from the side that is bigger than ΔτA” is upper bound threshold fASH of the figure of frequency change of
Circuit current i of
“The frequency threshold when period of 1st periodic signal F1 changes in the side that is bigger than ΔτB from the side that is smaller than ΔτB” is lower limit threshold fBSH of the figure of frequency change of
That is, with power conversion equipment 1 of
When frequency f1 of 1st periodic signal F1 reached upper bound threshold fASH, as for driving signal generation circuit 15, an electric switch outputs OFF and the control signal that it is to power converters 11. When frequency f1 of 1st periodic signal F1 fell to lower limit threshold fBSH, the control signal that an electric switch becomes the ON to power converters 11 is output (cf. VGs of
Control circuit 22 has periodic signal generation circuit 23 and frequency detecting circuit 24 and driving signal generation circuit 25. Periodic signal generation circuit 23 detects output voltage eO of power converters 21, and a detection level is converted into periodic signal F1.
Frequency detecting circuit 24 consists of delayed signals generation circuit 241 and judgment circuit 242. Delayed signals generation circuit 241 outputs 2nd periodic signal F2 where only Δτ (smaller than initial period of 1st periodic signal F1) retarded 1st periodic signal F1 for predetermined time. Judgment circuit 242 inputs 1st periodic signal F1 and 2nd periodic signal F2, and it is detected whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2, and judgment signal is output. Also, judgment circuit 242 detects whether period of 2nd periodic signal F2 was included in period of st periodic signal F1, and judgment signal is output. As for driving signal generation circuit 25, the control terminal of an electric switch comprising power converters 21 can output a control signal.
Also, 1st periodic signal F1 is set as follows period decreases in a harmonic progression from frequency 1 Hz, and to increase.
It is equivalent with including period of 1st periodic signal F1 in period of 2nd periodic signal F2 and two narrow width pulses to continue of 1st periodic signal F1 being located between two narrow width pulses to continue of 2nd periodic signal F2. Also, it is equivalent with including period of 2nd periodic signal F1 in period of 1st periodic signal F1 and two narrow width pulses to continue of 2nd periodic signal F2 being located between two narrow width pulses to continue of 1st periodic signal F1. In a judgment whether or not period of 1st periodic signal F1 was included in period of 2nd periodic signal F2, a former narrow width pulse may be piled up in the former narrow width pulse among two narrow width pulses to continue of 2nd periodic signal F2 among two narrow width pulses to continue of 1st periodic signal F1. Also, a later narrow width pulse may be piled up in the later narrow width pulse among two narrow width pulses to continue of 2nd periodic signal F2 among two consecutive narrow width pulses of 1st periodic signal F1.
In a judgment whether or not period of 2nd periodic signal F2 was included in period of 1st periodic signal F1, a former narrow width pulse may be piled up in the former narrow width pulse among two narrow width pulses to continue of 1st periodic signal F1 among two narrow width pulses to continue of 2nd periodic signal F2. Also, a later narrow width pulse may be piled up in the later narrow width pulse among two narrow width pulses to continue of 1st periodic signal F1 among two consecutive narrow width pulses of 2nd periodic signal F2.
In this embodiment, it can be detected whether a narrow width pulse of 1st periodic signal F1 and a narrow width pulse of 2nd periodic signal F2 are detected alternately whether period of 1st periodic signal F1 was included in period of 2nd periodic signal F2. Also, it can be detected whether period of 2nd periodic signal F2 was included in period of 1st periodic signal F1.
That is, in
In this case, judgment circuit 242 is judged to have an alternating characteristics to the next narrow width pulse.
That is, when, in 1st time when alternating characteristics with a narrow width pulse of 1st periodic signal F1 and the narrow width pulse of 2nd periodic signal F2 disappeared, 7th narrow width pulse of 1st periodic signal F1 was input into judgment circuit 242 in
Note that there is “7th narrow width pulse of 1st periodic signal F1” by all means than “6th narrow width pulse of 2nd periodic signal F2” to the left because the spacing of “6th narrow width pulse of 1st periodic signal F1” and “7th narrow width pulse” is smaller than Δτ and the spacing of “6th narrow width pulse of 1st periodic signal F1” and “6th narrow width pulse of 2nd periodic signal F2” is Δτ. From this, that judgment circuit 242 can detect a time when period of 1st periodic signal F1 shrank than Δτ is understood.
Then, when, in 2nd time when alternating characteristics with a narrow width pulse of 1st periodic signal F1 and the narrow width pulse of 2nd periodic signal F2 disappeared, 9th narrow width pulse of 2nd periodic signal F2 was input into judgment circuit 242 in
In other words, in
As mentioned earlier, in 2nd embodiment, frequency (frequency of, thus, 2nd periodic signal F2) of 1st periodic signal F1 rises in a harmonic progression. In this embodiment, frequency of 1st periodic signal F1 described a case to fluctuate like 1 Hz, 2 Hz, . . . , 5 Hz, 6 Hz, 7 Hz, . . . , 6 Hz, 5 Hz, . . . to make plain (cf.
As described earlier, frequency detecting circuit 24 can detect a time when it grew big than Δτ in a time when a narrow width pulse interval of 1st periodic signal F1 shrank than Δτ because Δτ delays 2nd periodic signal F2 to 1st periodic signal F1.
When period of 1st periodic signal F1 is longer than Δτ, as for driving signal generation circuit 25, as for (when value of voltage eO is small), in drive signal generator 15, an electric switch outputs a control signal becoming the ON to power converters 21 (cf. VGs of
It is different from ΔτB in delay time to 1st periodic signal F1 of 2nd periodic signal F2 in ΔτA and frequency detecting circuit 24B in delay time to 1st periodic signal FA1 of 2nd periodic signal FA2 in frequency detecting circuit 24A. That is, it is ΔτB>ΔτA. When period shrank than ΔτA when period is smaller greatly from ΔτA than ΔτB, as for driving signal generation circuit 25, as for driving signal generation circuit 25, an electric switch outputs OFF and the control signal that it is to power converters 21. When when “period is smaller greatly from ΔτA than ΔτB”, frequency factory automation corresponding to ΔτA is higher than frequency fB corresponding to ΔτB. When “period shrinks than ΔτA”, it is time beyond the frequency factory automation corresponding to ΔτA. And, as for (when it fell from frequency fB), driving signal generation circuit 25 outputs the control signal that an electric switch becomes the ON to power converters 21 when period grew big than ΔτB (cf. VGs of
Judgment circuit 242A detects with power conversion equipment 2 of
When frequency f1 of 1st periodic signal F1 reached upper bound threshold fASH, as for driving signal generation circuit 25, an electric switch outputs OFF and the control signal that it is to power converters 21. And, as for driving signal generation circuit 25, an electric switch outputs OFF and the control signal that it is to power converters 21 when frequency f1 of 1st periodic signal F1 fell to lower limit threshold fBSH (cf. VGs of
(Invention C) :
In impedance circuit 12, one end is connected to input signal path 15, and other end is connected to grand G Impedance circuit 12 includes a plurality of electric switches (SW1-SWM) to change the overall impedance of the impedance circuit into when an on control signal or an off control signal was input, respectively. In impedance circuit 12, impedance components (a resistance element, a capacitative element, reactive element at least one or combinations thereof) are usually provided other than electric switch SW1-SWM. All impedance in impedance circuit 12 was able to include the impedance that electric switch SW1-SWM had, impedance of the electric wiring, but when delay to be described below only in the impedance that electric switch SW1-SWM has, impedance of the electric wiring can be formed, impedance circuit 12 does not need to have an impedance component.
It should be the configuration that can detect the threshold, and detecting circuit 11 can compare the both ends voltage of a resistance element formed on thing voltage at the end of input signal path 15 is spread, and to compare with the value, input signal path 15 with the threshold. Also, the voltage drop to occur because of a resistance ingredient included in input signal path 15 in itself can be compared with the threshold.
Input buffer 14 is connected to the beginning edge of input signal path 15 in
Control circuit 13 can change (delay time signal DS) in the delay time when detecting circuit 11 generates detecting circuit 11 by this which can change impedance of detecting circuit 11 by the combination of an ON state of the electric switch SW1-SM or the off state. In
In this embodiment, each impedance circuit element 12 (k) includes electric switch SW (k), respectively. When on control signal SON was input, this electric switch electric switch SW (k) forms open position between input signal path 15 and gland G and impedance Z (k) (or admittance lateral (k)=1/Z (k)) is formed between input signal path 15 and gland G when off control signal SOFF was input.
Electric switch SW (k) is a transistor, and, in
In this embodiment, the untied impedance of the ON is ZallON, and all electric switches of detecting circuit 11 are represented by an ON-OFF combination of electric switch SW (k). 1/ZallONt=Σ(a(k)/(Z (k))
However, (k) is the coefficient that becomes to “1” at the time of “0”, off when an electric switch is on.) Σ is the totals from 1 to N. Note that all admittance YZallON is represented in YZallON=Σa (k) lateral (k) when it is represented in an admittance.
T1 (Z (1))=τ0
T2 (Z (2))=22τ0
T3 (Z (3))=23τ0 . . .
Tk (Z (k))=2k−1τ0 . . .
TN (Z (N))=2N−1τ0
It is thereby possible for detecting circuit 13 to make spacing of the listing (delay time) equal spacing (with disintegration spacing of the delay time as equality).
In
With power conversion equipment 2 of
It is the figure showing the embodiment that
Frequency detecting circuit 424 consists of delay circuit 1 and judgment circuit 425. Periodic signal generation circuit 423 detects output voltage eO and circuit current equivalency voltage Vi as voltage signal F1, and it is output to judgment circuit 425. Delay control turn (from
In
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-006315 | Jan 2008 | JP | national |
| 2008-006316 | Jan 2008 | JP | national |
| 2008-006317 | Jan 2008 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/071742 | 11/30/2008 | WO | 00 | 10/10/2011 |
