Frequency divider having the power supply connected to the GaAs substrate

Abstract

A frequency divider circuit including a field effect transistor on a semi-insulating substrate including applying a voltage higher than the lowest of the power supply voltages of the frequency divider circuit to the semi-insulating substrate.

Description

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and, more particularly, to a frequency divider circuit on a semi-insulating substrate.

BACKGROUND OF THE INVENTION

FIG. 10 shows a wiring arrangement of a conventional frequency divider circuit on a semi-insulating substrate that such as GaAs substrate is sealed in a flat package. FIG. 11 shows a circuit diagram thereof.

The frequency divider circuit of FIG. 10 includes an input terminal P1 for inputting a signal to be frequency divided, a power supply (VDD) terminal P2, a frequency divider output terminal P3, a ground (GND) terminal P4, a current control terminal P5, a reference voltage input terminal P6, package leads L1 to L8, a frame L.phi. on which an IC substrate 1 is mounted, and bonding wires W1 to W7 connecting the terminals and the leads with each other. Among these wires, wires W4 and W5 connect the ground terminal P4 and the lead L5 via the frame L.phi..

Reference numeral 1 of FIG. 10 designates an IC substrate, and reference numeral 2, represented by dotted line in FIG. 11, designates the package. In FIG. 11, there are provided a power supply voltage terminal V.sub.DD, a current control terminal V.sub.CS, an input terminal IN for a signal to be frequency divided, an input reference voltage terminal V.sub.R, a ground terminal GND, and an output terminal OUT.

As shown in FIGS. 10 and 11, the ground terminal GND is connected to the frame L.phi. of package to stabilize the substrate voltage and circuit operation.

A phase locked loop (hereinafter referred to as "PLL") frequency synthesizer for an automobile telephone using this frequency divider circuit is shown in FIG. 12.

In FIG. 12, a voltage controlled oscillator (hereinafter referred to as "VCO") A1, a frequency divider circuit A2, a reference frequency oscillator A3, a phase comparator A4, and a control circuit A5 of the frequency divider circuit A2 are provided. In the figure, f.sub.0 represents the oscillation frequency of the VCO A1, which is an output of the PLL frequency synthesizer, f.sub.h represents the output of the frequency divider circuit A2, f.sub.r represents a reference frequency, and V.sub.0 represents the output voltage of the phase comparator A4. In this construction, suppose that the frequency division rate of the frequency divider A2 is n, then f.sub.h is as follows.

f.sub.h =f.sub.0 /n (1)

When the frequency f.sub.h is higher than the frequency f.sub.r, the output voltage V.sub.O of the phase comparator A4 is lowered, and when the V.sub.O is thus lowered, that is, the input voltage of the VCO A1 is lowered, f.sub.O is lowered and the following relation is established:

f.sub.h =f.sub.r ( 2) Then, this circuit is stabilized and the output frequency f.sub.O holds a constant value. Accordingly, from the formula (1), the output frequency of the PLL synthesizer, that is, f.sub.O is represented by: f.sub.O =n.multidot.f.sub.h ( 3)

Herein, the frequency division rate n of the frequency divider circuit A2 is variable dependent on the signal supplied from the control circuit A5, and accordingly, the output frequency f.sub.O is also variable.

Furthermore, in order to lower the current consumption of the PLL frequency synthesizer, the operation of the frequency divider circuit may be halted when the circuit is not required for operation of the synthesizer. One way of constructing such a frequency divider circuit is reported in Japanese Published Patent Application 63-294214.

FIG. 13(a) shows a frequency divider circuit having such a halt mode. The V.sub.CS terminal in FIG. 11 is a current switching terminal for this halt mode. The frequency divider circuit 1 operates in accordance with the applied voltage as shown in FIG. 13(b).

In such a system, circuits such as a control circuit or a phase comparator which do not have to operate at high frequency are silicon CMOS ICs and the power supply voltage V.sub.DD is usually a single 5 V power supply. Accordingly, even in a frequency divider circuit which requires operation at high frequency, the 5 V power supply is used. That is, V.sub.DD is 5 V and GND is 0 V in FIG. 11.

This means that the semi-insulating substrate may occasionally be set at 0 V and circuit elements such as an FET or implanted resistor may operate at a voltage close to 4 V as shown in FIG. 16. When the active layer of implantation resistor or FET has a voltage higher than the substrate, the characteristics of the FET or the resistance value of an implanted resistor vary during operation at frequencies from 0 to 5 KHz. The cause thereof is thought to be an electron, hole trapping mechanism (not shown) between the semi-insulating substrate 1 and the active layer 1a as shown in FIG. 16. The mechanism effectively causes electrons and holes to be generated and recombined, changing the voltage applied to the active layer, and modulating the thickness of active layer, as described in greater detail later.

When the characteristics of FET vary or the value of the resistor oscillates in such a frequency divider circuit, the output signal is phase-modulated. When such divider is used in a PLL frequency synthesizer, output signal varies in phase, thereby causing malfunctions such as noise.

The malfunction will be described with reference to FIG. 14. FIG. 14 shows an example of a logic gate including a frequency divider circuit in a source coupled type logic gate.

In FIG. 14, field effect transistors (FET) and J.sub.1 and J.sub.2 are switches and J.sub.3 is a constant current source. The circuit of FIG. 14 also includes load resistors R.sub.L, and a reference voltage generator Vr. V.sub.DD represents a power supply voltage and GND represents a ground voltage. I.sub.1 to I.sub.3 designate currents flowing through the FETs J.sub.1 to J.sub.3, and V.sub.S represents the source voltages of FETs J.sub.1 and J.sub.2, V.sub.IN represents an input voltage, and V.sub.01 and V.sub.02 represent output voltages which are inverted with respect to each other.

When the threshold voltage of this logic gate, V.sub.T, is the same as the input voltage so that the output signals V.sub.01 and V.sub.02 are to equal, the gains of J.sub.1 and J.sub.2 are K, the threshold voltage is V.sub.th, the characteristics of the FETs J.sub.1 and J.sub.2 are equal to each other, and the currents I.sub.1 and I.sub.2 of the FETs J.sub.1 and J.sub.2 become:

I.sub.1 =K(V.sub.IN -V.sub.S -V.sub.th).sup.2 ( 4) I.sub.2 =K(V.sub.r -V.sub.S -V.sub.th).sup.2 ( 5)

Therefore, when the input voltage V.sub.IN is V.sub.T,

I.sub.1 =I.sub.2, (6) and from the formulae (4) and (5), and V.sub.T =V.sub.r. (7)

Now, if the voltage applied to the active layer is changed by the substrate voltage and the gain K varies by .DELTA.K, the active layer of the FET J.sub.2 is modulated and the threshold voltage V.sub.th varies by .DELTA.V.sub.th, the currents I.sub.1 and I.sub.2 become

I.sub.1 =K(V.sub.IN -V.sub.S '-V.sub.th).sup.2 ( 8) I.sub.2 =(K+.DELTA.K){Vr-V.sub.S '-(V.sub.th +.DELTA.V.sub.th)}.sup.2.(9)

When V.sub.IN =V.sub.T ', the threshold voltage of the circuit becomes V.sub.T ' and:

I.sub.3 =I.sub.1 +I.sub.2 ( 10)

Further, from the formula (6), ##EQU1## and from the formula (8), ##EQU2##

Furthermore, from the formulae (11) and (9), ##EQU3## and from the formula (12), ##EQU4## Thus, the variation .DELTA.V.sub.T of V.sub.T becomes, ##EQU5##

The threshold voltage V.sub.T thus varies.

The phase modulation due to the variation in the threshold value will be described with reference to FIG. 15. In FIG. 15, V.sub.IN designates an input signal, V.sub.T and V.sub.T ' designate threshold values of the circuit, and the .DELTA..phi..sub.0 designates phase deviation due to the change in the threshold value.

As shown in FIG. 15, the threshold value V.sub.T changes to V.sub.T ', and the phase information unfavourably varies by .DELTA..phi..sub.0.

Thus, when a phase modulation of .DELTA..phi..sub.0 arises in the output signal in the frequency divider circuit, suppose that the frequency division rate of the frequency divider circuit is n, the total phase error .DELTA..phi. in the PLL frequency synthesizer becomes,

.DELTA..phi.=n.multidot..DELTA..phi..sub.0. (16)

The phase modulation arises in the frequency divider circuit when the frequency divider circuit is operated at an ambient temperature above 60.degree. C. The modulation of the output signal is also low, below -60 dB, and has caused no problem in conventional devices.

As described above, in the conventional frequency divider circuit produced on a semiconductor substrate, since 0 V is applied to the substrate even when the frequency divider circuit is operated at a power supply voltage of 5 V, oscillation between the internal element and substrate occurs due to a so called back gate effect, phase modulating in the output of the frequency divider circuit. This effect particularly occurs when a semi-insulating substrate is employed. This effect especially results in problems in a high speed PLL frequency synthesizer operable at GHz frequencies.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device including a frequency divider circuit in which phase modulation does not occur even using a semi-insulating substrate.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications with in the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to the present invention, a voltage higher than the lowest of the power supply voltages supplied to the frequency divider circuit is applied to the semi-insulating substrate on which a frequency divider circuit is disposed and, during operation of the circuit, the substrate voltage is made high. Thus, an electric field between an FET or resistor on the semi-insulating substrate and the substrate is reduced, thereby preventing oscillationss of the FET characteristics and resistance values, and the phase modulation of the output signal of the frequency divider circuit. Further, since the substrate voltages are increased during only the operation, any increase in the power consumption is suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an arrangement of a package including a frequency divider circuit according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of the package of FIG. 1

FIG. 3 is a diagram of a package arrangement according to a third embodiment of the present invention;

FIGS. 4(a) and 4(b) are a circuit diagram and an operational table of a third embodiment of the invention, respectively.

FIGS. 5 and 6 are a diagram of a package arrangement and a circuit diagram, respectively, of a second embodiment of the present invention;

FIG. 7 is a diagram of a package arrangement according to a fourth embodiment of the invention;

FIGS. 8 and 9 are side views of fifth and sixth embodiments of the present invention, respectively;

FIG. 10 is a diagram showing an arrangement of package of a frequency divider circuit according to the prior art;

FIG. 11 is a circuit diagram of the package of FIG. 10;

FIG. 12 is a diagram showing a PLL frequency synthesizer including a frequency divider circuit;

FIG. 13(a) is a circuit diagram of a frequency divider circuit incorporating a halt mode and FIG. 13(b) is an operational table of the circuit;

FIG. 14 is a circuit diagram of a logic gate in a frequency divider circuit;

FIG. 15 is graph showing the phase error caused by the frequency divider circuit; and

FIG. 16 is a cross-sectional view of a field effect transistor of a frequency divider circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. This figure shows an arrangement of a frequency divider circuit sealed in a package. FIG. 2 shows a circuit diagram thereof. In FIGS. 1 and 2, reference numeral 1 designates a semi-insulating substrate in which a frequency divider circuit is produced and reference numeral 2 designates the package. The circuit includes an input terminal P1 for inputting a signal to be frequency divided, a power supply terminal P2, a frequency divider output terminal P3, a ground terminal P4, a current control terminal P5, and a reference voltage input terminal P6. The substrate 1 is mounted on a frame L.phi. and the leads of package L1 are connected by W1 to W7 to respective terminals. Amongst them, the wire W5 connects the frame L.phi. and the lead L6. Further, IN in FIG. 2 represents an input signal to be frequency divided, V.sub.R a reference voltage, V.sub.DD a power supply voltage, V.sub.CS a current control signal, OUT an output signal, GND a ground voltage, and V.sub.B a substrate power supply voltage.

In this embodiment, the voltage applied to the semi-insulating substrate in which a frequency divider circuit is produced is higher than the lowest one of the power supply voltages supplied to the frequency divider circuit by the substrate power supply V.sub.B. The substrate voltage is controlled so that a voltage independent of V.sub.DD and GND is applied to the frame on which the substrate is mounted. Therefore, when the voltage of the substrate power supply V.sub.B is a fairly high voltage which is close to the power supply voltage, the substrate voltage is made higher than that of the FET and the active layer of implantation resistance in the circuit. As a result, modulation of the thickness of the active layer does not arise.

The reason why an oscillation due to modulation of active layer arises when the substrate voltage is lower than the voltage of the channel, as described in the prior art, is as follows.

When the substrate voltage is low and the voltage of the channel is high, traps in the substrate capture electrons from the channel and substrate. When the traps are filled with electrons, electrons are emitted from the traps. Repetition of this capture and emission produces a voltage difference between the substrate and the channel, the depth of the depletion layer changes, and the thickness of the active layer varies. When the substrate voltage is raised as in the present invention, the electric field between the substrate and the channel is weakened and the influences of the traps are weakened, thereby removing the above-described oscillations. Thus, the output signal of the frequency divider circuit will not be phase-modulated and an accurate frequency divided output signal is obtained.

FIGS. 5 and 6 show a second embodiment of the present invention. In this second embodiment, the substrate power supply voltage V.sub.B is the power supply voltage V.sub.DD. This power supply voltage V.sub.DD is connected to the frame L.phi. by a wire W.

In this second embodiment, because the substrate voltage V.sub.B is set at V.sub.DD, modulation of the thickness of the active layer can be prevented and an accurate frequency division output is obtained as described in the first embodiment. Furthermore, it is not necessary to provide another power supply for the substrate voltage V.sub.B which simplifies circuit construction.

FIGS. 3 and 4(a) show a third embodiment of the present invention. In this third embodiment, the substrate voltage V.sub.B is set at the voltage of a current control terminal V.sub.CS for turning the frequency circuit ON or OFF. The current control terminal V.sub.CS is connected to the frame L.phi. by the wire W5.

In this third embodiment, because the substrate voltage V.sub.B is set at V.sub.CS, the substrate voltage is close to V.sub.DD in the operation of the frequency divider circuit and is close to ground when the frequency divider circuit is halted. Therefore, during operation modulation of the thickness of the active layer can be prevented, thereby obtaining an accurate frequency divided output signal.

Furthermore, when the frequency divider circuit is halted, it is quite natural that the current flowing through the frequency divider circuit is reduced, that the substrate voltage is made ground, and that the FET and the active layer 1a of the implantation resistor are made thin by the depletion layer extending from the interface with the substrate 1. Thus, leakage current does not flow, and the power supply current of frequency divider circuit can be reduced to a great extent.

In the above-described first, second, and third embodiments, as a method of applying a voltage to the substrate, respective power supply terminals are connected to the frame of package by wire bonding, and the voltages are applied to the substrate from its rear surface. However, this may also be achieved by another other method.

FIG. 7 shows a fourth embodiment of the present invention. In this embodiment, an Al electrode pattern of V.sub.CS electrode is produced in a contour configuration at the upper surface of semi-insulating substrate 1, and whereby the V.sub.CS voltage is given to the substrate from the upper surface of substrate.

FIG. 8 shows a fifth embodiment of the present invention. In this fifth embodiment, a via-hole aperture penetrates from the front surface of substrate to the rear surface so that the V.sub.CS voltage may be applied to the substrate from the rear surface B3.

In more detail, in the device of FIG. 8, there are provided a bonding wire W1, a circuit pattern B1, and a via-hole aperture B2 which penetrates the substrate from the front surface to the rear surface. This via-hole aperture B2 is produced by dry etching from the front surface of substrate to the rear surface thereof. Reference character B3 designates a rear surface electrode.

FIG. 9 shows a sixth embodiment of the present invention. In this sixth embodiment, a conductive layer B4 is disposed in the semi-insulating substrate, and a voltage is applied to this conductive layer from the front surface of the substrate.

In more detail, in the device of FIG. 9, a conductive layer B4 is disposed in the substrate 1, and the V.sub.CS voltage is applied to this conductive layer B4 from the terminal P5. When the V.sub.CS voltage is applied by the conductive layer B4 to the substrate 1 on which a circuit pattern B1 is produced, similar effects to those described above are obtained.

In the above-illustrated embodiments of FIGS. 7, 8, and 9, the V.sub.CS voltage is applied to the substrate. However, another power supply voltage which makes the substrate voltage high may be applied to the substrate with the same effects as described above.

As is evident from the foregoing description, according to the present invention, a semi-insulating substrate in which a frequency divider circuit is produced is made a higher voltage than that of the active layer of the circuit element. Therefore, there is no oscillation of circuit element and no phase modulation in the output signal of frequency divider circuit. Accordingly, an accurate output signal is obtained.

Claims

1. A frequency divider for dividing the frequency of an input signal to produce an output signal of lower frequency than the input signal comprising a frequency divider circuit formed in a semi-insulating GaAs substrate and including a field effect transistor having an active layer in the semi-insulating GaAs substrate, the frequency divider circuit having a power supply terminal for supplying power to the frequency divider circuit, a ground terminal, and a control terminal for applying a control signal to activate and deactivate frequency division by the frequency divider circuit wherein the power supply terminal is directly electrically connected to the semi-insulating GaAs substrate whereby changes in substrate potential do not modulate the active layer, thereby avoiding phase shifting of the output signal.

2. The frequency divider of claim 1 wherein the substrate has opposed first and second surfaces, the field effect transistor is disposed at the first surface of the substrate, and the power supply terminal is connected to the substrate at the first surface.

3. The frequency divider of claim 1 wherein the substrate includes an electrically conducting via hole penetrating through the substrate from the first surface to the second surface, the field effect transistor is disposed at the first surface, and the power supply terminal is connected to the substrate at the front surface and through the via hole to the rear surface.

4. A frequency divider for dividing the frequency of an input signal to produce an output signal of lower frequency than the input signal comprising a frequency divider circuit formed in a semi-insulating GaAs substrate and including a field effect transistor having an active layer in the semi-insulating GaAs substrate, the frequency divider circuit having a power supply terminal for supplying power to the frequency divider circuit, a ground terminal, and a control terminal for applying a control signal to activate and deactivate frequency division by the frequency divider circuit wherein the control terminal is directly electrically connected to the semi-insulating GaAs substrate whereby changes in substrate potential do not modulate the active layer, thereby avoiding phase shifting of the output signal.