Claims
- 1. A frequency divider for reducing the frequency of a clock signal by an odd numbered factor n, where n is an integer value, comprising:
a clock generator circuit for receiving the clock signal and for providing an n-divided clock signal having a first and second logic level, the clock generator circuit driving the n-divided clock signal from the first logic level to the second logic level in response to a reset signal; and, a clock delay circuit for activating the reset signal at n clock transitions after receiving the first logic level of the n-divided clock signal, and for deactivating the reset signal within n clock transitions after receiving the second logic level of the divided clock signal, the clock generator circuit driving the n-divided clock signal from the second logic level to the first logic level at n clock transitions after activation of the reset signal.
- 2. The frequency divider of claim 1, wherein the clock generator circuit includes a first resettable flip-flop having a data input connected to a supply voltage and a reset input for receiving the reset signal.
- 3. The frequency divider of claim 2, wherein the clock delay circuit includes a second resettable flip-flop having a data input for receiving the divided clock signal and a reset input for receiving the reset signal, the second resettable flip-flop providing a delayed n-divided clock signal, and
at least one pair of serially connected non-resettable flip-flops receiving the delayed n-divided clock signal from the second resettable flip-flop for activating and deactivating the reset signal.
- 4. The frequency divider of claim 3, wherein the first resettable flip-flop and the first non-resettable flip-flop of each pair of non-resettable flip-flops receive the clock signal, and the second resettable flip-flop and the second non-resettable flip-flop of each pair of non-resettable flip-flops receive an inverted clock signal.
- 5. The frequency divider of claim 4, wherein an output of the at least one serially connected pair of non-resettable flip-flops are connected to the reset inputs of the first and second resettable flip-flops.
- 6. The frequency divider of claim 5, wherein the first resettable flip-flop, the second resettable flip-flop, and the pair of non-resettable flip-flops are data inverting flow through flip-flops.
- 7. The frequency divider of claim 4, wherein each resettable flip-flop includes an input circuit receiving a pair of input signals in response to a first transition of the clock signal for inverting a logic level of the input signals at complementary output terminals during an active phase of operation;
an input latch circuit for latching the logic states of the complementary output terminals in response to a second transition of the clock signal during the active phase of operation; a reset circuit for driving the complementary output terminals to preset logic states in response to the second transition of the clock signal during a reset phase of operation; and, a reset latch circuit for latching the preset logic states of the complementary output terminals in response to the first transition of the clock signal during the reset phase of operation.
- 8. The frequency divider of claim 1, wherein the n clock transitions include transitions in both positive and negative directions.
- 9. The frequency divider of claim 1, wherein each resettable flip-flop includes a first load device connected between VCC and one of the complementary output terminals,
a second load device connected between VCC and an other of the complementary output terminals, a first input transistor having a collector connected to the one of the complementary output terminals and a base for receiving one of the pair of input signals, a second input transistor having a collector connected to the other of the complementary output terminals and a base for receiving an other of the pair of input signals, the emitters of the first and second input transistors being connected to each other, a first mode transistor having a collector connected to the emitters of the first and second input transistors and a base for receiving the reset signal, a first pair of cross-coupled transistors having collectors connected to the complementary output terminals, a second mode transistor having a collector connected to the emitters of the first pair of cross-coupled transistors and a base for receiving an inverted reset signal, the emitters of the first and second phase transistors being connected to each other, a first clock transistor having a collector connected to the emitters of the first and second mode transistors, an emitter connected to VEE, and a base for receiving the clock signal, a second pair of cross-coupled transistors having collectors connected to the complementary output terminals, a third mode transistor having a collector connected to the emitters of the second pair of cross-coupled transistors and a base for receiving the reset signal, a first reset transistor having a collector connected to the one of the complementary output terminals and a base connected to VCC, a second reset transistor having a collector connected to the other of the complementary output terminals and a base for receiving a reference voltage, the emitters of the first and second reset transistors being connected to each other, a fourth mode transistor having a collector connected to the emitters of the first and second reset transistors and a base for receiving the inverted reset signal, and a second clock transistor having a collector connected to the emitters of the third and fourth phase transistors, an emitter connected to VEE, and a base for receiving an inverted clock signal.
- 10. A frequency divider for reducing the frequency of a clock signal by a factor of three, comprising:
a clock generator circuit having a data input for receiving a supply voltage, a clock input for receiving the clock signal and a reset input for receiving a reset signal, for providing a divide-by-3 clock signal having a first and second logic level from an output terminal, the clock generator circuit driving the divide-by-3 clock signal from the first logic level to the second logic level in response to the reset signal; first, second and third serially connected clock delay flip-flops each receiving the clock signal for receiving the divide-by-3 clock signal and for activating the reset signal at three clock transitions after receiving the first logic level of the divide-by-3 clock signal, and for deactivating the reset signal within three clock transitions after receiving the second logic level of the divide-by-3 clock signal, the clock generator circuit driving the divide-by-3 clock signal from the second logic level to the first logic level at three clock transitions after activation of the reset signal.
- 11. The frequency divider of claim 10, wherein the clock generator circuit includes a resettable flip-flop.
- 12. The frequency divider of claim 11, wherein the first clock delay flip-flop is a resettable flip-flop having a reset input.
- 13. The frequency divider of claim 12, wherein the second and third clock delay flip-flops are non-resettable flip-flops.
- 14. The frequency divider of claim 13, wherein the clock generator circuit and the second clock delay flip-flop receives the clock signal, and the first clock delay flip-flop and the third clock delay flip-flop receives an inverted clock signal.
- 15. The frequency divider of claim 14, wherein an output of the third clock delay flip-flop is connected to the reset inputs of the clock generator circuit and the first clock delay flip-flop.
- 16. The frequency divider of claim 11, wherein the clock generator circuit, the first, second and third clock delay flip-flops are data inverting flow through flip-flops.
- 17. An RF divider system for providing divided clock signals from a clock signal comprising:
a divide-by-3 sub-block receiving the clock signal for providing a divide-by-3 clock signal; a divide-by-2 sub-block receiving the clock signal for providing a divide-by-2 clock signal; a divide-by-1 sub-block receiving the clock signal for providing a divide-by-1 clock signal; a bias circuit for selectively coupling a current signal to one of the divide-by-3 sub-block, the divide-by-2 sub-block and the divide-by-1 sub-block; and, a decoder circuit receiving sub-block selection signals for controlling the bias circuit.
- 18. The RF divider system of claim 17, wherein the divide-by-3 sub-block includes a clock input buffer for buffering the clock signal;
a divide-by-3 circuit for generating a pre-buffered divide-by-3 clock signal from the buffered clock signal; and, a clock output buffer for buffering the pre-buffered divide-by-3 clock signal to provide the divide-by-3 clock signal.
- 19. The RF divider system of claim 18, wherein the divide-by-3 circuit includes
a clock generator circuit for receiving the buffered clock signal and for providing the pre-buffered divide-by-3 clock signal having a first and second logic level, the clock generator circuit driving the pre-buffered divide-by-3 clock signal from the first logic level to the second logic level in response to a reset signal; and, a clock delay circuit for activating the reset signal at three clock transitions after receiving the first logic level of the pre-buffered divide-by-3 clock signal, and for deactivating the reset signal within three clock transitions after receiving the second logic level of the pre-buffered divide-by-3 clock signal, the clock generator circuit driving the pre-buffered divide-by-3 clock signal from the second logic level to the first logic level at three clock transitions after activation of the reset signal.
- 20. A method for generating an n-divided clock signal having a 50% duty cycle at an output of a clock generator from a clock signal, where n is an integer value, comprising:
a) switching the clock generator to an active phase of operation; b) driving the output of the clock generator to a first logic level in the active phase of operation; c) activating a reset signal for switching the clock generator circuit to a reset phase of operation at n clock signal transitions after the output of the clock generator is driven to the first logic level; d) driving the output of the clock generator to a second logic level in the reset phase of operation; and, e) deactivating the reset signal for switching the clock generator to the active phase of operation at n clock signal transitions after the output of the clock generator is driven to the second logic level.
- 21. The method for generating an n-divided clock signal of claim 20, wherein the step of driving the output of the clock generator to the first logic level includes delaying activation of the reset signal until the nth clock signal transition after the n-divided clock signal is driven to the first logic level.
- 22. The method for generating an n-divided clock signal of claim 20, wherein the first logic level of the divided clock signal is a high logic level and the second logic level of the divided clock signal is a low logic level.
- 23. The method for generating an n-divided clock signal of claim 20, wherein the step of deactivating the reset signal includes delaying deactivation of the reset signal until n−1 system clock signal transitions after the n-divided clock signal is driven to the second logic level.
- 24. A resettable flip-flop circuit responsive to a clock signal comprising:
an input circuit receiving a pair of input signals in response to a first transition of the clock signal for inverting a logic level of the input signals at complementary output terminals during an active phase of operation; an input latch circuit for latching the logic states of the complementary output terminals in response to a second transition of the clock signal during the active phase of operation; a reset circuit for driving the complementary output terminals to preset logic states in response to the second transition of the clock signal during a reset phase of operation; and, a reset latch circuit for latching the preset logic states of the complementary output terminals in response to the first transition of the clock signal during the reset phase of operation.
- 25. The resettable flip-flop circuit of claim 24, wherein the input circuit includes a differential pair of transistors for receiving the pair of input signals,
a load circuit for coupling a first supply voltage to each of the differential pair of transistors and to each of the complementary output terminals, and a pair of control transistors serially connected between the differential pair of transistors and a second supply voltage for receiving a reset signal and the clock signal.
- 26. The resettable flip-flop circuit of claim 24, wherein the input latch circuit includes a pair of cross-coupled transistors and a pair of control transistors serially connected between the cross-coupled transistors and a second supply voltage for receiving a reset signal and the clock signal.
- 27. The resettable flip-flop circuit of claim 24, wherein the reset latch circuit includes a pair of cross-coupled transistors and a pair of control transistors serially connected between the cross-coupled transistors and a second supply voltage for receiving a reset signal and the clock signal.
- 28. The resettable flip-flop circuit of claim 24, wherein the reset circuit includes
a first reset transistor connected to one of the complementary output terminals, and having a control terminal connected to a power supply voltage,
a second reset transistor connected to the other of the complementary output terminals and the first reset transistor, and having a control terminal biased to a reference voltage level, and a pair of control transistors serially connected between the common first and second transistor terminals and a second supply voltage, for receiving a reset signal and the clock signal.
- 29. The resettable flip-flop circuit of claim 28, wherein the reference voltage level is generated by a voltage divider circuit.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to U.S. Provisional Application No. 60/372,425 filed on Apr. 16, 2002, the contents of which are incorporated herein, by reference, in their entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60372425 |
Apr 2002 |
US |