Patent Application
20100190463
The present disclosure relates generally to methods and systems related to frequency dividers, and more particularly to radio frequency (RF) frequency dividers.
Frequency dividers are used in many applications to reduce the frequency of an input signal to make it more suitable for processing. Although it is easy to construct frequency dividers which are reliable at relatively low frequencies, for example by using flip-flops, it becomes much more challenging to design frequency dividers that are reliable at relatively high frequencies.
State-of-the art frequency dividers that are capable of handing relatively high frequencies suffer from a shortcoming in that they require a relatively high rail-to-rail (e.g., VCC to VEE) voltage. This relatively high rail-to-rail voltage can cause problems. For example, high voltages, particularly when used at high switching frequencies, give rise to high power densities for integrated circuits. These high power densities, somewhat like a stovetop burner, cause an integrated circuit to heat up. If high power densities remain unchecked, they can destroy the integrated circuit and/or the electronic device on which the integrated circuit is included.
Several different approaches can be used, singly or in combination, to limit heating due to high-power densities. In one approach, cooling fans, heat sinks, and the like can be used to attempt to pull heat from the integrated circuit to cool it. Although these components are often somewhat effective, they create additional expense for the integrated circuit module and also increase the size of the integrated circuit module. Therefore, these types of cooling components are less than ideal. Consequently, improved frequency dividers that can operate effectively at high frequencies and low power densities are needed.
The following presents a simplified summary. This summary is not an extensive overview, and is not intended to identify key or critical elements. Rather, the primary purpose of the summary is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
One embodiment relates to a frequency divider. The frequency divider includes an active mixer having a first mixer input, a second mixer input, and a mixer output. The first mixer input is adapted to receive an input signal having an input frequency, and the mixer output is adapted to provide a mixed signal based on the input signal. The frequency divider also includes an amplification element having an amplification input and an amplification output. The amplification input is adapted to receive the mixed signal and the amplification output is adapted to provide an amplification output signal having an output frequency. A feedback path, which includes an alternating current (AC) coupling element, couples the amplification output to the second mixer input. Other systems and methods are also disclosed.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations. These are indicative of only a few of the various ways in which the principles disclosed may be employed.
One or more implementations will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. It will be appreciated that nothing in this specification is admitted as prior art.
As the inventors have appreciated, in comparison to using cooling fans or other cooling components to limit heating of a frequency divider integrated circuit, a better solution is to reduce the rail-to-rail voltage at which the frequency divider can operate. This reduction in rail-to-rail voltage reduces power density, and thereby limits undesirable integrated circuit heating without the expense associated with cooling fans, etc. In addition, reducing the rail-to-rail voltage of the frequency divider has an additional advantage in that it may make the frequency divider more easily compatible with other integrated circuits that use a similar low-voltage supply voltage. For example, a frequency divider can be designed to share a common supply voltage of about 2.7 V or about 3.3 V with CMOS integrated circuits, thereby easing integration of several integrated circuits. In some embodiments of the present disclosure, this voltage reduction is achieved by including an AC-coupling element on a feedback path of the frequency divider. This AC-coupling element allows the frequency divider to operate at lower rail-to-rail voltages than previously achievable.
During operation, the dynamic frequency divider 100 receives an input signal having an input frequency on the input 102, and outputs an output signal having an output frequency on the output 104. Typically, the input frequency is an integer multiple of the output frequency—in other words, the frequency divider reduces the input frequency down to some lesser output frequency. For purposes of illustration, one example is discussed below where the input signal has an input frequency of approximately 100 GHz and the output signal has an output frequency of approximately 50 GHz. It will be appreciated that the concept is equally applicable to other frequencies, and is particularly advantageous in the RF range.
More particularly, the input signal, fin, is received on the first mixer input 108, and a feedback signal, fout′, is received on the second mixer input 110. The active mixer 106 multiples these signals together, thereby providing a mixed signal having frequency components at fin+fout′ at fin−fout′. Thus, in this example where the input signal has a frequency of 100 GHz, the mixed signal has frequency components at 50 GHz (i.e., fin−fout′) and 150 GHz (i.e., fin+fout′). Although other harmonics may also be present in the mixed signal, they are omitted in this discussion for simplicity.
The mixed signal on mixer output 112 is optionally received and processed by the low-pass filter 114, which removes unwanted frequency components therefrom. In the illustrated example, the low pass filter 114 removes the 150 GHz frequency component, thereby passing the 50 GHz component (i.e., fin−fout′) to the low pass filter output 116.
The amplifier 118 receives and amplifies the filtered signal, thereby generating the output signal fout on the output 104. As shown, the output signal fout has frequency of about 50 GHZ in this example.
After amplification, the output signal fout is fed back on the feedback path 120, which includes the AC coupling element 122. The AC-coupling element 122 can be thought of as passing the frequency components from the output signal fout to the second mixer input 110, and simultaneously blocking the DC voltage in the output signal fout from reaching the second mixer input 110. In place of the blocked DC voltage, the AC-coupling element generates another DC voltage which is provided to the second mixer input 110. For example, in one embodiment fout has a 50 GHz frequency with a DC offset of about 0.8 V, while fout′ also has a 50 GHz frequency but with a DC offset of about 2.5 V. This “blocking” of the DC offset allows the active mixer 106 to use a reduced rail-to-rail voltage relative to previous solutions, and may also improve frequency performance (see
In this manner, the frequency divider 100 can cut a frequency of an input signal down to a lower frequency that is more suitable for use in a given system. In addition, because this frequency divider 100 facilitates a reduced rail-to-rail voltage, the frequency divider 100 alleviates some shortcomings of previous solutions. For example, the frequency divider 100 may exhibit a lower power density than previous solutions and may enable easier integration than previously achievable.
The Gilbert mixer 106A includes a first differential mixer input 108A (on which the input signal is received), a second differential mixer input 110A (on which the feedback signal is received), and a differential mixer output 112A (on which a mixed output signal is provided). An RF stage 201 is coupled to the first differential mixer input 108A and includes a pair of RF-stage transistors 202, 204 and a current source 206. A local oscillator (LO) stage 207 is coupled to the second differential mixer input 110A and includes four LO-stage transistors 208, 210, 212, 214. In this example, the transistors in the RF-stage 201 and LO-stage 207 are shown as bipolar junction transistors (BJTs), but they could also be metal oxide semiconductor transistors (MOSFETs) or some other type of transistor. Resistors 216, 218 are also present and separate collectors of the LO stage 207 from the DC supply voltage (VCC).
The differential mixer output 112A is coupled to an amplifier 118A made of a series of emitter follower stages, which collectively act to increase the gain of the circuit. The emitter follower stages may be arranged as “gain boosters” or Darlington pairs, where two transistors are cascaded together to act as a single transistor. Thus, a first emitter follower stage includes a first BJT 220 and first resistor 228; and a second emitter follower stage includes a second BJT 222 and a second resistor 232. The base of the first BJT 220 is coupled to a first leg of the differential mixer output 112A, and a base of the second BJT 222 is coupled to the emitter of the first BJT 220. A third emitter follower stage includes a third BJT 224 and a third resistor 230, and a fourth emitter follower stage includes a fourth BJT 226 and a fourth resistor 234. The base of the third BJT 224 is coupled to a second leg of the differential mixer output 112A, and a base of the fourth BJT 226 is coupled to the emitter of the third BJT 224.
The frequency divider in
More particularly in the AC-coupling element 122A, a first capacitor 236 is in series between a first leg of the differential output 104A and a first leg of the second differential mixer input 110A; and a second capacitor 238 is in series between a second leg of the differential output 104A and a second leg of the second differential mixer input 110A. Typically, the first and second capacitors 236, 238 have equal capacitances. Often, these capacitors do not limit the lower operating frequency limit of the frequency divider because dynamic frequency dividers do not operate down to very low frequencies even when they are DC coupled. Therefore, in some embodiments, the first and second capacitors 236, 238 have a relatively small capacitor value, such as between about 200 fF and about 1 pF, and can be integrated on chip as metal-insulator-metal (MIM) capacitors or using parallel-plate capacitors in the metallization layers of the integrated circuit.
Biasing resistors 240, 242 are arranged to establish a suitable bias voltage to the second differential mixer input 110A. For example, in one embodiment where the VCC supply voltage is approximately 2.7 V, the biasing resistors 240, 242 could be ratioed to provide a bias voltage of about 2.5 V to the points on the feedback path between the capacitors 236, 238 and the second differential mixer input 110A. The other resistors 244, 246 are arranged to deliver the bias to the points and are typically equal in value to one another.
Although FIG. 2A's embodiment shows the legs of the differential output 104A as coupled to the last emitter follower stages (i.e., second and fourth emitter follower stages having transistors 222 and 226, respectively); other arrangements are possible. For example,
In addition, although
As
Some aspects of the present disclosure are also applicable to frequency dividers having mixers that include a trans-impedance amplifier. For example,
Now that some examples of systems have been discussed, reference is made to
For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required. Further, one or more of the acts 25 depicted herein may be carried out in one or more separate acts or phases.
At 602, a radio frequency (RF) input signal is provided. For example, in some embodiments the RF input signal could be provided with a frequency ranging from about 76 GHz to about 81 GHz.
At 604, the RF input signal is mixed with a feedback signal, thereby generating a mixed signal. Because the feedback signal has an output frequency that is a unit fraction of the input frequency, the mixed signal has a frequency component equal to the difference between the input frequency and the output frequency.
At 606, the mixed signal is amplified to provide a downconverted signal having the output frequency. In one embodiment, for example, the downconverted signal is generated to have an output frequency that is one-half of the input frequency, although other unit fractions could also be generated.
At 608, the feedback signal is generated by adjusting a DC offset of the downconverted signal. The feedback signal concurrently retains the output frequency of the downconverted signal.
Although one or more implementations has been illustrated and/or discussed above, alterations and/or modifications may be made to these examples without departing from the spirit and scope of the appended claims.
For example, although some embodiments have been illustrated and described above in which a Gilbert mixer comprised of BJTs, it will be appreciated that other types of transistors, including but not limited to: metal oxide semiconductor field effect transistors (MOSFETs), junction gate field effect transistors (JFETs), insulated gate field effect transistors (IGFETs), insulated gate bipolar transistors (IGBTs); constitute legal equivalents of these BJTs. These transistors may be made of silicon in some embodiments, but may also be made of other materials, including but not limited to: germanium, gallium arsenide, silicon carbide, and others. Similarly, the emitter followers could include transistors other than BJTs, and could be made of silicon or other materials. In typical embodiments, a frequency divider is formed on a single monolithic integrated circuit, but the frequency divider functionality could also be split between several different integrated circuits.
Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through direct electrical connection, or through an indirect electrical connection via other devices and connections. Although various numeric values are provided herein, these values are just examples and do not limit the scope of the disclosure. Also, all numeric values are approximate.
In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
