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1. Field
This disclosure relates to circuitry for dividing the frequency of a signal.
2. Description of the Related Art
Frequency dividers are used in frequency synthesizers for many applications and in test and measurement equipment. Some application require a frequency divider to provide a symmetrical output with 50% duty factor, even when the frequency is divided by an odd integer.
Throughout this description, the embodiments and examples shown should be considered as exemplars, rather than limitations on the apparatus and methods disclosed or claimed.
Description of Apparatus
Throughout the drawings, elements have been assigned three digit reference designators where the most significant digit is the drawing number and the two least significant digits define an element. Common elements having the same function in multiple figures will have reference designators with the same least significant digits. The description of common elements will not be repeated for each and every figure. An element that is not described in conjunction with a figure may be presumed to have the same function as that described for the counterpart element in a preceding figure. Reference designators used in timing diagrams have the same least significant digits as the corresponding signal line or element in the preceding figure.
Referring now to
The second means 140 may be comprised of a second divide-by-N circuit 150 and a second divide-by-2 circuit 160. The second divide by N circuit 150 may provide a second 1/N signal 125 every N clock cycles. The second divide-by-N circuit 150 may be implemented as described for the first divide-by-N circuit 120. The first divide-by-N circuit 120 and the second divide-by-N circuit 150 may or may not be implemented in the same manner. The output of the second divide-by-2 circuit 160 is the second divided signal 165, which has a 50% duty factor and a frequency equal to the frequency of the input clock signal 100 divided by 2N.
The first divided signal 135 and the second divided signal 165 are both symmetrical signals having 50% duty factor and a frequency equal to the input clock frequency divided by 2N. The third means controls the relative phase of the first and second divided signals 135/165 such that the first and second divided signals 135/165 differ in phase by one-quarter cycle or 90 degrees. Combining the first divided signal 135 and the second divided signal 165 with exclusive OR function 170 provides an output signal having 50% duty factor and a frequency equal to the frequency of the input clock signal 100 divided by N.
The first means 110 and the second means 140 may be synchronous circuits where all internal and external signals change in response to a rising edge or a falling edge of a clock signal. All of the timing diagrams in this description assume the circuits are responsive to the rising edge of the clock.
The frequency divider, including first means 110, second means 140, third means 180, and exclusive OR function 170 may be implemented by software instructions executed on a processor. The frequency divider may be implemented in hardware or a combination of hardware, firmware and software. The frequency divider hardware may include one or more of logic arrays, digital circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), programmable logic devices (PLDs) and programmable logic arrays (PLAs).
The frequency divider may be implemented on a single integrated circuit chip. For high speed applications, the frequency divider may be implemented using Silicon, Silicon-Gemanium, Gallium Arsenide, Indium Phosphide, or other integrated circuit technology. The frequency divider may be implemented with any static logic family, including, but not limited to, conventional static complementary metal-oxide-semiconductor (CMOS) logic, differential current-mode logic (CML) using field-effect or bipolar devices, and emitter-coupled logic (ECL) bipolar logic families including positive emitter coupled logic (PECL) and low voltage positive emitter coupled logic (LVPECL).
The first divided signal (line 230, labeled “1st DS) and the second divided signal (line 260, labeled “2nd DS) are square waves with 50% duty factor and a frequency equal to the frequency of the input clock (line 200) divided by 2N (2×5=10 in this example). The output signal 270 from the exclusive OR gate has 50% duty cycle and a frequency equal to the frequency of the input clock (line 200) divided by N (5 in this example).
The first T flip-flop 330 is a known circuit where the output Q changes state in response to a clock if the T input is logical “1”, and holds the previous state if the T input is logical “0”. A T flip-flop may be implemented as a J-K flip flop with the J and K inputs connected together to form the T input.
The first comparator 323 compares the Qi outputs from the first counter 320 to the value N−1. The output 325 from the first comparator 323 feeds the PS input on the first counter 320 such that the first counter 320 is preset to zero on the clock cycle after the Qi outputs reach a value of N−1. Thus the first counter 320 counts cyclically between zero and N−1. The output 325 from the first comparator 323 also feeds the T input of the first toggle flip-flop 330.
The second means 340 for dividing the frequency of an input clock signal by N and then by 2 may be comprised of a second counter chain including a second up-counter 350, a second comparator 353, and a second T flip flop 360. The functionality of the second counter 350 may be the same as that described for the first counter 320. The second comparator 353 compares the Qi outputs from the second counter 350 to the value N−1. The output 355 from the second comparator 353 drives the T input of the second toggle flip-flop 360. The output 325 from the first comparator 323 drives the PS input of the second counter 350, and causes the second counter 350 to be preset to a value of (N−1)/2. Using the same signal 325 to preset the first counter 320 and the second counter 350 to different values is an implementation of the third means to control the relative phase of the first and second divided signals 335/365.
The second T flip-flop 360 may have an input 362, labeled “CLR”, to inhibit toggling and thus force the second divided signal 365 to a fixed logical state where the first divided signal 365 is continuously either “0” or “1”. With the toggling of the second T flip-flop 360 inhibited, the output for the exclusive OR gate 370 will have the same frequency as the first divided signal 335. In this manner, the first means 310 can be used to divide the input clock frequency by an even number N. When dividing by an even number, the first comparator 323 may compare the Qi outputs from the first counter 320 to the value N/2-1.
A buffer 300 may accept the input clock signal (Clock In) and may provide a first clock 302 and a second clock 304. The second clock 304 may be the complement, or inverse, of the first clock 302. The first means 310 may be responsive to the first clock 302. The second means 340 may be responsive to the second clock 304, as shown. Alternately, the first means 310 may be responsive to a rising edge of a clock and the second means may be responsive to the falling edge of the same clock. Additionally, the first means 310 and the second means 340 may be implemented with circuitry that requires a differential clock. In this case, the polarity of the clock signals would be reversed for the first means 310 and the second means 340.
Note that the rising edge of the output 470 is synchronous with the rising edge of the first clock 402, and the falling edge of the output 470 is synchronous with the rising edge of the complementary second clock 404. Thus the output 470 will have precisely 50% duty cycle if the first and second clocks 402 and 404 are complementary and have 50% duty cycle. In cases where a precise 50% duty cycle is desired for the output 470, additional circuitry may be required to ensure the input clock also has a precise 50% duty cycle. The output 470 will also have a 50% duty cycle if the rising edge of the second clock 404 occurs precisely at the mid-point between successive rising edges of the first clock 402.
Any error in the phase or duty cycle of the clock signals will not be multiplied when the frequency is divided. For example, assume that the first and second clocks have a frequency of 1 MHz but are asymmetric by 100 nanoseconds (ns) such that the first clock 402 is “0” for 450 ns and “1” for 550 ns and the second clock 404 is the complement of the first clock 402. After dividing by seven, the output 470 will have a period of 7 microseconds (us) but will also be asymmetric by 100 ns (logic “0” for 3.450 and Logic “1” for 3.550 us).
The frequency divider of
Returning briefly to
In contrast to
Any of the previously described frequency dividers and the subsequently described frequency division process may be incorporated within frequency synthesizers or in frequency counters for a variety of applications.
Description of Processes
Referring back to
Closing Comments
The foregoing is merely illustrative and not limiting, having been presented by way of example only. Although examples have been shown and described, it will be apparent to those having ordinary skill in the art that changes, modifications, and/or alterations may be made.
Although many of the examples presented herein involve specific combinations of method acts or system elements, it should be understood that those acts and those elements may be combined in other ways to accomplish the same objectives. With regard to flowcharts, additional and fewer steps may be taken, and the steps as shown may be combined or further refined to achieve the methods described herein. Acts, elements and features discussed only in connection with one embodiment are not intended to be excluded from a similar role in other embodiments.
For means-plus-function limitations recited in the claims, the means are not intended to be limited to the means disclosed herein for performing the recited function, but are intended to cover in scope any means, known now or later developed, for performing the recited function.
As used herein, whether in the written description or the claims, the terms “comprising”, “including”, “carrying”, “having”, “containing”, “involving”, and the like are to be understood to be open-ended, i.e., to mean “including but not limited to”. Only the transitional phrases “consisting of” and “consisting essentially of”, respectively, are closed or semi-closed transitional phrases with respect to claims.
Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.
As used herein, “and/or” means that the listed items are alternatives, but the alternatives also include any combination of the listed items.