Frequency divider with variable modulo

Abstract

The field is that of variable-modulo frequency dividers. To obtain a fast variable-modulo divider over a wide operating range the idea of the invention is to use twin flip-flops (1, 2; 3, 4; 5, 6; 7, 8) for the feedbacks. The benefit of this configuration is that it avoids the use of decoding gates between the flip-flops this increasing the propagation times of the feedback signals.

Description

The present invention relates to a variable-modulo frequency divider.

It applies in particular to constructions of frequency synthesizers with high spectral purity using variable-rank dividers operating at high frequencies with low modulos.

To construct dividers with low division ranks it is known practice to use commercial synchronous counters of the type for example of those marketed under the references 54163 and 10136 respectively by the companies registered in the United States TEXAS INSTRUMENTS and MOTOROLA or to use flip-flops linked in cascade according to the diagram of FIG. 1 which is that of a divider with two modulos 4 and 5 or else according to diagrams adopted in integrated circuits of the type for example of that which is marketed under the reference SP8680 by the company registered in Britain General Electric Company, or else according to patent application JP-A-63-283316.

However, commercial counters and constructions of dividers by means of cascaded flip-flops exhibit limited operation within the high frequencies. This is mainly due, in constructions of the type of those of FIG. 1 , to the presence of feedback logic gates which increase the propagation times of the signals between the outputs of the flip-flops and the feedback input of the first flip-flop.

Other types of construction of dividers of the type of that shown in FIG. 2 , which is that of a divider with two modulos 4 and 5 , also implement cascaded flip-flops. However, unlike in the case of the model of FIG. 1 , the feedbacks are not achieved by logic gates but by a hard-wired “OR” circuit constructed by simple connections between outputs of flip-flops and the D input of the first flip-flop making it possible to obviate the propagation times of the signals in the logic gates. This last type of construction makes it possible to obtain higher operating frequencies than the constructions described previously but has the drawback of being limited in the number of achievable division ranks, and in the possible combinations.

Other characteristics and advantages of the invention will become apparent with the aid of the following description, given with regard to the appended drawings which represent:

FIGS. 1 and 2 two embodiments of variable-rank dividers according to the prior art.

FIG. 3 a schematic diagram of an embodiment of a variable-rank divider according to the invention (modulo 2 to 10 ).

FIG. 4 the truth table of a D type flip-flop involved in the implementation of the diagrams of FIGS. 1 , 2 , 3 , 7 A to 7 F.

FIG. 5 the timing diagram of the division of rank 5 implemented according to the diagram of FIG. 3 .

FIG. 6 a control table for the division ranks of the divider of FIG. 3 .

FIGS. 7A to 7 F simplified embodiments of dividers according to the invention making it possible to obtain division ranks which can vary by integers lying between 2 and n; n going from 2 to 7.

The divider according to the invention and which is represented in FIG. 3 , is more particularly adapted to embodiments in ECL technology where the outputs Q and {overscore (Q)} of the flip-flops take place via the emitters of the output transistors, but it may also be adapted to other technologies such as TTL technology, for example, to the detriment of the speed. It comprises a first chain of D type flip-flops respectively denoted 1 , 3 , 5 , 7 and 9 linked in cascade, the output Q of one being linked to the D input of the next. Closure of the chain is achieved by connecting the {overscore (Q)} output of the last flip-flop 9 to the D input of the first 1 . With each flip-flop 1 , 3 , 5 and 7 there is associated respectively a twin flip-flop denoted 2 , 4 , 6 and 8 , the flip-flops of each pair having their D inputs linked together.

The clock inputs C K of the flip-flops are linked together and to the input F e of the divider.

The {overscore (Q)} outputs of the flip-flops 2 , 4 , 6 , 8 and 9 are linked together to form a hard-wired “OR” circuit 10 . They are fed back to the D input of the flip-flops 1 and 2 . Within the framework of embodiments using TTL logic the {overscore (Q)} outputs must be linked to a logic “OR” gate with 5 inputs.

The output F s of the divider is constituted by the output Q of the flip-flop 1 .

The division ranks are controlled by inputs d 1 , d 2 , d 3 , d 4 and d 5 connected respectively to the “SET” inputs denoted S of the flip-flops 2 , 4 , 6 , 8 and 9 . The division rank obtained as a function of the controls d 1 to d 5 is determined according to the table represented in FIG. 6 .

To aid the understanding of the diagram every D flip-flop having its S input at 1 is disabled and can be ignored. The same holds true for the odd-numbered flip-flops, associated with the even-numbered flip-flops, counted starting from the last even flip-flop in the ascending order of their reference number which receives a 0 level on its D input, except for flip-flop 1 which must always be retained since it delivers the output signal, and flip-flops 7 and 9 when the S input of flip-flop 9 is at 0.

Thus in the case of division by 5, the flip-flops 2 , 8 and 9 can be ignored.

Flip-flops 5 and 7 are ignored since the control input d 3 is at zero. The ignored flip-flops are represented dashed in FIG. 3 .

The timing diagram for the division by 5 thus carried out is represented in FIG. 5 .

In accordance with the array of FIG. 4 , the output Q of each flip-flop takes the value of the D input at the moment the clock input C K switches from “0” (low state) to “1” (high state). In the explanation of the operation which follows it will be kept in mind that the flip-flops are synchronous, that is to say that they are controlled by one and the same clock signal F e arriving at the inputs C K .

Initially the outputs Q 1 , Q 3 , Q 4 and Q 6 of flip-flops 1 , 3 , 4 and 6 are at “0”

Q 1 applies a “0” state to inputs D 3 and D 4 of flip-flops 3 and 4

Q 3 applies a “0” state to input D 6 of flip-flop 6

The logical “OR” {overscore (Q)} 4 +{overscore (Q)} 6 applies a “1” state to the input D 1 of the first flip-flop 1

On the first rising edge of the clock signal F e :

Q 1 switches to “1”, implying D 3 and D 4 at “1”

Q 3 remains at “0” implying D 6 at “1”

Q 4 and Q 6 remain at “0”, {overscore (Q)} 4 +{overscore (Q)} 6 implying D 1 at “1”

On the second rising edge of the clock signal F e :

Q 1 remains at “1”, implying D 3 and D 4 at “1”

Q 3 and Q 4 switch to “1”, Q 3 implying D 6 at “1”

Q 6 remains at “0”, {overscore (Q)} 6 implying D 1 at “1”

On the third rising edge of the clock signal F e :

Q 1 remains at “1”, implying D 3 and D 4 at “1”

Q 3 and Q 4 remain at “1”, Q 3 implying D 6 at “1”

Q 6 switches to “1”, {overscore (Q)} 4 +{overscore (Q)} 6 implying D 1 at “0”

On the fourth rising edge of the clock signal F e :

Q 1 switches to “0”, implying D 3 and D 4 at “0”

Q 3 and Q 4 remain at “1”, Q 3 implying D 6 at “1”

Q 6 remains at “1”, {overscore (Q)} 4 +{overscore (Q)} 6 implying D 1 at “0”

On the fifth rising edge of the clock signal F e :

Q 1 remains at “0” implying D 3 and D 4 at “0”

Q 3 and Q 4 drop back to “0”, Q 3 implying D 6 at “0”, {overscore (Q)} 4 implying D 1 at “1”

Q 6 remains at “1”

On the sixth rising edge of the clock signal F e :

Q 1 rises back to “1”, implying D 3 and D 4 at “1”

Q 3 and Q 4 remain at “0”, Q 3 implying D 6 at “0”,

{overscore (Q)} 4 implying D 1 at “1”

Q 6 drops back to “0”, {overscore (Q)} 6 confirming D 1 at “1”

At this juncture the divider again has the same states as after the first rising edge of the clock signal F e and starts off again for a new identical division cycle.

The division rank of a divider according to the invention is not limited in theory.

In general, it is possible, by applying the principle of the invention, to construct any divider going from a rank equal to 2 up to a divider of any rank n>2.

If n is even the number of odd-numbered flip-flops of the first chain is equal to $$ n 2 ,

the number of even flip-flops of the second chain is equal to $$ n - 2 2

and the {overscore (Q)} outputs of the even flip-flops of the second chain as well as the last odd-numbered flip-flop of the first chain are connected together.

If n is odd the number of odd-numbered flip-flops of the first chain is equal to $$ n + 1 2 ,

the number of even flip-flops of the second chain is equal to $$ n - 3 2

and the {overscore (Q)} outputs of the even-numbered flip-flops of the second chain and of the last two odd-numbered flip-flops of the first chain are connected together.

Another possibility consists when n is odd, in using $$ n + 1 2

odd flip-flops in the first chain and $$ n - 1 2

even flip-flops in the second chain by linking together the {overscore (Q)} outputs of the even flip-flops and of the last odd-numbered flip-flop of the first chain.

This possibility uses one flip-flop more.

Diagrams of dividers according to the invention for division ranks lying between 2 and n, (n going from 2 to 7) together with their control array are represented in FIGS. 7A to 7 F.

Claims

1. Variable-modulo frequency divider of the type comprising a first chain of n greater than 3 D type flip-flops (1, 3, 5, 7, 9) linked in cascade, the output Q of one being linked to the input D of the next, and in which the complementary output {overscore (Q)} of the last flip-flop (9) is fed back to the D input of the first flip-flop (1) by way of an “OR” circuit, characterized in that it comprises a second chain of D type flip-flops (2, 4, 6, 8) comprising a determined number of flip-flops associated respectively with a flip-flop of the first chain (1, 3, 5, 7) the flip-flops of each pair thus formed (1, 2; 3, 4; 5, 6; 7, 8) having the D inputs linked together, in which the complementary outputs {overscore (Q)} of the flip-flops of the second chain (2, 4, 6, 8) as well as the output {overscore (Q)} of the last flip-flop of the first chain are linked by the “OR” circuit to the D input of the first flip-flop of the first chain and in which control links (d1, d2 . . . d5) are provided linking the control inputs S for disabling the D flip-flops (2, 4, 6, 8) of the second chain and of the last D flip-flop (9) of the first chain so as to programme the modulo of the divider.

2. Divider according to claim 1, characterized in that it comprises, for carrying out a division modulo 2 to n even, n2flip-flops in the first chain and n-22flip-flops in the second chain, the complementary output {overscore (Q)} of the last flip-flop of the first chain and the complementary outputs Q of the flip-flops of the second chain are linked to the D input of the first flip-flops of the even and odd chains by way of the “OR” circuit.

3. Divider according to claim 1, characterized in that it comprises, for carrying a division modulo 2 to n odd, n+12flip-flops in the first chain and n-32flip-flops of the second chain, the complementary outputs {overscore (Q)} of the last two flip-flops of the first chain being linked to the outputs {overscore (Q)} of the flip-flops of the second chain to the D input of the first flip-flops of the even and odd chains by way of the “OR” circuit.

4. Divider according to claim 1, characterized in that it comprises, for carrying out a division modulo 2 to n odd, n+12odd flip-flops in the first chain and n-12even flip-flops of the second chain, by linking together the outputs {overscore (Q)} of the even flip-flops and of the last odd-numbered flip-flop {overscore (Q)} of the first chain by way of the “OR” circuit.

5. Divider according to claim 1 for carrying out a division modulo m to n, m<n, n being as large as desired, characterized by a number of flip-flops which in the truth chart of the divider have their disable inputs S always at zero or altering according to the “0” or “1” state, excluding the flip-flops which have their disable input S always 1.