Claims
- 1. A dividing circuit comprising:
a first group of bistable devices, each device being configured to produce a first output signal in response to a received master clock signal; and a plurality of circuit stages, each stage including at least one bistable device from a second group of bistable devices and being coupled, at least indirectly, to one or more output ports of the devices of the first group, the plurality of stages being configured to produce a second output signal; wherein each stage is configured to receive as an input a respective slaved clock signal, each respective slaved clock signal having characteristics different from characteristics of the master clock signal; and wherein the second output signal has a frequency substantially equal to a frequency of the master clock signal divided by a non-integer factor.
- 2. The dividing circuit of claim 1, wherein the characteristics include phase.
- 3. The dividing circuit of claim 2, further comprising a logic gate; wherein the logic gate and the first group of bistable devices form a synchronous counter.
- 4. The dividing circuit of claim 3, wherein the synchronous counter is a Johnson counter.
- 5. The dividing circuit of claim 1, wherein the bistable devices are flip-flops.
- 6. The dividing circuit of claim 5, wherein the master output signal is successively provided as an input to each of the flip-flops.
- 7. The dividing circuit of claim 1, further comprising a multi-phase voltage control oscillator configured to generate all of the clock signals.
- 8. The dividing circuit of claim 7, wherein the multi-phase voltage control oscillator generates the first output signal and each of the respective slaved clock signals;
wherein the master clock signal and each of the respective slaved clock signals are derived from multi-phase clock signal; and wherein the master clock signal and each of the respective slaved clock signals are shifted in phase relative to one another.
- 9. A dividing circuit comprising:
a first circuit portion including a synchronous counter configured to receive a first clock signal as an input and produce an output signal in response thereto; and at least a second circuit portion including a plurality of circuit stages, each stage being configured to receive a respective clock signal, each respective clock signal having characteristics different from the first clock signal, the second circuit portion (i) being electrically connected to the first circuit portion, (ii) being configured to receive the output signal therefrom, and (iii) produce an output clock signal having a frequency numerically related to a frequency of the first clock signal.
- 10. The circuit of claim 9, wherein each of the plurality of circuit stages includes one or more bistable devices.
- 11. The circuit of claim 9, wherein the first clock signal is a master clock signal;
wherein the respective clock signals are slave clock signals; and wherein the numerically related frequency is equal to a frequency of the master clock signal divided by a non-integer factor.
- 12. A method to generate a frequency divided output clock signal comprising:
receiving a first clock signal; shifting a phase of the first clock signal to produce a plurality of phase shifted clock signals; and producing a frequency divided output clock signal based upon the first clock signal and the plurality of phase shifted clock signals.
- 13. The method of claim 12, wherein the frequency divided output clock signal has a frequency equal to a frequency of the master clock signal divided by a non-integer factor.
- 14. A dividing circuit comprising:
means for producing a first output signal in response to a received master clock signal; and means for producing a second output signal coupled to the means for producing a first output signal; wherein the means for producing a second output signal is configured to receive as an input one or more slaved clock signals, each having characteristics different from characteristics of the master clock signal; and wherein the means for producing a second output signal is configured to produce a second output signal having a frequency substantially equal to a frequency of the master clock signal divided by a non-integer factor.
- 15. An apparatus for generating a frequency divided output clock signal comprising:
means for receiving a first clock signal; means for shifting a phase of the first clock signal to produce a plurality of phase shifted clock signals; and means for producing a frequency divided output clock signal based upon the first clock signal and the plurality of phase shifted clock signals.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of the U.S. Non-Provisional Application entitled “Frequency Dividing Circuit,” Ser. No. 09/982,844, filed Oct. 22, 2001, which claims the benefit of U.S. Provisional Application No. 60/248,425, filed Nov. 14, 2000, all of which are incorporated herein in their entireties by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60248425 |
Nov 2000 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09982844 |
Oct 2001 |
US |
Child |
10307308 |
Dec 2002 |
US |