BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic circuit providing frequency-doubling function in prior art.
FIG. 2 is a schematic circuit comprising dual Gilbert mixer blocks and RC (resistor-capacitor) load according to one preferred embodiment of this invention.
FIG. 3 is a schematic circuit demonstrating a Gilbert mixer comprising CMOS transistors and a current source according to one preferred embodiment of this invention.
FIG. 4 is a schematic circuit demonstrating a Gilbert mixer comprising CMOS transistors (without tail current source, as opposed to FIG. 3) according to one preferred embodiment of this invention.
FIG. 5 is a diagram of the input and output waveforms of the frequency doubler according to one preferred embodiment of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In realizing a direct conversion transceiver, a frequency doubler is a key component to avoid interference between Power Amplifier (PA) and Voltage Controlled Oscillator (VCO). A transceiver circuit including a frequency doubler is briefly shown in FIG. 1. Referring to FIG. 1, a frequency doubler circuit 100 is illustrated herein. The input signal is fed into Low Noise Amplifier (LNA) 101, and is mixed with a doubled oscillating frequency at mixer 102. The oscillating frequency is generated at a VCO oscillator 103 and is doubled at a frequency doubler 104 so as to implement mixing scheme. However, the input impedance of the conventional frequency doubler is not designed to be balanced, thus poor sinusoidal output waveforms are generated so that are not being symmetrical for further usage.
The concept of tuning the waveforms in this present invention is to balance out input impedance of the internal circuit of the frequency doubler, as well as to choose output load carefully in order to obtain the symmetry of output waveforms. The first scheme provided by this present invention is to use dual identical circuit in the frequency doubler, i.e. to use two identical Gilbert mixers, as shown in FIG. 2. Referring to FIG. 2, the frequency doubler circuit 200 comprises dual Gilbert mixer 300 and output load consisting capacitors 211 and 212, and inductors 221 and 222. Considering input signals firstly, a LO frequency (INP) and its inverse (INN), and a 90° shifted frequency (QNP), i.e. by quadrature, and its inverse (QNN), are provided for the frequency doubler circuit in this preferred embodiment. Further considering connections of the elements in this circuit. A block of the Gilbert mixer 300 in this present invention comprises six input terminals and two output terminals, which are IN0, IN1, . . . , IN5 and OUT0 to OUT1. Notice that IN0 and IN1 are connected in a pair, and IN2 and IN3 are connected in a pair for this application in this preferred embodiment. It is obvious that the two Gilbert mixers and the two loads in this embodied circuit are symmetrically constructed, thus the connection scheme shown in FIG. 2 is not the only topology. In the exemplary connection in this preferred embodiment, input signal INP feeds IN0 and IN1 of the first Gilbert mixer and IN4 of the second Gilbert mixer, while input signal INN feeds the IN2 and IN3 of the first Gilbert mixer and IN5 of the second Gilbert mixer. Meanwhile, QNP feeds IN5 of the first Gilbert mixer and IN2 and IN3 of the second Gilbert mixer, as well as QNN feeds IN4 of the first Gilbert mixer and IN0 and IN1 of the second Gilbert mixer. The first output terminal OUT0 of each Gilbert mixer is connected to the second terminals of capacitor 211 and inductor 221, while the second output terminal OUT1 of each Gilbert mixer is connected to the second terminal of capacitor 212 and inductor 222. These output terminals are then marked OUTP and OUTN of the frequency doubler circuit in FIG. 2. Notice that each of the first and second loads is implemented in parallel capacitor-inductor arrangement in this preferred embodiment, as well as implemented with at least one of resistor, capacitor and inductor.
Referring to FIG. 3 for understanding internal construction of the Gilbert mixer 300 in FIG. 2, six NMOS transistors 330 to 335 and a current source 341 build the circuit therein. The gates of the transistors 330 to 335 correspond to the input terminals IN0 to IN5 in block diagram in FIG. 2, whereas OUT0 and OUT1 are actually coupled to the drains of transistors 330, 333 and the drains of transistors 331, 332 respectively. For the remaining connections, the sources of transistors 330 and 332 are coupled to the drain of transistor 334, while the sources of transistors 331 and 333 are coupled to the drain of transistor 335. Lastly, the positive terminal of current source 341 couples to the sources of transistor 334 and 335, and its negative terminal couples to VSS. Notice that providing the transistor sizes are carefully chosen, the input impedance seen from the top level of the frequency doubler is balanced out for each of the input terminals.
Referring to FIG. 4, another preferred embodiment of the internal construction of the Gilbert mixer is illustrated as 400 in replace with 300, where six NMOS transistors 430 to 435 build the circuit therein. The gates of the transistors 430 to 435 correspond to the input terminals IN0 to IN5 in bock diagram in FIG. 2, whereas OUT0 and OUT1 are actually coupled to the drains of transistors 430, 433 and the drains of transistors 431, 432 respectively. For the remaining connections, the sources of transistors 430 and 432 are coupled to the drain of transistor 434, while the sources of transistors 431 and 433 are coupled to the drain of transistor 435. Lastly, the positive terminal of current source 441 couples to the sources of transistor 434 and 435, and its negative terminal couples to VSS. Notice that providing the transistor sizes are carefully chosen, the input impedance seen from the top level of the frequency doubler is balanced out for each of the input terminals.
Referring to FIG. 5, the input and output waveforms are shown in the diagram. As demonstrated, INP, INN are in inverse-phase manner, QNP and QNN are in inverse-phase manner, QNP and INP are differed by 90° in phase, that is in quadrature-phase. As a result, OUTP and OUTN are the output waveforms in inverse-phase to each other thus demonstrate doubling frequency. Notice that symmetrical waveforms are obtained as designed.
Ultimately, NMOS transistors and CMOS semiconductor technology are applied in this preferred embodiment in the present invention in order to achieve small size and to lower power consumption. Yet other available semiconductor technologies also apply, BiCMOS technology for example, as long as the spirit and scope of this present invention are satisfied.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080068052
