FREQUENCY MODULATED OUTPUT CLOCK FROM A DIGITAL FREQUENCY/PHASE LOCKED LOOP

Abstract

A frequency modulated output of a Digital Locked Loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

This invention is described in a preferred embodiment in the following description with reference to the drawings, in which like numbers represent the same or similar elements, as follows:

FIG. 1 is a block diagram of a typical PLL of the prior art using frequency modulation on its output to reduce the circuit's generation of EMI.

FIG. 2 shows a frequency-modulated digital locked loop, in accordance with a preferred embodiment of the present invention.

FIG. 3 shows a block diagram of a Johnson Counter generating the FM control word for driving the FM DAC, in accordance with a preferred embodiment of the present invention.

FIG. 4 shows a representative timing diagram of a frequency-modulated digital locked loop, in accordance with a preferred embodiment of the present invention.

Claims

1. An apparatus comprising: a counter having an input for receiving a reference clock signal, a first output for providing a sample clock signal, and a second output;a frequency measurement device having a first input coupled to the sample clock, a second input coupled to a feedback signal, and an output for providing a digital error signal indicating a difference between the ratio of the reference and actual feedback clocks;a digital device having a first input coupled to the sample clock signal, a second input coupled to a digital error signal, and an output for providing a filtered digital error signal;a summing device having a first input coupled to the filtered error signal, a second input and an output for providing an oscillator control signal resulting from a combination of the filtered error signal and the second input; andan oscillator having an input coupled the frequency control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal.

2. The apparatus of claim 1, wherein the apparatus is a digital frequency locked loop further comprising, the second output of the counter having a multi-bit representation of a frequency modulation control signal value is coupled to the second input to the summing device.

3. The apparatus of claim 1, wherein the apparatus is a digital phase locked loop further comprising, a phase detector device having a first input coupled to a reference clock signal, a second input coupled to a feedback signal from the timing output, and an output representing the phase difference between the two signals that is coupled to the second input of the summing device for the purpose of coupling a phase correction signal to the oscillator.

4. The apparatus of claim 1, wherein the digital device is a digital loop filter.

5. The apparatus of claim 1, wherein the counter is a Johnson Counter.

6. The apparatus of claim 1, wherein the counter generates a plurality of digital bit output signals on one or more digital bit output signal lines, the counter including a plurality of flip-flops cascaded together, each output of the plurality of flip-flops coupled to the one or more digital bit output signal lines to provide frequency conversion of the reference clock signal to the frequency modulation signal having a desired frequency relative to the reference clock signal.

7. The apparatus of claim 4, wherein each of the one or more digital bit output signal lines is received at an equally weighted input of a digital-to-analog converter.

8. The apparatus of claim 1, further comprising a digital-to-analog converter receiving the output of the digital device to generate an analog form of the error signal at its output.

9. The apparatus of claim 1, further comprising output signals on one or more digital bit output signal lines, the counter including a plurality of flip-flops cascaded together, each output of the plurality of flip-flops coupled to the one or more digital bit output signal lines to provide frequency conversion of the reference clock signal to the frequency modulation signal having a desired frequency relative to the reference clock signal.

10. A method for generating an oscillation signal of a digital locked loop, the method comprising the steps of: converting a reference clock signal to generate a divided sample clock signal at a first output of a counter;converting a reference clock signal to generate a divided frequency modulation signal at a second output of a counter, wherein the frequency modulated signal is synchronized with the sample clock signal;generating an error signal indicative of a frequency relationship between a reference clock signal and a feedback signal;filtering the frequency error signal to produce a control signal;deriving the feedback signal from the oscillation signal;combining the control signal with a second signal to control an oscillation signal.

11. The method of claim 10, further comprising, coupling the second output of the counter having a multi-bit representation of a frequency modulation control signal value to the second input to the summing device.

12. The apparatus of claim 1, wherein the apparatus is a digital phase locked loop further comprising, coupling a phase detector device having a first input to a reference clock signal, a second input coupled to a feedback signal from the timing output, and an output representing the phase difference between the two signals to the second input of the adder thereby coupling a phase correction signal to the oscillator.

13. The method of claim 10, wherein the step of combining includes frequency modulating the control signal with the frequency modulated signal.

14. The method of claim 10, further comprising the steps of: generating a plurality of sample signals;generating intermediate count signals from a counter between generating the plurality of sample signals; andgenerating the frequency modulated signal from the intermediate count signals.

15. The method of claim 10, wherein the step of filtering is performed by a digital filter.

16. The method of claim 10, wherein the step of converting is performed by a Johnson Counter.

17. The method of claim 10, wherein the digital locked loop is a digital frequency locked loop.

18. A method for generating an oscillation signal of a digital locked loop, the method comprising the steps of: converting a reference clock signal to generate a divided sample clock signal at a first output of a counter;generating an error signal of a phase relationship between a reference clock signal and a feedback signal;converting the error signal to produce a control signal;combining the control signal with the phase error control signal to generate an oscillation control signal;deriving the feedback signal from the oscillation signal.

19. The method of claim 18, wherein the step of combining includes phase modulating the control signal with the phase error control signal.

20. The method of claim 18, further comprising the step of: generating a plurality of sample signals.

21. The method of claim 18, wherein the step of converting is performed by a Johnson Counter.

22. The method of claim 18, wherein the digital locked loop is a digital phase locked loop.