The present invention relates to a frequency regeneration circuit and a frequency regeneration method used in a high-speed serial communication.
Information on the frequency of data being inputted is important in order to receive signals accurately in a receiving circuit for a high-speed serial communication. A related system is provided with a quartz oscillator for supplying information on the frequency to a receiving side. According to an increase of a communication rate, however, an oscillation frequency and an accuracy of the oscillation frequency required in a quartz oscillator increases. As a result, there is a problem that quartz oscillators that meet those requirements are very expensive. In order to solve such a problem, technology of regenerating a frequency within a receiving circuit has attracted much attention.
The following technologies are disclosed as related frequency regeneration technologies: ICCE 1998 Digest of Technical Paper (H. Kikuchi et al., “Gigabit Video Interface: A Fully Serialized Data Transmission System for Digital Moving Pictures,” Consumer Electronics, 1998. ICCE. 1998 Digest of Technical Papers. International Conference on, 1998, pp. 30-32.) (Non-Patent Literature 1) uses a technique of amplifying serial data into an internal digital signal amplitude with use of an analog amplifier circuit and then performing a phase-frequency comparison between an internal clock signal and the amplified serial data with use of a phase-frequency comparator circuit, which is generally used in a PLL (Phase Locked Loop) circuit. Furthermore, IEEE JSSC 2003 (A. Pottbacker, U. Langmann, and H. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” Solid-State Circuits, IEEE Journal of, vol. 27, 1992, pp. 1747-1751.) (Non-Patent Literature 2) uses a technique of oversampling serial data to obtain a plurality of data pulses and performing an asynchronous operation on those data pulses so as to extract frequency information.
However, the technique of Non-Patent Literature 1 requires signal amplification of serial data and thus suffers from a problem that much electric power is consumed in the analog amplifier circuit. Furthermore, the technique of Non-Patent Literature 2 requires an asynchronous design for the operation of the data pulses and thus suffers from a problem that it has difficulty in design.
An exemplary object of the present invention is to provide a frequency regeneration circuit that regenerates a frequency that is 1/n of a rate of serial data (where n is a natural number) without an analog amplifier circuit for amplifying the serial data and without the need for asynchronous circuit design.
According to one aspect of the present invention, there is provided a frequency regeneration circuit that compares a width of a single pulse of input data with a time width of a 1/n clock cycle defined by a phase difference of multi-phase clock signals (where n is a natural number) in order to regenerate a frequency that is 1/n of a rate of the input data.
Furthermore, according to another aspect of the present invention, there is provided a frequency regeneration circuit including: a judgment circuit operable to sample input data with multi-phase clock signals to obtain judgment results; an exclusive-OR circuit operable to compare judgment results that have been sampled with clock signals having adjacent phase differences to each other for thereby outputting phase comparison results; a frequency comparison logic operable to output frequency comparison results in which a logical operation has been performed on the phase comparison results; a charge pump circuit operable to output a control voltage, the frequency comparison results being inputted to the charge pump circuit; and a voltage controlled oscillator controlled by the control voltage so as to output multi-phase clock signals having a frequency that is 1/n of a rate of the input data (where n is a natural number).
Moreover, according to still another aspect of the present invention, there is provided a frequency regeneration method of converting input data into judgment results that have been sampled with multi-phase clock signals each having a certain phase difference; obtaining phase comparison results by an exclusive-OR operation on the judgment results that have been sampled with clock signals having adjacent phase differences; outputting frequency comparison results obtained by performing a logical operation on the phase comparison results; and outputting multi-phase clock signals controlled by the frequency comparison results, the multi-phase clock signals having a frequency that is 1/n of a rate of the input data (where n is a natural number).
According to the present invention, a width of a single pulse of input data is compared with a time width of a 1/n clock cycle defined by a phase difference of multi-phase clock signals (where n is a natural number), so that a clock signal having a frequency that is 1/n of a rate of the input data can be obtained. The present invention is advantageous in that a frequency that is 1/n of a rate of the input data can be regenerated without an analog amplifier circuit for amplifying a waveform of the input data and without the need for asynchronous circuit design.
Embodiments of the present invention will be described below with reference to the drawings.
(First Embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
The frequency regeneration circuit illustrated in
Two judgment results 105 sampled with clock signals having adjacent phases are inputted to each of exclusive-OR circuits, which outputs a phase comparison result 106 to the frequency comparison logic 107. For example, judgment results 105 of adjacent phases are inputted to the exclusive-OR (XOR) circuits in the order of d0 and d1, d1 and d2, . . . , d9 and d0. The exclusive-OR circuits output ten phase comparison results 106 of dn0, up1, . . . , up9. As shown in
The frequency comparison logic 107 performs a logical operation therein with use of the inputted phase comparison results 106 to thereby generate and output frequency comparison results 108. The phase comparison results 106 are inputted to AND circuits, which output frequency comparison results 108 that are synchronized with the clock signals. The frequency comparison logic 107 outputs five pairs of frequency comparison results 108 (fdn0 and fup0), (fdn1 and fup1), . . . , (fdn4 and fup4), which have been generated with the clock signals clk0 and clk1, clk2 and clk3, . . . , clk8 and clk9. The five pairs of frequency comparison results 108 are respectively inputted to the charge pumps 109, which control an oscillation frequency of the VCO 110. The VCO 110 outputs 10-phase clock signals 102 (c1k0-clk9) of 400 MHz that have equal phase differences.
Here, dn* of the phase comparison results 106 and fdn* of the frequency comparison results 108 are down-signals, which slow down the clock signal, whereas up* of the phase comparison results 106 and fup* of the frequency comparison results 108 are up-signals, which accelerate the clock signal. Those definitions differ depending upon what phase of the 10-phase clock signals is used as a reference. According to the present invention, as shown in
Here, the phase comparison results 106 are control signals for synchronizing the rising timing of the clock signals clk0, clk2, clk4, clk6, and clk8 of the 10-phase clock signals 102 with the transition timing of the serial data. The phase comparison results 106 are obtained from an exclusive-OR operation of judgment results of the serial data obtained at the rising timing of adjacent two clock signals of the 10-phase clock signals. Therefore, as shown in
fdn0=dn0*˜up1*˜dn2*up3 (Formula 1)
fup0=up1*dn2 (Formula 2)
fdn1=dn2*˜up3*˜dn4*up5 (Formula 3)
fup1=up3*dn4 (Formula 4)
fdn2=dn4*˜up5*˜dn6*up7 (Formula 5)
fup2=up5*dn6 (Formula 6)
fdn3=dn6*˜up7*˜dn8* up9 (Formula 7)
fup3=up7*dn8 (Formula 8)
fdn4=dn8*˜up9*˜dn0*up1 (Formula 9)
fup4=up9*dn0 (Formula 10)
The frequency regeneration circuit of this embodiment oversamples the serial data (2 Gb/s) twice with the 10-phase clock signals for thereby regenerating a clock signal having a frequency corresponding to ⅕ of the frequency of the serial data. The serial data are first sampled by the judgment circuits provided within the phase comparator circuit, which operate with the 10-phase clock signals. Thus, the serial data are converted into judgment results as digital data. Phase comparison results generated from the judgment results are inputted to the frequency comparison logic. The frequency comparison logic performs a logical operation therein with use of the phase comparison results to thereby generate and output frequency comparison results. The charge pumps control the oscillation frequency of the VCO with use of the frequency comparison results. Thus, the frequency of the clock signal can be regenerated.
As described above, the width of a single pulse of the serial data is compared with the time width defined by a phase difference of multiphase clock signals. The frequency comparison logic calibrates the phase comparison results with the data transition interval having a width of a single pulse of the serial data to thereby obtain frequency comparison results. In order to regenerate a clock frequency that is 1/n of a rate of the serial data (where n is a natural number; and n=5 in the present embodiment), a frequency comparison result fdn for lowering the frequency is generated when the clock signal has a frequency higher than the 1/n clock frequency. A frequency comparison result fup for increasing the frequency is generated when the clock signal has a frequency lower than the 1/n clock frequency. The oscillation frequency of the VCO is controlled with use of the frequency comparison results so as to regenerate a frequency that is 1/n of the frequency of the clock signal.
(Second Embodiment)
A second embodiment of the present invention will be described with reference to the drawings.
The present embodiment is provided with a phase control that is implemented with phase comparison results 408 outputted from the phase comparator circuit 404, in addition to a frequency control that is implemented with the phase comparator circuits 404 and 405 and the frequency comparison logic 406. A phase comparison control is performed when an oscillation frequency of the VCO 409 is brought sufficiently close to 400 MHz by a frequency control using the frequency comparison results 407. Thus, the data input 401 and the 10-phase clock signals 402 are synchronized in phase with each other.
The serial data 401 of 2.0 Gb/s are sampled at the phase comparator circuit 405 with the 10-phase clock signals 403 (clk1, clk3, . . . , clk19) and converted into judgment results (d1, d3, . . . , d19). Two judgment results sampled with adjacent phases of the 10-phase clock signals 403 (clk1-c1k19) are inputted to each of exclusive-OR circuits, which outputs a phase comparison result 410 to the frequency comparison logic 406. The judgment results sampled with adjacent phases (d1 and d3, d5 and d7, . . . , d17 and d19) are inputted to the exclusive-OR circuits of the phase comparator circuit 405. Each of the exclusive-OR circuits outputs a phase comparison result.
Similarly, the phase comparator circuit 404 samples the serial data 401 being inputted with the 10-phase clock signals 402 (clk0, clk2, . . . , clk18) and converts them into judgment results (d0, d2, . . . , d18). Two judgment results sampled with adjacent phases of the 10-phase clock signals 403 (c1k0-clk18) are inputted to each of exclusive-OR circuits, which outputs a phase comparison result 410 to the frequency comparison logic 406. The judgment results sampled with adjacent phases (d0 and d2, d2 and d4, . . . , d18 and d0) are inputted to the exclusive-OR circuits of the phase comparator circuit 404. Each of the exclusive-OR circuits outputs a phase comparison result.
The frequency comparison logic 406 performs a logical operation therein with use of the inputted phase comparison results 408 and 410 to thereby generate and output frequency comparison results 407. The frequency comparison logic 406 outputs five pairs of frequency comparison results 407 (fdn0 and fup0), (fdn1 and fup1), . . . , (fdn4 and fup4), which are synchronized with the clock signal. Charge pumps, to which those five pairs of frequency comparison results 407 are inputted, control an oscillation frequency of the VCO 409. A frequency control is interrupted when an oscillation frequency of the VCO 409 is brought sufficiently close to 400 MHz by a frequency control using the frequency comparison results 407. In this case, the charge pumps are controlled with use of the phase comparison results 408 outputted from the phase comparator circuit 404. Thus, a phase comparison control of the VCO 409 is performed, and the data input 401 and the 10-phase clock signals 402 are synchronized in phase with each other.
In the second embodiment of the present invention, as with the first embodiment, whether or not a single pulse of the serial data 401 make a transition in a specific interval is detected based upon the phase comparison results 408 and 410 in order to generate frequency comparison results 407.
fdn0=dn0*˜up2*˜dn4*dn5 (Formula 11)
fup0=up2*dn5*˜up6 (Formula 12)
fdn1=dn4*˜up6*˜dn8*dn9 (Formula 13)
fup1=up6*dn9*˜up10 (Formula 14)
fdn2=dn8*˜up10*˜dn12*dn13 (Formula 15)
fup2=up10*dn13*˜up14 (Formula 16)
fdn2=dn12*˜up14*˜dn16*dn17 (Formula 17)
fup2=up14*dn17*˜up18 (Formula 18)
fdn2=dn16*˜up18*˜dn0*dn1 (Formula 19)
fup2=up18*dn1*˜up2 (Formula 20)
In the present embodiment, serial data of 2.0 Gb/s are oversampled four times with 20-phase clock signals including two lines of 10-phase clock signals. Thus, frequency comparison results are obtained for a clock frequency of 400 MHz. Phase comparison results are generated from judgment results in which the serial data have been sampled with the corresponding 10-phase clock signals by using two phase comparator circuits. The frequency comparison logic generates frequency comparison results from the phase comparison results and controls an oscillation frequency of the VCO. In addition to such a frequency control, a phase comparison control is performed when an oscillation frequency of the VCO is brought sufficiently close to 400 MHz. Thus, the serial data input and the 10-phase clock signals can be synchronized in phase with each other.
(Third Embodiment)
A third embodiment of the present invention will be described with reference to the drawings.
The phase comparator circuit 1102 samples serial data 1101 of 2.0 Gb/s with the 10-phase clock signals (clk1, clk3, . . . , clk19) among the 20-phase clock signals to thereby obtain judgment results. Phase comparison results (dn1, up3, dn5, . . . , up19) are outputted to the frequency comparison logic 1104 with use of judgment results that have been sampled with adjacent phases. The phase comparator circuit 1103 samples the serial data 1101 of 2.0 Gb/s with the 10-phase clock signals (clk0, clk2, . . . , clk18) and outputs phase comparison results (dn0, up2, dn4, . . . , up18) to the frequency comparison logic 1104 with use of signals that have been sampled with adjacent phases.
The frequency comparison logic 1104 generates frequency comparison results based upon the phase comparison results inputted from the phase comparator circuits 1102 and 1103. For example, the phase comparison results dn0 and up18 are inputted to an OR circuit. An output from the OR circuit, the phase comparison result dn5, the negative of the phase comparison result up2, and the negative of the phase comparison result dn4 are inputted to an AND circuit, which outputs a frequency comparison result fdn0′ that is synchronized with the clock signal clk3. Furthermore, the phase comparison results dn5 and up2 and the negative of the phase comparison result up6 are inputted to an AND circuit, and the phase comparison results dn5 and up3 and the negative of the phase comparison result up6 are inputted to an AND circuit. Outputs of those AND circuits (fup0a, fup0b) are inputted to an OR circuit, which outputs a frequency comparison result fup0′ that is synchronized with the clock signal clk5. Transition detection intervals for generating those frequency comparison results are illustrated in
The frequency regeneration circuit of the present embodiment shown in
Meanwhile,
In the frequency regeneration circuit according to the third embodiment, detection intervals are added to the detection intervals used in the second embodiment. Thus, a frequency comparison can be made at a frequency of 200 MHz or less. The frequency comparison logic of
In the present embodiment, serial data of 2.0 Gb/s are oversampled with 20-phase clock signals including two lines of 10-phase clock signals. Thus, frequency comparison results are obtained for a clock frequency of 400 MHz. Phase comparison results are generated from judgment results in which serial data have been sampled with the corresponding 10-phase clock signals by using two phase comparator circuits. The logical configuration of the frequency comparison logic is changed and added to widen the transition detection intervals. Thus, a correct frequency comparison result is outputted from a wide frequency region, and an oscillation frequency of the VCO can be controlled.
A frequency regeneration circuit according to the present invention oversamples serial data with multi-phase clock signals for thereby generating a clock signal corresponding to 1/n of a frequency of the serial data (where n is a natural number). The serial data are first sampled by a judgment circuit provided within a phase comparator circuit, which is operable with multi-phase clock signals, and converted into judgment results as digital data. Phase comparison results generated from the judgment results are inputted to a frequency comparison logic. The frequency comparison logic performs a logical operation so that the phase comparison results are calibrated with data transition intervals having a width of a single pulse of the serial data. Thus, frequency comparison results are generated. With use of those frequency comparison results, charge pumps can control an oscillation frequency of the VCO and regenerate a frequency of the clock signal.
In a frequency regeneration circuit according to the present invention, the width of a single pulse of serial data being inputted can be compared with a phase difference of multi-phase clock signals by detecting consecutive transitions of the input data in two different periods of time defined by the multi-phase clock signals. The detection of transitions can be made by performing a logical operation on judgment results obtained from a judgment circuit that operates upon rising edges of the multi-phase clock signals.
Furthermore, the judgment with the multi-phase clock signals to detect a transition is made at a rate that is at least twice a rate of the input data. When the judgment with the multi-phase clock signals is made at a rate that is four times a rate of the input data, detection of a frequency difference can be interrupted in a state in which the multi-phase clock signals are synchronized in phase with the input data. Additionally, a transition with the multi-phase clock signals is detected with use of phase comparison results obtained from judgment results of the multi-phase clock signals by exclusive-OR circuits. A logical operation of the phase comparison results can be performed with a synchronization circuit using the clock signal.
According to the present invention, there can be provided a frequency regeneration circuit that can regenerate a clock signal by comparing a width of a single pulse of input data with a time width of a clock cycle defined by a phase difference of multi-phase clock signals and by performing a logical operation. Thus, there can be provided a frequency regeneration circuit that can regenerate a frequency that is 1/n of input data (where n is a natural number) with use of judgment results obtained from judgment of the input data and a synchronization circuit without an analog amplifier circuit for amplifying the serial data.
While the invention has been particularly shown and described with reference to exemplary embodiments thereof, the invention is not limited to these embodiments. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the claims.
Description of Reference Numerals
101, 401, 1101 serial data
102, 402, 403 10-phase clock signal
103, 404, 405, 1102, 1103 phase comparator circuit
104 judgment circuit
105 judgment result
106, 408, 410 phase comparison result
107, 406, 1104 frequency comparison logic
108, 407 frequency comparison result
109 charge pump
110, 409 VCO
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2009/064095 | 8/4/2009 | WO | 00 | 2/3/2012 |