Claims
- 1. A voltage regulator for a memory device comprising:means for generating a clock pulse signal based on a system clock signal; means for delaying said clock pulse signal; means for determining a control signal based on said clock pulse signal and a delay time of said delaying means; and means for turning on and off a supply voltage in response to said control signal to regulate said voltage.
- 2. A voltage regulator as defined in claim 1 wherein said means for delaying said clock pulse signal includes a delay chain having a plurality of inverters operatively connected in series with one another and a reset input adapted to receive said clock pulse signal.
- 3. A voltage regulator as defined in claim 1 wherein said means for turning on and off said supply voltage comprises a transistor operatively connected between a source of electrical supply and an electrical load.
- 4. A voltage supply circuit comprising:a control circuit adapted to output a first gate control voltage; a delay circuit adapted to receive a periodic pulse signal and controllably output a second gate control voltage; a first transistor having a first gate operatively connected to said control circuit and adapted to receive said first gate control voltage; a second transistor having a second gate operatively connected to said delay circuit and adapted to receive said second gate control voltage, said first and second transistors operatively connected in series between a source of constant potential voltage and an electrical load, wherein said delay circuit exhibits a characteristic signal delay and wherein said delay circuit is adapted to output said second gate voltage when said characteristic signal delay has a duration shorter than a pulse length of said periodic pulse signal.
- 5. A voltage supply circuit as defined in claim 4, wherein said first gate control voltage is substantially constant over time.
- 6. A voltage supply circuit as defined in claim 4, wherein said first transistor is an NMOS transistor and said second transistor is a PMOS transistor.
- 7. A voltage supply circuit as defined in claim 4, wherein said electrical load comprises a portion of a memory integrated circuit.
- 8. A voltage supply circuit as defined in claim 4, wherein said second transistor enters a non-conductive state when said second gate voltage control is output.
- 9. A method of regulating an electrical voltage applied to an electrical load comprising:comparing a duration of a clock pulse to a time delay of a delay circuit; and turning off a transistor operatively connected between a source of electrical supply and an electrical load during a time when said duration has exceeded said time delay, whereby said electrical voltage is regulated across said electrical load.
- 10. A voltage control signal adapted to control a voltage regulator circuit, said signal comprising:a first state and a second state, said signal exhibiting said first state during a first time when a duration of a clock pulse has not exceeded a delay duration of a delay circuit, said signal exhibiting said second state during a second time when a duration of said clock pulse has exceeded said delay duration of said delay circuit, said signal adapted to control a transistor operatively connected between a voltage supply and a load, whereby a voltage across said load is regulated.
- 11. A voltage control signal as defined in claim 10, wherein said first state comprises a first potential voltage, and said second state comprises a second potential voltage.
Parent Case Info
This application is a continuation of U.S. patent application Ser. No. 09/692,472, filed Oct. 20, 2000, which is a continuation of U.S. patent application Ser. No. 09/386,312 filed Aug. 31, 1999 (issued as U.S. Pat. No. 6,175,221 on Jan. 16, 2001), the entirety of each of which is incorporated herein by reference.
US Referenced Citations (14)
Continuations (2)
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Number |
Date |
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09/692472 |
Oct 2000 |
US |
Child |
09/947522 |
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US |
Parent |
09/386312 |
Aug 1999 |
US |
Child |
09/692472 |
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US |