Patent Application
20250218371
This application claims the benefit of the Korean Patent Application No. 10-2023-0197157 filed on Dec. 29, 2023, which is hereby incorporated by reference as if fully set forth herein.
The present disclosure relates to a frequency variable display apparatus and a flicker compensation method thereof.
Frequency variable display apparatuses vary a frame frequency of an image displayed on a screen, based on an attribute of video data received from an external video source. Frequency variable display apparatuses support a variable refresh rate (VRR) function which varies a frame frequency within a predetermined frequency range.
When a frame frequency is rapidly changed from a low-speed frame to a high-speed frame or to be opposite thereto by a VRR operation, a flicker phenomenon caused by a recognition luminance deviation may be recognized by a user. To decrease the recognition luminance deviation, luminance algorithm technology which adjusts a data gain with a frame frequency has been known.
However, in a VRR mode, frequency information about a current frame may not be known until the current frame ends. Therefore, conventional luminance algorithm technology determines a data gain of a current frame, based on frequency information about a previous frame.
The present disclosure may provide a frequency variable display apparatus and a flicker compensation method thereof, which may decrease a recognition luminance deviation occurring in a rapid change condition of a frame frequency.
To achieve these technical characteristics and other features and in accordance with the embodiments of the disclosure, as broadly described herein, a frequency variable display apparatus includes a display panel where a plurality of subpixels are provided, an image driving circuit configured to write an input image in the plurality of subpixels in a vertical active period, where a data enable signal swings, of one frame to implement target luminance in the plurality of subpixels, and a flicker compensation circuit configured to cause a leakage current flowing from the plurality of subpixels to signal lines corresponding thereto in a vertical blank period, where the data enable signal does not swing, of the one frame to implement flicker compensation luminance which is lower than the target luminance in the plurality of subpixels.
In another aspect of the present disclosure, a flicker compensation method of a frequency variable display apparatus, including a display panel where a plurality of subpixels are provided, includes writing an input image in the plurality of subpixels in a vertical active period, where a data enable signal swings, of one frame to implement target luminance in the plurality of subpixels and causing a leakage current flowing from the plurality of subpixels to signal lines corresponding thereto in a vertical blank period, where the data enable signal does not swing, of the one frame to implement flicker compensation luminance which is lower than the target luminance in the plurality of subpixels.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art.
Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.
The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for description of various embodiments of the present disclosure to describe embodiments of the present disclosure are merely exemplary and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout. Throughout this specification, the same elements are denoted by the same reference numerals. As used herein, the terms “comprise”, “having,” “including” and the like suggest that other parts can be added unless the term “only” is used. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless context clearly indicates otherwise.
Elements in various embodiments of the present disclosure are to be interpreted as including margins of error even without explicit statements.
In describing a position relationship, for example, when a position relation between two parts is described as “on˜”, “over˜”, “under˜”, and “next˜”, one or more other parts may be disposed between the two parts unless “just” or “direct” is used.
It will be understood that, although the terms “first”, “second”, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
The pixels may be arranged on the screen AA in a matrix type defined by the data lines DL, the gate lines GL, and the reference voltage lines. The pixels may be arranged as various types, such as a stripe type and a diamond type as well as a matrix type, on the screen AA.
The pixel array may include a plurality of pixel columns and a plurality of pixel lines L1 to Ln intersecting with the pixel columns. Each of the pixel columns may include pixels which are arranged in a Y-axis direction. A pixel line may include pixels which are arranged in an X-axis direction. One vertical period may be one frame period needed for writing image data DATA of one frame in all pixels of the screen. One horizontal period may be a time obtained by dividing one frame period by the number of pixel lines L1 to Ln. One horizontal period may be a time needed for writing the image data DATA of one pixel line, sharing a gate line GL, in pixels of one pixel line.
Each of the pixels may include a red (R) subpixel 101, a green (G) subpixel 101, a blue (B) subpixel 101, and a white (W) subpixel 101 for implementing colors.
The frequency variable display apparatus according to the present embodiment may be implemented as an electroluminescent display apparatus. In this case, a pixel circuit of the frequency variable display apparatus may include a light emitting device, a driving element, one or more switch elements, and a capacitor. The light emitting device may be implemented as an organic light emitting diode (OLED) or an inorganic light emitting diode. A driving current which allows the light emitting device to emit light may be adjusted based on a gate-source voltage of the driving element. Each of the driving element and the switch element may be implemented as a transistor. A semiconductor layer of the transistor may include amorphous silicon or polysilicon. A semiconductor layer of at least some of transistors may include oxide. The pixel circuit may be connected to a data line DL and a gate line GL. In
Touch sensors may be disposed on the display panel 100. The touch sensors may be arranged as an on-cell or add-on type on the screen AA of the display panel 100, or may be implemented as in-cell type touch sensors embedded in the pixel array. A touch input may be sensed through the touch sensors, or may be sensed through only pixels even without touch sensors.
A source driver 110 may convert the image data DATA, received from a timing controller 130, into gamma compensation voltages by using a digital-to-analog converter (DAC) to generate data voltages. The source driver 110 may supply the data voltages to the data lines DL. The data voltages may be supplied to the data lines DL and may be applied to gate electrodes of the driving elements through the switch elements of the subpixels 101. The source driver 110 may supply a reference voltage lines with a reference voltage received from a power circuit 200. The reference voltage may be supplied to the reference voltage lines and may be applied to a source electrode of the driving element through a switch element of each subpixel 101.
The source driver 110 may be implemented with one or more source drive integrated circuits (ICs). The source drive IC may be connected to the timing controller 130 through an internal interface circuit. The internal interface circuit may be implemented as an embedded clock point to point interface (EPI). The source drive IC may further include a touch driver. The touch driver may generate a touch sensor driving signal and may convert an electric charge variation of a touch sensor into touch raw data. The touch driver may transfer the touch raw data to a host system (not shown) through a separate interface circuit. The separate interface circuit may be implemented as a serial peripheral interface (SPI).
A gate driver 120 may be provided in a bezel region BZ which is outside a screen and does not display an image on the display panel 100. The gate driver 120 may sequentially supply a gate signal, synchronized with data voltages, to the gate lines GL according to control by the timing controller 130. The gate signal may simultaneously activate a pixel line into which a data voltage is charged. The gate driver 120 may output the gate signal by using one or more shift registers and may shift the gate signal. The gate signal may include one or more scan signals and an emission control signal. The gate signal (or scan signal) may include a gate on voltage VON and a gate off voltage VOFF, received from the power circuit 200, and a 3-level scan signal based on a gate-off control voltage received from the flicker compensation circuit 150.
The timing controller 130 may receive video data DATA and a timing signal, synchronized with the video data DATA, from the host system (not shown). The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync may define a vertical period (i.e., one frame). The horizontal synchronization signal Hsync may define a horizontal period. The data enable signal DE may define a time (i.e., a vertical active period) where the video data DATA is transferred in a vertical period. The other time, except the vertical active period, of the vertical period may be a vertical blank period. The data enable signal DE may swing in the vertical active period and may not swing in the vertical blank period.
The timing controller 130 may generate a source timing control signal DDC for controlling an operation timing of the source driver 110 and a gate timing control signal GDC for controlling an operation timing of the gate driver 120, based on the timing signal Vsync, Hsync, and DE received from the host system.
The host system be one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an automotive display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and a level shifter 140 may be integrated into one drive IC.
The level shifter 140 may shift a logic voltage level of the gate timing control signal GDC, output from the timing controller 130, to the gate on voltage VON or the gate off voltage VOFF to supply to the gate driver 120. A low logic voltage of the gate timing control signal GDC may be shifted to the gate off voltage VOFF, and a high logic voltage of the gate timing control signal GDC may be shifted to the gate on voltage VON.
The source driver 110 and the gate driver 120 may configure an image driving circuit. The image driving circuit may write an input image in the subpixels 101 in a vertical active period of one frame to implement target luminance in the subpixels 101.
The flicker compensation circuit 150 may cause a leakage current flowing from the subpixels 101 to signal lines (i.e., data lines and reference voltage lines) corresponding thereto in a vertical blank period of the one frame to implement flicker compensation luminance which is lower than the target luminance in the subpixels 101. When a frame frequency varies, a length of the vertical active period may be fixed, but a length of the vertical blank period may be changed. The flicker compensation circuit 150 may cause a leakage current in the vertical blank period to reduce luminance implemented in the subpixels 101, and thus, may decrease a recognition luminance deviation between frames occurring in a rapid change condition of the frame frequency.
The flicker compensation circuit 150 may cause a leakage current in the vertical blank period to output a gate-off control voltage between the gate on voltage VON and the gate off voltage VOFF to the gate driver 120. Accordingly, the gate on voltage VON, the gate off voltage VOFF, and the 3-level scan signal based on a gate-off control voltage may be generated from the gate driver 120. The flicker compensation circuit 150 may adjust a level of the gate-off control voltage, based on a change in length of the vertical blank period.
The flicker compensation circuit 150 may further output a first fixed voltage to the data lines DL and may further output a second fixed voltage to the reference voltage lines, so as to decrease luminance implemented through subpixels in the vertical blank period. A gate-source voltage of the driving element may be relatively reduced by the first fixed voltage in the vertical blank period, and thus, a current flowing in the driving element may decrease. Based on the second fixed voltage, a leakage current flowing to the reference voltage line may increase, and thus, a current flowing in the light emitting device may be reduced.
The flicker compensation circuit 150 may be integrated into the power circuit 200.
The power circuit 200 may generate various source voltages needed for panel driving. The power circuit 200 may generate the gate on voltage VON and the gate off voltage VOFF needed for generating of the scan signal, generate a high level source voltage EVDD and a low level source voltage EVSS which are to be supplied to each subpixel 101, and generate the reference voltage Vref which is to be supplied to a reference voltage line.
Referring to
The light emitting device EL may emit light with a driving current supplied from the driving transistor DT to implement luminance. An anode electrode of the light emitting device EL may be connected to a second node N2, and a cathode electrode thereof may be connected to an input terminal of a low level source voltage EVSS. In the same frame, the amount of current flowing in the light emitting device EL may be more reduced in a vertical blank period than a vertical active period. This may be caused by a leakage current occurring in the vertical blank period.
The driving transistor DT may generate the driving current based on the gate-source voltage thereof to supply to the light emitting device EL. A gate electrode of the driving transistor DT may be connected to a first node N1, a drain electrode thereof may be connected to an input terminal of a high level source voltage EVDD, and a source electrode thereof may be connected to the second node N2. In the same frame, the gate-source voltage of the driving transistor DT may be more reduced in the vertical blank period than the vertical active period. This may be caused by a leakage current occurring in the vertical blank period.
A gate electrode of the first switch transistor ST1 may be connected to a gate line GL. A first electrode of the first switch transistor ST1 may be connected to the data line DL, and a second electrode thereof may be connected to the first node N1.
A gate electrode of the second switch transistor ST2 may be connected to the gate line GL. A first electrode of the second switch transistor ST2 may be connected to the reference voltage line RL, and a second electrode thereof may be connected to the second node N2.
A first electrode of the storage capacitor Cst may be connected to the first node N1, and a second electrode thereof may be connected to the second node N2.
The first and second switch transistors ST1 and ST2 may be turned on based on a scan signal SCAN of a gate on voltage in the vertical active period, and thus, may connect the gate electrode of the driving transistor DT to the data line DL and may connect the source electrode of the driving transistor DT to the reference voltage line RL. Accordingly, a display programming operation for writing image data may be performed. When the display programming operation is completed in the vertical active period, the first and second switch transistors ST1 and ST2 may be turned off based on a scan signal SCAN of a gate off voltage.
The first and second switch transistors ST1 and ST2 may be turned on based on the scan signal SCAN of the gate on voltage in a vertical back porch VBP (see
The first and second switch transistors ST1 and ST2 may be slightly turned on, e.g., by a gate voltage smaller than the threshold voltage but sufficient to cause leakage, based on the scan signal SCAN of a gate-off control voltage in a vertical front porch VFP (see
Furthermore, in the vertical front porch VFP (see
A first switch SW1 and a second switch SW2 may be further connected to the reference voltage line RL. The first switch SW1 may connect an output terminal of the reference voltage Vref or an output terminal of the second fixed voltage AFIX2 to the reference voltage line RL. The second switch SW2 may connect a sensing circuit SU to the reference voltage line RL.
The first switch SW1 and the second switch SW2 may operate to be opposite to each other. That is, an electrical connection between the second switch SW2 and the reference voltage line RL may be turned off while the first switch SW1 is being connected to the reference voltage line RL. On the other hand, an electrical connection between the first switch SW1 and the reference voltage line RL may be broken while the second switch SW2 is being connected to the reference voltage line RL.
A sensing operation of the sensing circuit SU may be enabled while the second switch SW2 is being connected to the reference voltage line RL. The sensing operation of the sensing circuit SU may be performed after the sensing programming operation is completed in the vertical back porch, and thus, an electrical characteristic change (for example, a threshold voltage variation and an electron mobility change of the driving transistor) of each subpixel may be sensed.
Referring to
A vertical active period ACT and a vertical blank period BLK in the one frame time (vertical period) may be defined by a data enable signal DE. The vertical active period ACT may be a period where the data enable signal DE swings, and the vertical blank period BLK may be a period where the data enable signal DE does not swing.
Vertical blank periods BLK may be divisionally arranged with the vertical active period ACT therebetween in the one frame. The vertical blank period BLK may include a vertical back porch VBP arranged previously to the vertical active period ACT and a vertical front porch VFP arranged next to the vertical active period ACT.
The frequency variable display apparatus according to the present embodiment may have a VRR mode where a length of one frame varies. In the VRR mode, as in
In a vertical active period ACT having a fixed length, a display programming operation for writing an image may be performed.
In a vertical front porch VFP having a variable length, a flicker compensation operation for reducing luminance may be performed. The flicker compensation operation may be performed so that the amount of reduction of luminance increases as a length of the vertical front porch VFP increases.
The sensing programming operation and the sensing operation described above may be performed in the vertical back porch VBP having a fixed length. In the VRR mode, because a real-time (RT) sensing operation is performed in the vertical back porch VBP having the fixed length, a sensing line compensation algorithm may be applied in real time without an error. The sensing line compensation algorithm may be technology which differentially applies a compensation gain for luminance restoration, based on a position of a pixel line where a sensing operation is performed, and thus, increases image quality. For example, when the sensing operation is performed in a blank period where a length is changed based on a frame frequency, it may be difficult to apply the sensing line compensation algorithm in real time. This may be because a length of a blank period should be more reflected in a compensation gain, but the length of the blank period may not be known until the blank period ends. That is, this may be because the length of the blank period may not be known at a time at which the sensing line compensation algorithm is executed.
Peak low points of
The display programming operation and the emission operation may be successively performed in one frame. The number of display programming operations may increase as the number of frame arrangements in a predetermined time increases, namely, a frame frequency increases, and thus, recognition luminance may be reduced. For example, the number of display programming operations in a predetermined time in a frame frequency of 240 Hz may be twelve, the number of display programming operations in a predetermined time in a frame frequency of 120 Hz may be six, and the number of display programming operations in a predetermined time in a frame frequency of 60 Hz may be three. As a result, a real-time luminance integral value (i.e., recognition luminance) of a frame frequency of 240 Hz may be L1, a real-time luminance integral value (i.e., recognition luminance) of a frame frequency of 120 Hz may be L2 which is higher than L1, and a real-time luminance integral value (i.e., recognition luminance) of a frame frequency of 60 Hz may be L3 which is higher than L2.
As described above, when it is assumed that a gray level of a display image is constant, recognition luminance may be relatively higher in a case, where a frame frequency is a low frequency, than a case where the frame frequency is a high frequency. Accordingly, a luminance deviation caused by a change in recognition luminance may occur when the frame frequency is changed from a high frequency to a low frequency.
A frequency-based luminance deviation, as in
Referring to
The flicker compensation circuit 150 may output a gate-off control voltage AVOFF, so as to cause the leakage current flowing from the subpixels to the signal lines corresponding thereto in the vertical front porch VFP. The gate-off control voltage AVOFF may configure a 3-level scan signal SCAN along with a gate on voltage VON and a gate off voltage VOFF. The gate-off control voltage AVOFF may be set to be lower than the gate on voltage VON and higher than the gate off voltage VOFF. In a case where the gate on voltage VON is set to a voltage of VG1 or more in a Vg-Id curve graph of
The flicker compensation circuit 150 may increase a level of the gate-off control voltage AVOFF in proportion to a length of the vertical front porch VFP. As a level of the gate-off control voltage AVOFF increases, a leakage current flowing through the first and second switch transistors ST1 and ST2 may increase.
To this end, the flicker compensation circuit 150 may include a counter 152 and a voltage controller 154.
A length of the vertical front porch VFP defined by a vertical synchronization signal Vsync and a data enable signal DE may vary based on a frame frequency. The counter 152 may count a length of the vertical front porch VFP with a reference clock RCLK to continuously supply a real-time count value CNT to the voltage controller 154.
The voltage controller 154 may progressively increase a level of the gate-off control voltage AVOFF, based on the real-time count value CNT corresponding to a length of the vertical front porch VFP. That is, a level of the gate-off control voltage AVOFF may increase up to a target value in the vertical front porch VFP.
The voltage controller 154 may further output the first fixed voltage AFIX1 to the data lines DL during the vertical front porch VFP and may further output the second fixed voltage AFIX2 to the reference voltage lines RL during the vertical front porch VFP, so as to implement flicker compensation luminance in subpixels during the vertical front porch VFP.
The first fixed voltage AFIX1 may be lower than a data voltage Vdata charged into gate nodes N1 of the subpixels in a vertical active period ACT. As a potential difference between the first fixed voltage AFIX1 and the data voltage Vdata increases, a gate potential (an electric potential of N1) of a driving transistor DT may be quickly discharged up to the first fixed voltage AFIX1 from the data voltage Vdata. As a result, in the vertical front porch VFP, a gate-source voltage Vgs of the driving transistor DT may relatively decrease, and thus, a driving current Ids flowing between a drain and a source of the driving transistor DT may be reduced.
The second fixed voltage AFIX2 may be lower than a reference voltage Vref charged into gate nodes N2 of the subpixels in the vertical active period ACT. In the vertical front porch VFP, a source potential (an electric potential of N2) of the driving transistor DT may be maintained as an operation point voltage of the light emitting device EL which is higher than the reference voltage Vref. At this time, when the second fixed voltage AFIX2 is sufficiently lower than the reference voltage Vref, a leakage current flowing to the reference voltage line RL may increase, and thus, a current Iel flowing in the light emitting device EL may decrease.
Referring to
The data voltage Vdata may be applied to the data line DL and the reference voltage Vref may be applied to the reference voltage line RL, in synchronization with a gate on voltage VON of the first pulse P1.
The first fixed voltage AFIX1 may be applied to the data line DL and the second fixed voltage AFIX2 may be applied to the reference voltage line RL, in synchronization with a gate-off control voltage AVOFF of the second pulse P2.
The first pulse P1 may be sequentially applied to all gate lines GL #1 to GL #n in the vertical active period ACT, and the second pulse P2 may be simultaneously applied to all gate lines GL #1 to GL #n in the vertical front porch VFP. In the vertical front porch VFP, the first fixed voltage AFIX1 may be simultaneously applied to all data lines DL and the second fixed voltage AFIX2 may be simultaneously applied to all reference voltage lines RL, in synchronization with the second pulse P2.
Referring to
Referring to
The flicker compensation circuit may previously store a plurality of count threshold values TH1 to TH3 having different magnitudes, which respectively correspond to a plurality of frame frequencies, and may step by step increase a level of a gate-off control voltage AVOFF up to a target value in real time, based on a sequential comparison operation between the plurality of count threshold values TH1 to TH3 and a real-time count value of a length of the vertical front porch VFP.
That is, during a vertical front porch VFP of a first frame, the flicker compensation circuit may step by step increase a level of the gate-off control voltage AVOFF up to a first target value (for example, AVOFF2) in real time, based on a real-time count value of a first length of the vertical front porch VFP, and during a vertical front porch VFP of a second frame, the flicker compensation circuit may step by step increase a level of the gate-off control voltage AVOFF up to a second target value (for example, AVOFF4) in real time, based on a real-time count value of a second length of the vertical front porch VFP.
In this case, the second length of the vertical front porch VFP may be longer than the first length of the vertical front porch VFP, and the second target value of the gate-off control voltage AVOFF may be greater than the first target value of the gate-off control voltage AVOFF. Accordingly, a leakage current may more increase in the second frame than the first frame.
Referring to
During a vertical front porch VFP of a first frame, the flicker compensation circuit may linearly increase a level of the gate-off control voltage AVOFF up to a first target value (for example, AVOFF2) in real time, based on a real-time count value of a first length of the vertical front porch VFP, and during a vertical front porch VFP of a second frame, the flicker compensation circuit may linearly increase a level of the gate-off control voltage AVOFF up to a second target value (for example, AVOFF4) in real time, based on a real-time count value of a second length of the vertical front porch VFP.
In this case, the second length of the vertical front porch VFP may be longer than the first length of the vertical front porch VFP, and the second target value of the gate-off control voltage AVOFF may be greater than the first target value of the gate-off control voltage AVOFF. Accordingly, a leakage current may more increase in the second frame than the first frame.
Referring to
Subsequently, the flicker compensation method of the frequency variable display apparatus according to the present embodiment may cause a leakage current flowing from the subpixels to signal lines corresponding thereto in a vertical blank period, where the data enable signal does not swing, of the one frame to implement flicker compensation luminance which is lower than the target luminance in the subpixels (S20).
The present embodiment may realize the following effect.
The present embodiment may decrease a recognition luminance deviation occurring in a rapid change condition of a frame frequency, thereby considerably improving display quality.
The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure including the following claims.
The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various embodiments to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0197157 | Dec 2023 | KR | national |
