Claims
- 1. An FSK signal receiver comprising:
- a demodulator demodulating a multi-value FSK signal into a voltage signal in response to transmission rate information, the voltage signal having a voltage depending on an instantaneous frequency of the multi-value FSK signal;
- an A/D converter converting the voltage signal into a corresponding digital signal, and outputting the digital signal;
- a bit sync device generating a bit sync signal from the output signal of the A/D converter;
- a bit-state detector including said bit sync device therein;
- said bit-state detector detecting a bit state from the output signal of the A/D converter in response to a threshold value at a timing responsive to the bit sync signal, and outputting recovered data corresponding to the detected bit state;
- an error correction device correcting errors in the recovered data;
- a histogram calculator providing histograms of digital values of the output signal of the A/D converter which occurs at every moment of the bit-state detection by the bit-state detector for respective different symbol states in response to output data from the error correction device;
- means for extracting the transmission rate information from the output data of the error correction device, and feeding the transmission rate information to the demodulator; and
- means for adjusting the threshold voltage used in the bit-state detector in response to the histograms provided by the histogram calculator and also the transmission rate information extracted by the extracting means.
Priority Claims (4)
Number |
Date |
Country |
Kind |
6-276442 |
Nov 1994 |
JPX |
|
6-276443 |
Nov 1994 |
JPX |
|
6-276444 |
Nov 1994 |
JPX |
|
7-152876 |
Jun 1995 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/548,373 filed Nov. 1, 1995, now U.S. Pat. No. 5,781,588.
US Referenced Citations (11)
Foreign Referenced Citations (1)
Number |
Date |
Country |
61-141228 |
Jun 1986 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
548373 |
Nov 1995 |
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