Fully integrated reference circuit having controlled temperature dependence

Abstract

Mobility in an FET is used as a time standard to develop a resistance (or a transconductance or a current) reference which may be fully integrated and which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding a precise R-C product which may be implemented fully in integrated form.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to circuits for producing reference voltages and reference currents, and to time reference circuits which use reference voltages and/or currents to create the time reference, such as oscillators, filters, time delay circuits and clocks, and more specifically relates to a reference circuit which is completely formed as an integrated circuit (i.e., having no external components) and which has either a controlled temperature dependence or substantially no dependence on temperature.

2. Related Art

It is generally desirable for integrated circuits to be fabricated entirely in integrated form (i.e., without any external components or external time references being needed), because an external connection to a component or time reference is a potential source of noise injection or other board or package parasitic problems. The external connection and component also add considerable complexity and significant cost. There are some circuits, however, such as oscillators and filters, which are inherently difficult to fabricate entirely in integrated form, because they require an accurate time constant, and accurate time constants are not readily implemented entirely in integrated form.

Time constants are typically derived from an R-C, L-C or crystal resonator time reference. Crystal resonators cannot be fabricated in an integrated circuit, so use of a crystal resonator inherently involves an external component and connection. Inductors can be fabricated in integrated form, but only in small values as a practical matter, so the use of integrated L-C circuits is limited to high-frequency applications. Internal resistors and capacitors are easy to fabricate in integrated form, but they have inaccurate values with a resulting R-C time constant tolerance in the +/- 30-60% range.

Hybrid circuits have been used to improve on the inaccuracy of integrated R-C time constants. Using an external capacitor improves the tolerance by about 10% and makes big time constants possible, but this becomes unwieldy and expensive if multiple time constants are required. The external connection is also a disadvantage, as noted above, and the inaccuracy of integrated R-C time constants is due mostly to variation of the resistance value with processing and temperature. Since integrated capacitors are usually temperature stable, combining them with an external resistor can yield a time constant accuracy in the range of 15%. It's also easy to use a single master resistor to achieve multiple time constants, but the external connection is still a significant disadvantage. A big jump in accuracy is achieved when trimmed internal resistors having a low temperature coefficient (TC) are used, but unfortunately this results in a big jump in process complexity and product cost.

Perhaps the most popular approach to timing accuracy at this time is to use an accurate external clock for driving switched capacitor circuits. Assuming the availability of such a clock, the system is made more complex by the presence of switching noise and the need for anti-alias and smoothing filters. Continuous-time filters can also be locked to an external clock, but this generally requires an additional phase locked loop (PLL) in the design. Both of these approaches also suffer from the disadvantage of requiring an external connection.

Many applications require an accuracy in timing variation in the range of 5% or better. Accordingly, there is a need for an integrated circuit design for producing a time constant having an accuracy of 5% or better without requiring any external component, clock, or trimming.

In U.S. Pat. No. 4,843,265, a temperature and processing compensated time delay circuit is described which can be fabricated in a monolithic integrated circuit. This circuit is shown in FIG. 1. A bias voltage connected to the gate of a field effect transistor (FET) M.sub.12 is deliberately designed to have a non-linear variation with temperature which substantially matches and compensates for the variation in temperature exhibited by the mobility of the FET, so as to make the drain current of the FET have a value which is not very much dependent upon temperature. The drain current of the FET is then used to discharge a capacitor (not shown) to provide a time constant. This approach promises to achieve the high accuracy desired, but the disclosed circuit implementation still has a number of disadvantages.

The gate bias voltage is given a temperature dependence in this circuit by subtracting three negative temperature coefficient base-emitter voltages (3 V.sub.be), generated by bipolar transistors Q.sub.1, Q.sub.2 and Q.sub.3, from a scaled and temperature-invariant bandgap reference voltage (V.sub.BG). The threshold voltage in FET M.sub.12 is cancelled by level-shifting the gate bias voltage up with another FET M.sub.54. Buffers are used to scale the bandgap reference and to provide a low impedance drive for the current source transistor M.sub.12.

This circuit has the disadvantage that the negative temperature coefficient term cannot be arbitrarily scaled. The coefficient of 3 can be reduced to 2 or increased to 4 by deleting or adding a bipolar transistor to substract or add a base-emitter voltage (V.sub.be), but coefficients in between cannot be selected. This either makes the compensation only approximate (i.e., still leaves a significant temperature variation) or else constrains the drain current of FET M.sub.12 to a single predetermined value that corresponds to the number of V.sub.be voltages subtracted by the circuit.

Another disadvantage stems from the fact that the circuit does not assure that FET M.sub.54 will have its source at the same potential as the source of FET M.sub.12. If the two sources are not at the same potential, the turn on voltages at which the two FETs turn on are not the same and there will not be exact cancellation of the threshold voltage in FET M.sub.12 ! The FIG. 1 circuit also is unduely complex since an operational amplifier A.sub.1 is needed to scale up V.sub.BG and another operational amplifier A.sub.2 is needed to match impedances.

Still another disadvantage is that the FIG. 1 circuit has no way of more accurately matching the temperature variation characteristic of mobility than by the 3 V.sub.be term. This term does not provide an exact match. Furthermore, the circuit is strictly designed for temperature compensating the drain current of an FET connected so as to discharge a capacitor. While this automatically temperature compensates the time delay produced by the capacitor being discharged, there are many other circuit configurations where the time constant will not be temperature compensated properly by the bias voltage dependence on temperature that is created by the FIG. 1 circuit.

One example of a circuit where a different temperature dependence is needed for the bias voltage is in a current source reference or a time reference that uses a current for the reference, such as a transconductance type filter. In this case, the drain current of the FET that needs to be temperature compensated is not proportional to the bias voltage, as is assumed in the FIG. 1 circuit, but instead is proportional to the bias voltage squared. An entirely different temperature dependence is needed for the bias voltage in such a circuit if the time constant is expected to be constant with respect to temperature variation.

There are also situations where it is desired to have a time reference value depend upon temperature, but where the temperature dependence characteristic of mobility in an FET is not the desired temperature dependence characteristic. It would be desirable to be able to arbitrarily tailor the temperature dependence of a time reference (or more generally the temperature dependence of a current source, or the temperature dependence of a bias voltage for an FET).

SUMMARY OF THE INVENTION

It is an object of this invention to provide an accurate time reference with an integrated circuit that requires no external components or connections other than usual supply voltages.

Another object is to provide a current reference circuit which may be fully integrated (i.e., not requiring any external component or timing signal) with a capacitor and other integrated circuit components to produce an accurate time reference.

Still another object is to provide a current reference circuit which may be fabricated as a monolithic integrated circuit and which may provide a current which has an arbitrary predetermined variation in value with respect to temperature variation.

It is a further object to provide a current reference circuit which may be fabricated as a monolithic integrated circuit and which may provide a current of arbitrary value that does not vary with respect to temperature variation.

It is also an object to provide a bias voltage for an FET which may be fabricated fully in integrated form and which exhibits an arbitrary predetermined variation in value with respect to temperature variation.

Another object is to provide a circuit that may be fabricated entirely in integrated form and which provides an accurate transconductance of arbitrary value and which does not vary with respect to temperature variation.

These and further objects and features have been achieved by using mobility in an FET as a time standard to develop a resistance (or a transconductance or a current) which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature.

In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature when it charges or discharges a capacitor, yielding a precise R-C product.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art circuit in which the drain current of an FET is stabilized with respect to temperature variation in order to produce a temperature stable time constant.

FIG. 2 is a simple R-C filter circuit in which the resistance is implemented with an MOS FET having a gate bias voltage of V.sub.X +V.sub.TH.

FIG. 3 shows a current source implemented by a MOS FET biased into saturation by a gate voltage V.sub.X +V.sub.TH.

FIG. 4 shows the FIG. 3 circuit in more detail and in which the gate voltage V.sub.X +V.sub.TH is generated so as to make the output current temperature invariant.

FIG. 5 is a circuit for use in experimentally determining proportionality factors for the PTAT sources in FIG. 4.

FIG. 6 is an example curve of V.sub.X as a function of temperature determined using the circuit of FIG. 5.

FIG. 7 is a circuit which converts a bandgap voltage reference into a constant current reference using the present invention.

FIG. 8 is a generalized bias circuit for providing V.sub.X +V.sub.TH in accordance with this invention.

FIG. 9 is a oneshot circuit that uses the FIG. 8 circuit to bias an MOS FET for constant current operation that is invariant to temperature.

FIG. 10 is a prior art Gm/C filter stage in which transconductance may be controlled by controlling the bias voltage of an FET current source using the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

All the embodiments use mobility in a MOS FET as a time reference. Mobility is sensitive to doping concentration and temperature. For native devices (low doping), mobility is insensitive to processing, and for typically implanted devices (eg., 1.times.10.sup.17 NMOS), 10% doping change causes only a 2.6% mobility shift. The units for mobility are cm-squared per volt-seconds. Since area is invariant and voltage can be controlled by design, the remaining parameter is seconds. Control of mobility is fairly tight with standard processing. For native devices, mobility is fairly independent of doping, so there is even less variability when the time (or current or voltage) reference is made in accordance with this invention using a native FET device.

Referring now to FIG. 2, a simple single-pole, low-pass MOS FET filter is shown. Capacitance is equal to capacitor area A times C.sub.OX, and the triode region resistance is equal to ##EQU1## where .mu. is mobility, C.sub.OX is the oxide capacitance per unit area, W is the width of the channel, L is the length of the channel, V.sub.GS is the gate to source voltage, and V.sub.TH is the threshold voltage. Therefore the R-C time constant is ##EQU2## which reduces to ##EQU3## If we bias V.sub.GS with a voltage V.sub.X plus V.sub.TH, as shown in FIG. 2, and substitute V.sub.X +V.sub.TH for V.sub.GS, the time constant reduces further to ##EQU4##

Capacitor area and W/L are well defined and temperature invariant. Mobility only varies a few percent in production, but it has a large temperature coefficient, typically varying with temperature to the -3/2 power. Overall temperature invariance may be achieved by designing V.sub.X to have an amplitude that varies with temperature opposite to the temperature variation of .mu., namely by giving V.sub.X a temperature coefficient (tc) proportional to absolute temperature T to the +3/2 power. Scaling of the corner frequency may be done by changing capacitor area, device W/L, or the nominal value of V.sub.X. Simple programming is also possible by using a single control voltage switched to the gates of different sized transistors connected in parallel. There are some disadvantages to this circuit architecture, however. Any DC voltage across the MOS FET device and/or body effect will make the on-resistance vary, so circuitry needs to be added to compensate.

A more practical reference may be built using a MOS FET device in saturation, as shown in FIG. 3. Assuming saturation ##EQU5## An equivalent resistance may be defined as V.sub.X divided by I.sub.OUT. ##EQU6## The principle is the same. As with the previous case, constant resistance is achieved by having V.sub.X vary with T to the 3/2 power. For constant current in the FIG. 3 circuit without variation due to temperature change ##EQU7## This condition simplifies to ##EQU8## Therefore, for constant current, V.sub.X needs to vary with T to the 3/4 power, or half of the mobility drift. This current source furthermore is proportional to C.sub.OX, and will therefore track timing capacitor variation. This reference can also be used in applications other than timing circuits if the tolerance due to C.sub.OX variation is acceptable. The reference can also be scaled via programming to account for measured, non-nominal C.sub.OX.

The circuit in FIG. 3 thus requires a bias voltage V.sub.X that has either approximately T.sup.3/2 absolute temperature variation (for constant resistance) or else a temperature variation of approximately T.sup.3/4 (for a constant current). FIG. 4 is a generalized circuit representation illustrating functionally how a circuit may be implemented which produces either one of these bias voltages (or for that matter any other desired arbitrary bias voltage temperature dependence characteristic). In FIG. 4, current sources I.sub.1 through I.sub.n are shown. Current source I.sub.1 is a constant current source that does not vary with temperature. Current source I.sub.2 is a current source that is proportional to absolute temperature (known as PTAT). Current source I.sub.3 is a current source which is proportional to absolute temperature squared (PTAT.sup.2) Current source I.sub.n is a current source which is proportional to absolute temperature to the n-1 power (PTAT.sup.n-1). As will become more apparent as this description proceeds, the value of n may vary from 2 upwards to whatever number is required to produce a desired V.sub.GS temperature characteristic of an arbitrary accuracy. In general, values of n between 2 and 4 should provide reasonable accuracy. Furthermore, one or more of the PTAT current sources in a series might have a value so low that a suitable circuit may be designed with acceptable accuracy without actually implementing one or more of the small PTAT terms in the series.

As will become more apparent in connection with later description of practical circuits, each of these current sources is actually implemented by creating a corresponding voltage source (V.sub.1 for I.sub.1 ; V.sub.2 for I.sub.2 ; etc.) having the right temperature characteristic (i.e., invariant for V.sub.1 ; PTAT for V.sub.2 ; PTAT.sup.2 for I.sub.3 ; PTAT.sup.3 for I.sub.4 ; etc.) and applying the voltage source across a resistance. The temperature characteristic of the resistances used to implement the current sources and the temperature characteristic of the R2 resistance are the same in the same integrated circuit. Therefore, each one of the voltage sources V.sub.1 to V.sub.n produces a voltage component contribution to the total voltage V.sub.X that is equal to a resistor ratio times the value of the voltage source used to implement that current source. Since resistor ratios determine the coefficients of each component of V.sub.X, temperature dependence of the resistances has no effect. If for each component portion of V.sub.X, we let K.sub.i be the amplitude and T.sup.i-1 be the temperature dependency, V.sub.X becomes ##EQU9## which more closely resembles the form in which V.sub.X is actually implemented in the preferred embodiments.

Still referring to FIG. 4, the current-source PMOS, M.sub.3, and the threshold-cancelling device, M.sub.1, are operated with a common source-voltage for improved matching and elimination of body effect. No amplifiers are needed as well because M.sub.2 provides feedback from the drain of M.sub.1 to the gate of M.sub.1, thereby providing a low-impedance output for V.sub.TH and yielding a smaller, more-accurate circuit. A small current flows through large device M.sub.1, forcing its V.sub.GS to approximately its threshold value V.sub.TH. The key design decision is determining the proper ratio of the various current sources I.sub.1 to I.sub.n (or more accurately the voltage sources V.sub.1 to V.sub.n that implement these current sources) to best match the mobility temperature drift of M.sub.3.

FIG. 5 shows a circuit that may be used to experimentally determine the right proportions for the current (or voltage) source terms. An opamp drives the gate of M1 to the gate-source voltage necessary for a drain current equal to a desired fixed current load I. We assume here that we want to determine the V.sub.X curve which makes I.sub.OUT of M.sub.3 (FIG. 4) constant. I is selected to have the amplitude desired for I.sub.OUT. If a temperature dependence is desired for I.sub.OUT, I (in FIG. 5) is given this dependence! Large device M2 operates at low current to make V.sub.GS equal to the threshold voltage. The temperature T of the circuit is then swept over the range of interest (also varying I with the temperature dependence of I.sub.OUT if a temperature dependence is desired for I.sub.OUT) and V.sub.X is measured as a function of temperature. FIG. 6 shows a curve which might be obtained using this method and three points on this curve at temperatures T.sub.0, T.sub.1 and T.sub.2 with corresponding voltage values V.sub.0, V.sub.1 and V.sub.2. The design task then becomes one of synthesizing this experimentally determined curve with the various temperature dependent sources. V.sub.X as a function of temperature can be defined as ##EQU10## where k.sub.1 is a temperature independent term, k.sub.2 is the amplitude of a PTAT term, k.sub.3 is the amplitude of a PTAT.sup.2 term, and k.sub.n is the amplitude of a PTAT.sup.n-1 term. If a straight-line approximation is good enough, then only the first two terms are needed and simultaneous equations can be solved using the values of V.sub.X at T.sub.0 and T.sub.1. A more exact approximation can be done by developing three simultaneous equations using the values of V.sub.X at T.sub.0, T.sub.1, and T.sub.2. Four (or more) voltage values may be used to solve four (or more) simultaneous equations in the same way.

Once the synthesis terms are known, the actual circuit is simple to implement, especially if a temperature invariant voltage reference is already available somewhere else in the design. FIG. 7 is a circuit which may be used to convert a bandgap voltage reference V.sub.BG into a constant current reference I.sub.OUT. Going up a V.sub.be at Q.sub.1 and down a V.sub.be at Q.sub.2, the base voltage of Q.sub.3 is also equal to V.sub.BG. Therefore, the collector current IC2 of Q.sub.2 is approximately V.sub.BG /R.sub.1. Since the emitter voltage of Q.sub.3 is V.sub.BG -V.sub.be, the collector current IC3 of Q.sub.3 will be PTAT. These two currents IC2 and IC3 are combined in R.sub.4 to provide the bias voltage V.sub.X. M5 is also biased for constant current, so the Q.sub.1 and Q.sub.2 base emitter voltages nearly track over temperature. Long channel device M4 provides a low current for the large threshold cancelling device M6. Both M6 and the current source device M8 are split in half to allow common centroid layout of these critical components.

The FIG. 7 circuit was built on a test mask in a 200 Angstrom gate process. The cancellation of mobility drift resulted in a variation in I.sub.OUT of only +/- 1.3% from -40 to 120 degrees C.

FIG. 8 is a more generalized bias circuit designed to operate in multiple applications. This circuit provides both a temperature stable voltage reference, V.sub.REF, and the bias for a temperature stable current reference, V.sub.BIAS. Positive tc (temperature coefficient) current is derived with a conventional PTAT generator consisting of Q3, Q2, R4, and the M12-M10 mirror. In addition to biasing the bases of Q2 and Q3, M5 provides a negative tc current with a value of V.sub.be of Q3 divided by R3. These currents are combined in different proportions to get V.sub.REF and V.sub.X. PMOS transistor MVT operates at low current for V.sub.GS equal to V.sub.TH, and Q1 has been added to provide NPN base current compensation. Note that this circuit doesn't have second order correction, which could have been added with a translinear multiplier operating on the PTAT current to get a PTAT.sup.2 current. V.sub.REF is set at 2 V, with taps at 1.5 V and 1 V available for various applications. This circuit will now be used in a circuit applications, in which this FIG. 8 reference circuit is labelled "PREFQ".

FIG. 9 is a oneshot circuit that uses the reference circuit PREFQ to bias PMOS MR for constant current. With V.sub.IN high, capacitor CT is held at zero volts. When V.sub.IN goes low, the constant drain current of MR ramps the voltage on CT. The reference circuit PREFQ also provides a 2 volt reference at the comparator negative input. When the ramp reaches this level, the output switches, and hysteresis is applied by switching the comparator negative input to a 1 volt reference. In the off state with V.sub.IN high, the drain of M2 is held low. Diode Q.sub.1 is off, so no current flows through ramp reset switch M3. This resets the voltage on CT to zero without the need for a large device, minimizing loading of the timing capacitor and glitching due to feedthrough of the input voltage.

Another application of this invention is for transconductance control, which is especially useful for filtering. FIG. 10 shows a prior art Gm/C filter stage. For this simple Gm/C stage, the transconductance of the input device M2 is ##EQU11## Letting the the gate-source voltage of M.sub.1 be V.sub.X +V.sub.TH, the transconductance turns out to be

Gm.sub.2 =.mu.C.sub.OX V.sub.X K where K is a constant set by the device areas. Designing V.sub.X for approximately a T.sup.3/2 dependence will therefore yield temperature invariant filtering.

What has been described is how a mobility reference can provide a temperature invariant current source proportional to C.sub.OX, or with a different tc a transconductance proportional to C.sub.OX. These components can be combined with capacitors to build temperature stable oscillators, delay blocks, or filters, without the need for external components or trimming. While the specific circuits described use BICMOS technology, the fact that bandgap references are built in CMOS shows that the same principles can be applied there. It should also be possible to use parasitic MOS devices available in many bipolar processes to build time references. Although various embodiments of the present invention have been shown and described in detail, many other embodiments that incorporate the teachings of this invention may be easily constructed by those skilled in this art. Furthermore, modifications, improvements and variations upon any of these embodiments would be readily apparent to those of ordinary skill and may be made without departing from the spirit and scope of this invention. For example, whereever PMOS transistors are used, NMOS transistors could be used instead by substituting V.sub.CC for ground and ground for V.sub.CC and by reversing the directions of current sources and polarities of voltage sources.

Claims

1. A circuit for producing an output reference current having an arbitrary predetermined temperature dependence, comprising:

a first field effect transistor (FET) having a gate, a source, and a drain;

a second field effect transistor having a gate, a source, and a drain,

said first FET source and said second FET source being commonly connected,

said first FET having a threshold voltage,

a bias source, operably coupled to the drain, gate and source of the second FET, that forces the voltage between the gate and the source of the second FET to be substantially equal to the threshold voltage of the first FET; and

a temperature dependent current source that provides a temperature dependent current through a first resistor to produce a temperature dependent voltage;

the gate of the first FET being operably coupled to the gate of the second FET through the first resistor so that the voltage between the gate and the source of the first FET is equal to a sum of the second FET's gate to source voltage plus the temperature dependent voltage, and producing the output reference current at the drain of the first FET,

a second resistor coupled between the first resistor and the sources of the first and second FETs,

said temperature dependent current source including:

a first current source which is substantially independent of temperature variation and has a first current value determined by a first scaling factor of arbitrary value, and

a second current source which is substantially proportional to absolute temperature and has a second current value determined by a second scaling factor of arbitrary value.

2. A circuit as claimed in claim 1, wherein said first and second FETs are PMOS transistors and wherein the sources of the first and second FETs are both connected to a common supply voltage.

3. A circuit as defined in claim 1, wherein said less source further comprises feedback means coupled between the drain of said second FET to the gate of said second FET for providing a low output impedance characteristic.

4. A circuit as defined in claim 1, wherein said further comprises a first and second current sources and third resistor, respectively and wherein said first and second scaling factors are determined by ratios of resistor values of said resistors.

5. A circuit as defined in claim 1, wherein said temperature dependent current source further includes a third current source.

6. A circuit according to claim 1, wherein said bias source includes a current source coupled to said drain of said second FET and a feedback transistor coupled between the gate and drain of said second FET.

7. A circuit according to claim 1, wherein said first and second current sources each include a respective voltage source coupled across a respective resistive device.

8. A circuit as defined in claim 5, wherein said third current source has a third current value that is substantially proportional to absolute temperature squared and has a value determined by a third scaling factor of arbitrary value.

9. A circuit according to claim 8, wherein said third current source includes a further voltage source coupled across a further resistive device.

10. A circuit for producing an output reference current having an arbitrary predetermined temperature dependence, comprising:

a first field effect transistor (FET) having a gate, a source, and a drain;

a second field effect transistor having a gate, a source, and a drain,

said first FET source and said second FET source being commonly connected,

a bias source, operably coupled to the drain, gate and source of the second FET, that forces the voltage between the gate and the source of the second FET to be substantially equal to the threshold voltage; and

a temperature dependent current source that provides a temperature dependent current through a first resistor to produce a temperature dependent voltage, the temperature dependent current source including a plurality of current source circuits each contributing a portion "i" the temperature dependent current,

a second resistor coupled between the first resistor and the sources of the first and second FETs,

the gate of the first FET being operably coupled to the gate of the second FET through the first resistor so that the voltage between the gate and the source of the first FET is equal to a sum of the second FET's gate to source voltage plus the temperature dependent voltage, and producing the output reference current at the drain of the first FET,

said temperature dependent current being substantially equal to:

.epsilon..sub.i=1.sup.n M.sub.i T.sup.i-1

where M.sub.i is a predetermined amplitude of the ith portion of the temperature dependent current, T is absolute temperature and n is at least 2.

11. A circuit as claimed in claim 10, wherein said first and second FETs are PMOS transistors and wherein the sources of the first and second FETs are both connected to a common supply voltage.

12. A temperature dependent current source as defined in claim 10, wherein said circuit further comprises scaling resistors and wherein M.sub.i is determined by ratios of resistor values of said scaling resistors and said first resistor.

13. A circuit according to claim 10, wherein said bias source includes a current source coupled to said drain of said second FET and a feedback transistor coupled between the gate and drain of said second FET.