Patent Application
20190051060
The present disclosure generally relates to the field of electronics. More particularly, an embodiment relates to functional safety critical audio system for autonomous and industrial applications.
Functional safety is important for the real time complex systems such as IOT (Internet Of Things) applications, like automotive and industrial segments. All these applications may impose tight constraints on the system to perform safely and reliably under complex and noisy system environments across a product's life cycle.
Additionally, functional safety critical automotive and industrial applications require a reliable audio safety alert warning chime system, e.g., enabled with embedded on-demand or self-checking safety mechanisms. This puts constraints on system to periodically enable safety mechanisms to monitor the fidelity of the ‘Alert Audio Messaging System’ wherever functional safety is of primary concern, without disturbing an end-user at the same time an audio message is delivered during a real safety alert.
However, conventional audio systems used for functional safety may use a communication channel that is omnidirectional. With such an implementation, it is not possible to periodically enable safety mechanisms to monitor the ‘Alert Audio Messaging’ without disturbing the end-user.
The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. Further, various aspects of embodiments may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware (such as logic circuitry or more generally circuitry or circuit), software, firmware, or some combination thereof.
As mentioned above, conventional audio systems used for functional safety may use a communication channel that is omnidirectional (e.g., sensing audio signals using a microphone). With such an implementation, it is not possible to periodically enable safety mechanisms to monitor the ‘Alert Audio Messaging’ without disturbing an end-user. Hence, the end-user will be hearing (and being distracted) by the periodic alert audio messages.
To this end, some embodiments relate to functional safety critical audio system for autonomous and industrial applications (which operate without distracting an end-user). In an embodiment, a Parametric Acoustic Array (PAA) is used for audio communication. One or more PAAs may be used in part because they provide high directivity and may be used for continuous monitoring of an audio system for functional safety (e.g., using a voice loop back), without disturbing the end-user. In one embodiment, safety island logic generates audio test patterns which are used to provide functional safety. In another embodiment, an audio loopback communication mismatch detection mechanism is provided where audio processing unit(s) would be able to provide corrective feedback using an audio channel (e.g., from a host unit to CODEC (Coder-Decoder) logic).
Such embodiments are envisioned to provide one or more of: unique and differentiating architecture solution; helping in enabling a functional safety audio test mechanism for functional safety audio sub-systems; and/or help with continuous monitoring of audio alert messages, while not disturbing end-users (or other vehicle occupants such as passengers) with periodic audio test patterns.
In an embodiment, PAA transducers 102/104 include parametric loudspeakers which generate unidirectional sound using ultrasound waves. In operation, the PAA transducers rely on the interaction of non-linear acoustics of sound waves in air, and an audio signal is generated in the air because of the self-demodulation effect. Moreover, during functional safety audio system testing (e.g., based on test patterns generated by functional safety island engine/logic 140), vehicle occupants will not be disturbed as the generated ultrasonic signals are highly directional and are only detectable by the microphone(s) 106/108. Later the audio test patterns detected by the microphones are converted into digital signals (e.g., by ADC logic 110/112) for further audio processing and communicated to SOC 130 through the audio communication channel 116.
In one or more embodiments, the audio channel 116 may provide a communication channel between the CODEC 118 and SOC 130 (and the audio processing unit(s) 114) via an I2S (Inter IC Sound) interface (which is a serial communication bus), SoundWire® interface (introduced in 2014 by the MIPI Alliance), Slimbus™ interface (where Slimbus stands for Serial low-power inter-chip media bus, which was developed by the MIPI Alliance, starting in 2007), or any other audio Input/Output (IO or I/O) interface. Whenever there is mismatch in the received test pattern (e.g., as detected by the audio processing unit(s) 114) with the transmitted pattern (e.g., due to ambient or other extraneous factors), the audio processing unit(s) apply feedforward correction to the CODEC 118. This correction code could, for example, change CODEC DAC configuration, equalization Configurations, or PA Gain related configurations. This continuous audio loop back system provides a secure audio system for functional safety applications.
During test mode, the microphone and the corresponding power amplifier for the PAA transducers are switched-on, while disabling the power amplifier directed towards (and intended to be heard by) the end-user. When the audio alert message is intended for the end-user to hear, both microphone and consumer intended transducers can be switched-on to ensure the consumer has successfully received the alert message, while the feedback loop verifies the alert message is heard by the user.
In an embodiment, the test path (using the PAA transducers and corresponding microphone(s)) can be used for continuous monitoring and feedforward correction to avoid distortion of the signal that is being transmitted. In alert message mode, both consumer and microphone receive the signals and the transmitted message is verified against the received message. Alert message path can also be used for verification and fine-tuning for any signal distortions in one embodiment. As discussed, a “consumer” or an “end-user” generally refer to a vehicle occupant or operator/driver.
As shown in
In one embodiment, logic and/or various components discussed with reference to
As illustrated in
The I/O interface 540 may be coupled to one or more I/O devices 570, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s) 570 may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch screen, a speaker, or the like.
An embodiment of system 600 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system 600 is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system 600 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system 600 is a television or set top box device having one or more processors 602 and a graphical interface generated by one or more graphics processors 608.
In some embodiments, the one or more processors 602 each include one or more processor cores 607 to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 607 is configured to process a specific instruction set 609. In some embodiments, instruction set 609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores 607 may each process a different instruction set 609, which may include instructions to facilitate the emulation of other instruction sets. Processor core 607 may also include other processing devices, such a Digital Signal Processor (DSP).
In some embodiments, the processor 602 includes cache memory 604. Depending on the architecture, the processor 602 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 602. In some embodiments, the processor 602 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 607 using known cache coherency techniques. A register file 606 is additionally included in processor 602 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 602.
In some embodiments, processor 602 is coupled to a processor bus 610 to transmit communication signals such as address, data, or control signals between processor 602 and other components in system 600. In one embodiment the system 600 uses an exemplary ‘hub’ system architecture, including a memory controller hub 616 and an Input Output (I/O) controller hub 630. A memory controller hub 616 facilitates communication between a memory device and other components of system 600, while an I/O Controller Hub (ICH) 630 provides connections to I/O devices via a local I/O bus. In one embodiment, the logic of the memory controller hub 616 is integrated within the processor.
Memory device 620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 620 can operate as system memory for the system 600, to store data 622 and instructions 621 for use when the one or more processors 602 executes an application or process. Memory controller hub 616 also couples with an optional external graphics processor 612, which may communicate with the one or more graphics processors 608 in processors 602 to perform graphics and media operations.
In some embodiments, ICH 630 enables peripherals to connect to memory device 620 and processor 602 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 646, a firmware interface 628, a wireless transceiver 626 (e.g., Wi-Fi, Bluetooth), a data storage device 624 (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller 640 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. One or more Universal Serial Bus (USB) controllers 642 connect input devices, such as keyboard and mouse 644 combinations. A network controller 634 may also couple to ICH 630. In some embodiments, a high-performance network controller (not shown) couples to processor bus 610. It will be appreciated that the system 600 shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, the I/O controller hub 630 may be integrated within the one or more processor 602, or the memory controller hub 616 and I/O controller hub 630 may be integrated into a discreet external graphics processor, such as the external graphics processor 612.
The internal cache units 704A to 704N and shared cache units 706 represent a cache memory hierarchy within the processor 700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 706 and 704A to 704N.
In some embodiments, processor 700 may also include a set of one or more bus controller units 716 and a system agent core 710. The one or more bus controller units 716 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). System agent core 710 provides management functionality for the various processor components. In some embodiments, system agent core 710 includes one or more integrated memory controllers 714 to manage access to various external memory devices (not shown).
In some embodiments, one or more of the processor cores 702A to 702N include support for simultaneous multi-threading. In such embodiment, the system agent core 710 includes components for coordinating and operating cores 702A to 702N during multi-threaded processing. System agent core 710 may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 702A to 702N and graphics processor 708.
In some embodiments, processor 700 additionally includes graphics processor 708 to execute graphics processing operations. In some embodiments, the graphics processor 708 couples with the set of shared cache units 706, and the system agent core 710, including the one or more integrated memory controllers 714. In some embodiments, a display controller 711 is coupled with the graphics processor 708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 711 may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 708 or system agent core 710.
In some embodiments, a ring based interconnect unit 712 is used to couple the internal components of the processor 700. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor 708 couples with the ring interconnect 712 via an I/O link 713.
The exemplary I/O link 713 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 718, such as an eDRAM (or embedded DRAM) module. In some embodiments, each of the processor cores 702 to 702N and graphics processor 708 use embedded memory modules 718 as a shared Last Level Cache.
In some embodiments, processor cores 702A to 702N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 702A to 702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 702A to 702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores 702A to 702N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor 700 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.
In some embodiments, graphics processor 800 also includes a display controller 802 to drive display output data to a display device 820. Display controller 802 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In some embodiments, graphics processor 800 includes a video codec engine 806 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.
In some embodiments, graphics processor 800 includes a block image transfer (BLIT) engine 804 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 8D graphics operations are performed using one or more components of graphics processing engine (GPE) 810. In some embodiments, graphics processing engine 810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.
In some embodiments, GPE 810 includes a 3D pipeline 812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 812 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 815. While 3D pipeline 812 can be used to perform media operations, an embodiment of GPE 810 also includes a media pipeline 816 that is specifically used to perform media operations, such as video post-processing and image enhancement.
In some embodiments, media pipeline 816 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 806. In some embodiments, media pipeline 816 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 815. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system 815.
In some embodiments, 3D/Media subsystem 815 includes logic for executing threads spawned by 3D pipeline 812 and media pipeline 816. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem 815, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem 815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.
The following examples pertain to further embodiments. Example 1 includes an apparatus comprising: safety island logic circuitry to transmit an enable signal to cause initiation of a functional safety test for an audio component in a vehicle; and audio processing logic circuitry to receive the enable signal and cause activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal, wherein the audio component comprises a Parametric Acoustic Array (PAA) transducer. Example 2 includes the apparatus of example 1, wherein the PAA transducer is to generate ultrasonic signals, wherein the ultrasonic signals are undetectable by an occupant of the vehicle. Example 3 includes the apparatus of example 1, wherein the safety island logic circuitry is to generate the audio alert test signal. Example 4 includes the apparatus of example 1, wherein the enable signal is to cause activation of the power amplifier logic circuitry and the audio component. Example 5 includes the apparatus of example 1, comprising one or more microphones to detect an audio signal to be generated by the audio component in response to the audio alert test signal. Example 6 includes the apparatus of example 1, wherein a coder-decoder logic is to comprise the power amplifier logic circuitry, an analog-to-digital converter logic, coupled to receive an audio signal from a microphone, and a digital-to-analog converter logic to transmit a signal to the power amplifier logic circuitry to cause the power amplifier logic circuitry to drive the audio component. Example 7 includes the apparatus of example 6, wherein the audio processing logic circuitry is to transmit correction command to the coder-decoder logic in response to a determination that an error exists based on comparison of an audio signal to be generated by the audio component in response to the audio alert test signal and the audio alert test signal. Example 8 includes the apparatus of example 6, comprising an input/output interface coupled between the coder-decoder logic and the audio processing logic circuitry. Example 9 includes the apparatus of example 8, wherein the input/output interface comprises one or more of: an I2S (Inter IC Sound) interface, a SoundWire® interface, or a Slimbus™ interface. Example 10 includes the apparatus of example 1, wherein the audio processing logic circuitry is to determine whether an error exists based on comparison of an audio signal to be generated by the audio component in response to the audio alert test signal and the audio alert test signal. Example 11 includes the apparatus of example 1, wherein the audio processing logic circuitry is to transmit an error signal to the safety island logic circuitry in response to a determination that an error exists based on comparison of an audio signal to be generated by the audio component in response to the 7audio alert test signal and the audio alert test signal. Example 12 includes the apparatus of example 1, wherein the audio component further comprises an omnidirectional transducer. Example 13 includes the apparatus of example 1, wherein a System On Chip (SOC) device comprises the safety island logic circuitry and the audio processing logic circuitry, wherein the audio processing logic circuitry is coupled to the power amplifier logic circuitry via an input/output bus or a system bus. Example 14 includes the apparatus of example 1, wherein an Internet of Things (IoT) device comprise one or more of: the safety island logic circuitry, the power amplifier logic circuitry, the audio component, the audio processing logic circuitry, and memory. Example 15 includes the apparatus of example 1, wherein a single integrated device comprises one or more of: a processor, the safety island logic circuitry, the audio processing logic circuitry, and memory. Example 16 includes the apparatus of example 1, wherein the vehicle comprises one or more of: an automobile, a truck, a motorcycle, an airplane, a helicopter, a vessel or ship, a train, or a drone.
Example 17 includes one or more computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to cause: safety island logic to transmit an enable signal to cause initiation of a functional safety test for an audio component in a vehicle; and audio processing logic to receive the enable signal and cause activation of power amplifier logic, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal, wherein the audio component comprises a Parametric Acoustic Array (PAA) transducer. Example 18 includes the one or more computer-readable medium of example 17, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to the PAA transducer to generate ultrasonic signals, wherein the ultrasonic signals are undetectable by an occupant of the vehicle. Example 19 includes the one or more computer-readable medium of example 17, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the safety island logic to generate the audio alert test signal. Example 20 includes the one or more computer-readable medium of example 17, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause activation of the power amplifier logic circuitry and the audio component in response to the enable signal.
Example 21 includes an apparatus comprising means to perform a method as set forth in any preceding example. Example 22 includes machine-readable storage including machine-readable instructions, when executed, to implement a method or realize an apparatus as set forth in any preceding example.
In various embodiments, the operations discussed herein, e.g., with reference to
Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals provided in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, and/or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
Thus, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.
