The present disclosure is generally related to mobile communications and, more particularly, to further enhancements in discontinuous reception (DRX) operation for extended reality (XR) and cloud gaming in mobile communications.
Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.
In wireless communications, such as mobile communications under the 3rd Generation Partnership Project (3GPP) specification(s) for 5th Generation (5G) New Radio (NR), applications and services with strict latency and high bandwidth requirements, such as XR applications and cloud gaming, are emerging and becoming more prevalent. However, there remain some issues that need to be addressed. One issue pertains to the DRX cycle mismatch with a quasi-periodic XR traffic. This is because legacy DRX cycle values do not match the periodicity (or quasi-periodicity) of typical XR traffic. Over time, the difference could build up and the DRX on-duration (herein interchangeably referred to as “On-Duration”) could be completely outside of (e.g., out of synchronization with) a jitter period. Another issue pertains to jitter for XR traffic/cloud gaming as the jitter can be large (e.g., [−4, +4] milliseconds) for XR and cloud gaming traffic. Even assuming the DRX cycle mismatch issue is resolved, covering the entire jitter period with On-Duration could have a large impact on the power consumption of a user equipment (UE). On the other hand, in case that the On-Duration is smaller than the jitter, some downlink (DL) data might be delayed until a next on-duration. Therefore, there is a need for a solution of further enhancements in DRX operation for XR and cloud gaming in mobile communications.
The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.
An objective of the present disclosure is to propose solutions or schemes that address the issue(s) described herein. More specifically, various schemes proposed in the present disclosure are believed to provide solutions involving further enhancements in DRX operation for XR and cloud gaming in mobile communications. It is believed that, under the various proposed schemes, aforementioned issues related to DRX cycle mismatch and jitter for XR traffic/cloud gaming may be avoided, reduced or otherwise alleviated.
In one aspect, a method may involve a UE entering a DRX mode in wireless communications. The method may also involve the UE controlling at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
In another aspect, an apparatus implementable in a UE may include a transceiver configured to communicate wirelessly and a processor coupled to the transceiver. The processor may enter the UE into a DRX mode in wireless communications. The processor may also control at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as 5G/NR mobile communications, the proposed concepts, schemes and any variation(s)/derivative(s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies such as, for example and without limitation, Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet-of-Things (IoT), Narrow Band Internet of Things (NB-IoT), Industrial Internet of Things (IIoT), vehicle-to-everything (V2X), and non-terrestrial network (NTN) communications. Thus, the scope of the present disclosure is not limited to the examples described herein.
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation in order to clearly illustrate the concept of the present disclosure.
Detailed embodiments and implementations of the claimed subject matters are disclosed herein. However, it shall be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matters which may be embodied in various forms. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that description of the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. In the description below, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.
Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and/or solutions pertaining to further enhancements in DRX operation for XR and cloud gaming in mobile communications in mobile communications. According to the present disclosure, a number of possible solutions may be implemented separately or jointly. That is, although these possible solutions may be described below separately, two or more of these possible solutions may be implemented in one combination or another.
Referring to
Each of apparatus 910 and apparatus 920 may be a part of an electronic apparatus, which may be a network apparatus or a UE (e.g., UE 110), such as a portable or mobile apparatus, a wearable apparatus, a vehicular device or a vehicle, a wireless communication apparatus or a computing apparatus. For instance, each of apparatus 910 and apparatus 920 may be implemented in a smartphone, a smart watch, a personal digital assistant, an electronic control unit (ECU) in a vehicle, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. Each of apparatus 910 and apparatus 920 may also be a part of a machine type apparatus, which may be an IoT apparatus such as an immobile or a stationary apparatus, a home apparatus, a roadside unit (RSU), a wire communication apparatus or a computing apparatus. For instance, each of apparatus 910 and apparatus 920 may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. When implemented in or as a network apparatus, apparatus 910 and/or apparatus 920 may be implemented in an eNodeB in an LTE, LTE-Advanced or LTE-Advanced Pro network or in a gNB or TRP in a 5G network, an NR network or an IoT network. In some implementations, each of apparatus 910 and apparatus 920 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, one or more complex-instruction-set-computing (CISC) processors, or one or more reduced-instruction-set-computing (RISC) processors. In the various schemes described above, each of apparatus 910 and apparatus 920 may be implemented in or as a network apparatus or a UE. Each of apparatus 910 and apparatus 920 may include at least some of those components shown in
In one aspect, each of processor 912 and processor 922 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC or RISC processors. That is, even though a singular term “a processor” is used herein to refer to processor 912 and processor 922, each of processor 912 and processor 922 may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, each of processor 912 and processor 922 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, each of processor 912 and processor 922 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including those pertaining to further enhancements in DRX operation for XR and cloud gaming in mobile communications in accordance with various implementations of the present disclosure.
In some implementations, apparatus 910 may also include a transceiver 916 coupled to processor 912. Transceiver 916 may be capable of wirelessly transmitting and receiving data. In some implementations, transceiver 916 may be capable of wirelessly communicating with different types of wireless networks of different radio access technologies (RATs). In some implementations, transceiver 916 may be equipped with a plurality of antenna ports (not shown) such as, for example, four antenna ports. That is, transceiver 916 may be equipped with multiple transmit antennas and multiple receive antennas for multiple-input multiple-output (MIMO) wireless communications. In some implementations, apparatus 920 may also include a transceiver 926 coupled to processor 922. Transceiver 926 may include a transceiver capable of wirelessly transmitting and receiving data. In some implementations, transceiver 926 may be capable of wirelessly communicating with different types of UEs/wireless networks of different RATs. In some implementations, transceiver 926 may be equipped with a plurality of antenna ports (not shown) such as, for example, four antenna ports. That is, transceiver 926 may be equipped with multiple transmit antennas and multiple receive antennas for MIMO wireless communications.
In some implementations, apparatus 910 may further include a memory 914 coupled to processor 912 and capable of being accessed by processor 912 and storing data therein. In some implementations, apparatus 920 may further include a memory 924 coupled to processor 922 and capable of being accessed by processor 922 and storing data therein. Each of memory 914 and memory 924 may include a type of random-access memory (RAM) such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM). Alternatively, or additionally, each of memory 914 and memory 924 may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM). Alternatively, or additionally, each of memory 914 and memory 924 may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and/or phase-change memory.
Each of apparatus 910 and apparatus 920 may be a communication entity capable of communicating with each other using various proposed schemes in accordance with the present disclosure. For illustrative purposes and without limitation, a description of capabilities of apparatus 910, as a UE (e.g., UE 110), and apparatus 920, as a network node (e.g., network node 125 or another network node implementing one or more network-side functionalities described above) of an application server side network (e.g., network 130 as a 5G/NR mobile network), is provided below.
Under various proposed schemes in accordance with the present disclosure pertaining to further enhancements in DRX operation for XR and cloud gaming in mobile communications, processor 912 of apparatus 910, implemented in or as a UE (e.g., UE 110) may enter a DRX mode in wireless communications. Moreover, processor 912 may control, via transceiver 916, at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
In some implementations, in controlling the at least one timer, processor 912 may stop an on-duration timer responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH; or (3) a DRX inactivity timer being started.
In some implementations, responsive to the PDCCH for the new UL or DL transmission having been received or the new UL or DL transmission having been received or performed, in controlling the at least one timer, processor 912 may start a secondary on-duration timer after stopping the on-duration timer. In some implementations, the secondary on-duration timer may have a smaller value or duration than that of the on-duration timer. Moreover, in starting the secondary on-duration timer, processor 912 may start the secondary on-duration timer for a first PDCCH or data arriving during a DRX on-duration. Additionally, processor 912 may monitor the PDCCH when the secondary on-duration timer is running.
In some implementations, in controlling the at least one on-duration occasion, processor 912 may skip one or more on-duration occasions in a current group of on-duration occasions responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH; or (3) a DRX inactivity timer being started. In some implementations, in controlling the at least one on-duration occasion, processor 912 may keep an on-duration timer for a current on-duration occasion in the current group of on-duration occasions running. In some implementations, in controlling the at least one on-duration occasion, processor 912 may also stop an on-duration timer for a current on-duration occasion in the current group of on-duration occasions. Moreover, in controlling the at least one on-duration occasion, processor 912 may keep one or more other on-duration occasions in the current group of on-duration occasions active.
In some implementations, a plurality of on-duration occasions in a current group of on-duration occasions may be distributed in an asymmetric pattern in time.
In some implementations, in controlling the at least one on-duration occasion, processor 912 may perform certain operations. For instance, processor 912 may utilize a short DRX cycle between two or more on-duration occasions in a first group of on-duration occasions. Moreover, processor 912 may utilize a long DRX cycle between the first group of on-duration occasions and a second group of on-duration occasions.
In some implementations, in controlling the at least one on-duration occasion, processor 912 may switch from a short DRX cycle to a long DRX cycle responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH.
In some implementations, in controlling, processor 912 may perform certain operations. For instance, processor 912 may receive a DCI indicating a specific type of traffic. Additionally, processor 912 may control the at least one timer or the at least one on-duration occasion responsive to receiving the DCI. In some implementations, a field in the DCI may indicate the specific type of traffic being a traffic for XR or cloud gaming.
In some implementations, in controlling, processor 912 may switch between sparse PDCCH monitoring and dense PDCCH monitoring based on a condition. In some implementations, the condition may include any one of the following: (1) a UE being in Active Time; (2) in case of a DRX on-duration timer running; or (3) in case of a DRX inactivity timer running.
At 1010, process 1000 may involve processor 912 of apparatus 910, implemented in or as a UE (e.g., UE 110) entering a DRX mode in wireless communications. Process 1000 may proceed from 1010 to 1020.
At 1020, process 1000 may involve processor 912 controlling, via transceiver 916, at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
In some implementations, in controlling the at least one timer, process 1000 may involve processor 912 stopping an on-duration timer responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH; or (3) a DRX inactivity timer being started.
In some implementations, responsive to the PDCCH for the new UL or DL transmission having been received or the new UL or DL transmission having been received or performed, in controlling the at least one timer, process 1000 may also involve processor 912 starting a secondary on-duration timer after stopping the on-duration timer. In some implementations, the secondary on-duration timer may have a smaller value or duration than that of the on-duration timer. Moreover, in starting the secondary on-duration timer, process 1000 may involve processor 912 starting the secondary on-duration timer for a first PDCCH or data arriving during a DRX on-duration. Additionally, process 1000 may also involve processor 912 monitoring the PDCCH when the secondary on-duration timer is running.
In some implementations, in controlling, process 1000 may involve processor 912 performing certain operations. For instance, process 1000 may involve processor 912 receiving a DCI indicating a specific type of traffic. Additionally, process 1000 may involve processor 912 controlling the at least one timer or the at least one on-duration occasion responsive to receiving the DCI. In some implementations, a field in the DCI may indicate the specific type of traffic being a traffic for XR or cloud gaming.
At 1110, process 1100 may involve processor 912 of apparatus 910, implemented in or as a UE (e.g., UE 110) entering a DRX mode in wireless communications. Process 1100 may proceed from 1110 to 1120.
At 1120, process 1100 may involve processor 912 controlling, via transceiver 916, at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
In some implementations, in controlling the at least one on-duration occasion, process 1100 may involve processor 912 skipping one or more on-duration occasions in a current group of on-duration occasions responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH; or (3) a DRX inactivity timer being started.
In some implementations, in controlling the at least one on-duration occasion, process 1100 may also involve processor 912 keeping an on-duration timer for a current on-duration occasion in the current group of on-duration occasions running. In some implementations, in controlling the at least one on-duration occasion, process 1100 may further involve processor 912 stopping an on-duration timer for a current on-duration occasion in the current group of on-duration occasions. Moreover, in controlling the at least one on-duration occasion, process 1100 may further involve processor 912 keeping one or more other on-duration occasions in the current group of on-duration occasions active.
In some implementations, a plurality of on-duration occasions in a current group of on-duration occasions may be distributed in an asymmetric pattern in time.
In some implementations, in controlling the at least one on-duration occasion, process 1100 may involve processor 912 performing certain operations. For instance, process 1100 may involve processor 912 utilizing a short DRX cycle between two or more on-duration occasions in a first group of on-duration occasions. Moreover, process 1100 may involve processor 912 utilizing a long DRX cycle between the first group of on-duration occasions and a second group of on-duration occasions.
In some implementations, in controlling the at least one on-duration occasion, process 1100 may involve processor 912 switching from a short DRX cycle to a long DRX cycle responsive to a condition being met. In some implementations, the condition may include any one of the following: (1) a PDCCH being received and indicating a new UL transmission or a new DL transmission; or (2) the new DL transmission being received on a PDSCH or the new UL transmission being performed on a PUSCH.
At 1210, process 1200 may involve processor 912 of apparatus 910, implemented in or as a UE (e.g., UE 110) entering a DRX mode in wireless communications. Process 1200 may proceed from 1210 to 1220.
At 1220, process 1200 may involve processor 912 controlling, via transceiver 916, at least one timer or at least one on-duration occasion to reduce DRX cycle mismatch or UE power consumption due to jitter when in the DRX mode.
In some implementations, in controlling, process 1200 may involve processor 912 switching between sparse PDCCH monitoring and dense PDCCH monitoring based on a condition. In some implementations, the condition may include any one of the following: (1) a UE being in Active Time; (2) in case of a DRX on-duration timer running; or (3) in case of a DRX inactivity timer running.
The herein-described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.
Further, with respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.
Moreover, it will be understood by those skilled in the art that, in general, terms used herein, and especially in the appended claims, e.g., bodies of the appended claims, are generally intended as “open” terms, e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc. It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an,” e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more;” the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number, e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”
From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
The present disclosure is part of a non-provisional application claiming the priority benefit of U.S. Patent Application No. 63/335,746, filed 28 Apr. 2022, the content of which herein being incorporated by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/089643 | 4/21/2023 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63335746 | Apr 2022 | US |