NSF Award
2425331
Energy use for computing is ever-increasing, particularly with the growth of artificial intelligence (AI) and machine learning. Modern AI requires large datacenters that house thousands of specialized computers that are used to train AI models and generate responses to queries. These datacenters require huge amounts of electricity, and they generate so much heat that extensive cooling systems are needed to prevent the computers from overheating. Networks of datacenters already exist to support the cloud-based computing that the world has come to rely on for everything from communication to banking to transportation infrastructure. However, the growth of AI will dramatically increase the need for such datacenters. According to a 2024 report from the International Energy Agency, an AI-enabled ChatGPT query uses almost ten times more energy than a standard Google search. Furthermore, the report predicts exponential growth in the AI industry, increasing AI’s electricity demand by at least 10x from 2023 to 2026. This research project will investigate ways to fundamentally redesign the computing systems that support AI, from the semiconductor materials and devices to the computing circuits and architectures. The project aims to improve the energy efficiency of these systems by orders of magnitude. Such dramatic reductions in the energy demand for AI would positively impact society by reducing the strain on the electricity grid and mitigating the impacts of AI on climate change. Furthermore, this project supports an Education and Workforce Development plan that is a collaboration with community colleges and the Micro Nano Technology Education Center, an NSF Advanced Technology Education Center dedicated to increasing the semiconductor workforce. <br/><br/><br/>In this project, a team of investigators will pursue interdisciplinary research encompassing materials, devices, circuits, and architecture co-designs to improve the energy efficiency of AI and machine learning computing hardware. Most of the computing resources for machine learning algorithms are used by multiply-and-accumulate (MAC). The regularity and parallelism of MACs make them very suitable for hardware acceleration. However, conventional random-access memory requires row-by-row accesses, and fetching billions of weights in this manner consumes substantial energy. One solution to this bottleneck is eliminating the row-by-row memory access by designing hardware systems where the computing occurs inside the memory, referred to as “in-memory computing”. In-memory computing is achieved by inserting a small computing circuit in each memory cell. A promising new memory element, the “memcapacitor,” has been proposed for this purpose, but few devices have been experimentally demonstrated. The technical aims of this project can be broken into three major areas: 1) Create a vertical memcapacitor device that can be fabricated in the backend of the CMOS process for monolithic 3D integration; 2) Create memcapacitor-based in-memory computing circuits; and 3) Create a deep neural network accelerator with fully analog-datapath and digital-control.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
