FuSe2 Topic 2: Heterogeneous 3D Integration of Energy-Efficient Electronics (H3E3) with Low-Dimensional Device Layers

Information

  • NSF Award
  • 2425218
Owner
  • Award Id
    2425218
  • Award Effective Date
    9/1/2024 - 11 months ago
  • Award Expiration Date
    8/31/2027 - 2 years from now
  • Award Amount
    $ 612,712.00
  • Award Instrument
    Continuing Grant

FuSe2 Topic 2: Heterogeneous 3D Integration of Energy-Efficient Electronics (H3E3) with Low-Dimensional Device Layers

For six decades, the semiconductor industry has relied on reducing the sizes of transistors, memory, and wires from microns to nanometers. The conventional approach of “cramming more components” onto the same chip area, leading to greater functionality and lower cost per function over time, is approaching its physical limits. However, a seismic shift in the future of semiconductors can be enabled by building three-dimensional (3D) integrated circuits (ICs) with much higher density than have been possible through conventional, lateral scaling. <br/><br/>This project will develop the fundamental steps necessary to accomplish such a vision through an inter-disciplinary approach from nanomaterials to systems, in a manner that will accelerate their lab-to-fab translation. The project will pursue the integration of atomically thin materials (e.g. one- and two-dimensional semiconductors like carbon nanotubes and MoS2) into individual circuit layers, which will then be stacked in 3D to achieve high-density circuits. The research will also advance the materials science and reliability of 3D integration, areas of inquiry that have received limited attention to date. The 3D integrated circuits which this research could enable, are expected to be much more energy-efficient (over 50x) than today’s technology due to the tight integration of logic and memory, with potentially massive impact from low-power wearables to large energy-hungry data centers. This project will also educate the future US semiconductor workforce in a unique way with much broader exposure (from materials-to-systems) than a traditional education which “silos” the various components (e.g. materials vs. circuits). The team will build on a strong track record of mentoring women and underrepresented minorities, who have gone into the semiconductor industry, and their educational efforts will be scaled up through online learning. These efforts could have a large societal impact, as contributions to US semiconductors are seen as major growth opportunities for industry, as important for our quality of life, and as critical to our economy and national security.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

  • Program Officer
    Sumanta Acharyasacharya@nsf.gov7032924509
  • Min Amd Letter Date
    8/15/2024 - 12 months ago
  • Max Amd Letter Date
    8/15/2024 - 12 months ago
  • ARRA Amount

Institutions

  • Name
    Stanford University
  • City
    STANFORD
  • State
    CA
  • Country
    United States
  • Address
    450 JANE STANFORD WAY
  • Postal Code
    943052004
  • Phone Number
    6507232300

Investigators

  • First Name
    Eric
  • Last Name
    Pop
  • Email Address
    epop@stanford.edu
  • Start Date
    8/15/2024 12:00:00 AM
  • First Name
    Tony
  • Last Name
    Heinz
  • Email Address
    tony.heinz@stanford.edu
  • Start Date
    8/15/2024 12:00:00 AM
  • First Name
    Andrew
  • Last Name
    Mannix
  • Email Address
    ajmannix@stanford.edu
  • Start Date
    8/15/2024 12:00:00 AM
  • First Name
    Tathagata
  • Last Name
    Srimani
  • Email Address
    tsrimani@andrew.cmu.edu
  • Start Date
    8/15/2024 12:00:00 AM

Program Element

  • Text
    NSF-Intel Semiconductr Partnrs

Program Reference

  • Text
    Microelectronics and Semiconductors