Radio frequency up-converters typically convert lower frequency signals, such as quadrature I and Q baseband signals to higher frequencies, such as microwave frequencies. One such up-converter is disclosed in U.S. patent application Ser. No. 14/258,634. It can become difficult to reach a desired gain through the up-converter. The load after mixing, shown as 101 in FIG. 1, at the output of the up-converter relative to the baseband input determines the up-converter gain.
Typically, two ways to change the gain in a transconductance (Gm) gain amplifier exist. One can increase the load resistance for a fixed input Gm gain stage. Alternatively, one can increase the transconductance of the baseband input stage. These should occur while taking into account that the inputs to the transconductance stage will typically match a source impedance, typically 50 ohms single ended or 100 ohms differential.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a prior art embodiment of a gain boosted differential transconductance amplifier.
FIG. 2 shows an alternative embodiment of a gain boosted transconductance amplifier.
FIG. 3 shows an embodiment of a gain boosted differential transconductance amplifier.
FIG. 4 shows a graph of gain versus input current for a test embodiment.
FIG. 5 show a graph of a differential voltage swing at an output for a test embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
FIG. 1 shows a prior art transconductance (Gm) amplifier for a baseband interface to an up-converter. The mixer 101 can also be replaced by cascode transistors followed by load resistors. The load resistors convert the current generated by the Gm stage back into a voltage to generate gain. FIG. 1 shows one example of an interface from a typical Digital to Analog Converter (DAC) to the input of the Gm amplifier stage. Resistors R1 and R2 set the input common-mode voltage and together with R6 determine the input signal swing VIP and VIM. Typically a Low Pass Filter (LPF) is inserted between the DAC and the amplifier inputs. In the following discussion, resistor names will be numbered and their values will be letters. Typical values for RS and RTERM are 50Ω and 100Ω respectively, while RE and RBE might be 20Ω and 10Ω respectively. Nodes VEP and VEN will be approximately equal to the bias voltages on the inputs VIP and VIM as will be explained below.
Normally an input match to a differential source of 100Ω, 50Ω per side, creates a broadband match and then one needs to add a 100Ω termination resistor (RTERM) across the input to satisfy the input match. Many applications have a further constraint to process signals down to DC in the case of baseband signals that have very low frequency content.
FIG. 2 shows an embodiment in which RTERM has been replaced by resistors R7 and R8 with value RFF. These resistors connect from the PNP level shifter base inputs to the emitters of the resistively degenerated NPN differential pair and implement the input match and at the same increase the gain of the Gm stage compared to the one in FIG. 1. To the first order there is unity gain from the base of the PNP transistors Q1 and Q2 to their respective emitters because the transistors are biased by high impedance current sources. This causes the entire input signal to show up at the bases of the NPN transistors, Q3 and Q4. The PNP transistors act as emitter followers. The term ‘degenerated’ as used here means that there is an element in the emitter/source of a transistor, to increase its linearity.
In addition, each of the NPNs Q3 and Q4 acts as unity-gain followers. The gain to their emitters from their respective bases is RE/(RE+re), which in the limit will go to ‘1’ as ‘re’=1/gm becomes much smaller than the degeneration resistors RE, in this embodiment R3 and R4. RE might be 20Ω in a typical application. Since the same bias current flows through ‘RE’ and ‘re’, the voltage drop across RE is relative to VT=kT/q and determines how close to ‘1’ the follower gain is. The larger the voltage drop across RE can be the better, however, due to bias and headroom constraints one cannot arbitrarily increase the voltage drop across RE. If the bias current in transistors Q3 and Q4 is 12.5 mA, then 1/gm=re=2Ω. For these values, the NPN follower gain is 20/(20+2)=0.909. One should note that if RE and RBE are equal to 20Ω and 10Ω respectively, and an input common-mode voltage equals 0.5 V, the bias currents through transistors Q3 and Q4 will be close to 12.5 mA.
Because the input signal can be ground referenced when driven from a current DAC, and the DAC output constraints will set the voltages needed, one cannot arbitrarily set the voltage drop across RE. For example, in the example used the DAC input 50Ω will result in the voltage being set at 0.5V for maximum swing. For a typical DAC with 0-20 mA of output current per side, this will result in a maximum differential swing of 0.25 to 0.75 V per side. This in turn sets the voltage across resistor R5 (RBE), for the example values above it is at 0.25 V.
Furthermore, for linearity reasons the voltage drop across R3 and R4 (RE) should also be about 0.25 V. The only variable left is the bias current through transistors Q3 and Q4 as that sets ‘re’=1/gm=VT/IC and its maximum will be constrained by power dissipation and transistor performance. As the load resistance in a typical RF amplifier most likely is also constrained for output matching reasons, typically 50Ω, and similar headroom constraints appear as at the input due to bias current and the desired signal swing, or output power, then the achievable gain is within a narrow range for a given supply voltage.
Often there is a need for more gain yet the typical embodiment in FIG. 1 does not allow more gain to be achieved. The embodiment in FIG. 2 is one way of achieving up to 6 dB more gain without changing the biasing, while simultaneously achieving the desired input match. In the embodiments of FIG. 2, the 100 Ohm resistors R7 and R8 are cross-connected. Since the inputs I+ and I− are driven differentially from a DAC, the emitter voltage (VEN) of the right NPN Q4 will be to first order equal to VIM, the voltage at the negative input. VIP=Vin/2 while VIM=−Vin/2 so that the current across resistor R7 (RFF) will be approximately Vin/RFF. The left side with NPN Q3, emitter voltage (VEP), and R8 is analogous and a minor image of the description above.
FIG. 3 shows an embodiment of a complete circuit as it might be implemented in an amplifier. Typically, in FIG. 1, RTERM=2*RS to match to the source resistors R1 and R2 with value RS. This parameter may also be used in the embodiments of FIG. 3. The two RE resistors R3 and R4, the current source 2*IE and the corresponding ‘re’=1/gm of the NPNs Q3 and Q4 make up a resistively degenerated transconductance differential pair. If RE is much larger than the ‘re’=VT/IC=1/gm, then to the first order the resistors having value RE, R3 and R4, together with load resistors having value RL, R9 and R10, set the gain of the amplifier stage. The desired linearity of this stage is primarily set by how large the voltage drop is across RE vs. VT=kT/q of the NPN transistors Q3 and Q4, a good starting point is about 10*VT=approx. 250 mV at 27° C.
The output power, also referred to as the signal swing that needs to be delivered to a load, together with a good output match will set the value for RL together with VPOS minus the voltage at the CASC node. The output match may also be referred to as the output reflection coefficient (S22) in a 2-port system, which is what most amplifiers are. The input port is the first port and the output port is the second port. A match is often referred to as S22 for a load match; while S11 is the input reflection coefficient (input match). Once RL has been thus determined, the gain will be set by RL/(RE+re) ignoring secondary losses. This will also force the value of the bias current (2*IE) due to the linearity constraint and the load power that needs to be delivered.
The above design restrictions typically force all the values and thereby the gain of this stage. One would often like to be able to adjust gain independently of signal power and linearity, the embodiments described in this disclosure provides this extra degree of freedom by taking advantage of the input match as an additional variable that allows the gain to be increased.
The PNP level shifters may act as simple gain-of-one followers. Furthermore, the NPNs may act in the same manner. In this case the voltage gain from nodes VIP to VEP in FIG. 3 should be approximately one, the same is true for the negative input VIM to VEN. If this circuit is driven differentially, as will more than likely be the case in an actual application where the signal source is a DAC as indicated in FIGS. 1 and 3, then one could cross-connect two resistors of value RFF from the positive input VIP to the negative emitter VEN. The reverse is also true. This provides the extra degree of freedom to increase the gain of the Gm stage, making this a boosted Gm amplifier stage.
In the usual case that an input match is desired, RFF needs to be equal to 2*RS, where RS is the source resistance value per side, R1 and R2, in FIG. 3. The input resistance per side as seen looking towards the amplifier will then be:
Note that the resistance as seen looking back from node EN to IP is also equal to RS. Furthermore, due to symmetry, the input resistance on the negative side, IM, is also RS when
R
FF=2*RS.
The gain is increased by the additional signal current IIN that is injected or removed into the nodes EN and EP via resistors RFF. This reduces or increases the emitter currents, and thereby collector currents of Q3 and Q4 when compared to FIG. 1, and thereby also the currents into the load resistors R9 and R10. The increase in gain is dependent on the value of RE relative to the effective resistance as seen from nodes EP and EN back towards the input. In the case of RFF=2*RS, the effective resistance is RS. The increase in gain compared to FIG. 1 is then:
From this it can be observed that for a value of RE=RS, the maximum increase in gain is a factor-of-two (6 dB). For smaller values of RE relative to RS, the increase is correspondingly smaller. Furthermore, it is important to note that the equations above only hold while there is enough bias current in the NPN differential pair. At the extremities when the input signal becomes large relative to the signal handling capability of the Gm stage, the input match and gain will deviate from the equations shown.
The simulation result in FIG. 4 shows comparisons for various values of RE relative to RS. For RE=RS, both boosted and un-boosted stages are fairly linear over the input current sweep of −1 to +1 mA. Note that in the embodiment used, the design is scaled to 1/10th from a typical DAC with 0 to 20 mA output current down to 0 to 2 mA but this is not a limitation and was only done for convenience. IBias−DAC=1 mA in the simulation such that the input current is from 0 to 2 mA per each side, with positive and negative inputs. However, the gain of the boosted stage is 6 dB higher in the middle of the range. One should note that the max signal handling capability of the boosted stage is reduced, the gain starts to “droop” beyond about ±0.8 mA, which has to do with the fact that the max input signal handling capability of the Gm stages are set by the voltage drop across RE=RE*IE, the smaller that number relative to VT, the lower the linear input range.
The three cases shown in FIG. 4 compare the Gm without boost, as in FIG. 1 with RTERM=2*RS, and with boost, as in FIG. 3 with RFF=2*RS, from the top: RE=0; RE=RS/10; and RE=RS. In all three cases, the gain of the boosted Gm stage is larger compared to the un-boosted stage. In addition the noise of the boosted stage is lower as the termination resistor is now also used to increase gain, not just to achieve the termination as in FIG. 1.
FIG. 5 shows the differential DC voltage swing at the output for the same conditions as in FIG. 4. In this result it becomes clear that since the linear input signal handling capability of the Gm stage is set by the voltage drop across RE→RE*IE, then by boosting the gain with the technique described here, the boosted stage will also reach the signal handling limit more quickly because of the extra signal current that gets injected or subtracted into nodes EN and EP via resistors R7 and R8 (RFF) respectively.
It should be pointed out that as long as the input is DC coupled, the current source I1 (2*IE) in FIG. 3 that sets the bias current for the resistively degenerated NPN differential pair can be replaced by a resistor R5 as shown in FIGS. 1 and 2. The bias current will be set by the voltage across R3, R4 and R5 which is set from the DAC via the input nodes IP and IM. The circuit needs to be driven differentially for the gain-boost to work.
In this manner, one can achieve increased gain with the same bias current used in the prior art transconductance stage. These embodiments also achieve this gain with lower noise. The source impedance match is preserved without increasing noise as in the prior art. The differential transistors are simultaneously used as common-source amplifiers and common-base amplifiers.
It will be appreciated that several of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Also that various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.
Patent Application
20150357982
