Patent Application
20050101277
1. Field of the Invention
The invention generally relates to the field of communications. More specifically the invention relates to gain control for use in coded signal communications, such as Code Division Multiple Access (“CDMA”) communications.
2. Discussion of the Related Art
In CDMA communication, coded signals are used to communicate between devices. Some typical CDMA communication systems use combinations of “spreading codes” and “covering codes” to encode signals. These encoded digital signals are used to convey digital voice, data and/or other forms of digital communication. As used herein spreading codes are pseudorandom number, or pseudo-noise, (“PN”) sequence codes and are known to those skilled in the art. Covering codes are also known those skilled in the art.
A spreading code encodes a data signal by applying a noise-like code sequence to the data at a rate faster than that of the data. Namely, the spreading code is applied to the data such that there are multiple “chips” of the code for any given element of data. Such an application of the spreading code is commonly referred to as direct sequence spreading of the data. A short code is an example of a spreading code. Chips and their associated chip rates are known to those skilled in the art.
A covering code further encodes the signal to provide “channelization” for a signal. For example, each unique covering code as it is applied to a spread signal provides a unique communication channel for the spread signal. Channelization allows a signal to be divided into a number of individual communication channels that may be either shared or assigned to specific users. Covering codes typically include families of codes that are either orthogonal (e.g., Walsh codes) or substantially orthogonal (e.g. Quasi Orthogonal Function codes, or “QOF” codes).
While the above-mentioned codes can be used to differentiate signals, interference from unwanted signals is a persistent problem in CDMA telephony communications. Interference degrades signal detection, tracking and demodulation capabilities of a receiver by hindering the recovery of a selected signal (i.e., a signal of interest, “SOI”). For example, interference can be the result of receiving one or more unwanted signals simultaneously with a selected signal. These interfering signals increase the total energy of the received signal, but decrease the Signal to Noise Ratio (“SNR”) of the selected signal.
The interfering signals can be coded signals having properties that are similar to that of the selected signal. Because of code similarities and associated signal energy, the coded signals often have a tendency to interfere with one another and disrupt the recovery of the selected signal. The lack of orthogonality of the received signals results in “leakage” from one signal into another. Examples of such interference include “cross-channel” interference and “co-channel” interference.
Co-channel interference may include multipath interference from the same transmitter, wherein a transmitted signal takes separate, unique paths that causes one path (e.g., an interfering signal path) and another path (e.g., a selected signal path) to differentially arrive at a receiver, thereby hindering processing of the selected signal path. Cross-channel interference may include interference caused by signal paths emanating from other transmitters, thereby hindering the processing of the selected signal path. Such interference can corrupt data and interfere with signal recovery as long as it is present in any substantial form.
Interference cancellation, such as that described in the '360, '828, '777 and TCOM0020 applications, substantially removes selected cross-channel interference and/or co-channel interference from a received signal. This interference cancellation increases the SNR of a selected signal. However, interference cancellation may decrease the energy of the SOI signal in the process of decreasing the amount of interference energy.
Prior art CDMA receivers typically scale a received signal at the receiver front-end to exploit the dynamic range of the bits used in quantizing the signal for subsequent processing. This front-end scaling is performed, among other reasons, to avoid division operations in SNR calculations and to exploit the dynamic range of signal quantization in the receiver.
Systems and methods for adjusting amplitude of an interference-canceled signal are presented. In one embodiment, a gain controller scales the signal amplitude of an interference-canceled signal. As used herein, an interference-canceled signal is a signal having one or more selected interfering channels and/or signal paths substantially removed from a received signal y. An interference-canceled signal from a Coded Signal Processing Engine (“CSPE”), as used herein, is generally referred to as an output canceled signal.
The received signal y essentially comprises the energy of the selected signal path Ec plus all other interference energy Iint. This total signal energy value I0 can be used to determine the SNR of an SOI, which is essentially Ec/I0. Accordingly, as the energy of the interference within I0 decreases and the energy of the SOI remains the same, the SNR of the SOI increases.
Interference cancellation selectively improves the SNR of an SOI by decreasing the energy of certain interfering signals. For example, as the number of interfering signals contributing to the interfering energy Iint substantially decreases, the SNR of the SOI typically increases because Iint is a component of I0 (e.g., if I0 decreases and Ec remains essentially the same, Ec/I0 increases). In selectively canceling certain interfering signals, the signal cancellation decreases the overall energy of the received signal because the energy of interfering signals is substantially removed. Moreover, signal cancellation may cancel energy from the SOI and thus decrease Ec by an amount less than the decrease in the energy of the interfering signals.
In a preferred embodiment, therefore, the gain controller comprises a scaling element that scales the overall signal energy, or amplitude, after interference cancellation and prior to signal demodulation in receiver circuitry. This scaling effectively compensates for the overall signal energy reduction resulting from interference cancellation to a level substantially equivalent to the I0 value prior to cancellation. If the reduction in I0 energy is greater than the Ec energy reduction, the SNR of the SOI as seen by the receiver increases. The amplitude adjusted output canceled signal improves receiver performance as the SOI is demodulated. Since prior art receivers typically adjust signal amplitude at the front-end of the receiver, a gain controller may be used to adjust the amplitude of an interference-canceled signal to a level comparable with that of the prior art front-end scaling. Receiver front-ends comprising signal scaling are well known to those skilled in the art.
The gain controller also comprises a receiving element configured for receiving either an output canceled signal or an uncanceled received signal y as an input. For example, the gain controller may receive an interference-canceled signal output from a CSPE, such as those described in the '360, '828, '777 and TCOM0020 applications. Alternatively, the gain controller may receive the signal y with no interfering components removed. Such an instance may occur when a determination is made to not perform signal cancellation on a symbol via the CSPE. Accordingly, the gain controller may apply a gain of unity (i.e., a gain of one) since there is no decrease in total signal energy attributable to signal cancellation.
In the preferred embodiment, the gain controller is an Automatic Gain Control (“AGC”) that is communicatively coupled between a CSPE and one or more processing fingers of a receiver to selectively adjust the amplitude of the output canceled signal by applying a gain. The AGC may be configured for receiving a bypass signal that alerts the AGC as to whether the CSPE is performing or not performing signal cancellation. Once the bypass signal is received, the AGC may route the received signal through another “gain path” of the AGC. This gain path may apply a gain that is substantially a unity gain. The AGC may be used in a serial canceller embodiment, a parallel canceller embodiment or any combination thereof.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that it is not intended to limit the invention to the particular form disclosed, but rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims.
The signal from the CSPE may be either an output canceled signal or a received signal in which no cancellation has been performed, such as when the CSPE generates an empty interference matrix that results in no cancellation. An output cancelled signal as used herein is a signal with one or more interfering signals substantially canceled and may be either a signal y having signal cancellation performed thereon or reference code x having signal cancellation performed thereon.
Gain controller 100 also comprises scaling element 102 communicatively coupled to receiving element 101. Scaling element 102 is configured for adjusting amplitude of the received signal from the receiving element 101. For example, if receiving element 101 transfers an output canceled signal to scaling element 102, the scaling element may adjust the amplitude of the signal to a level that is substantially comparable to the level of the signal prior to signal cancellation. If, however, the receiving element transfers an uncanceled signal, scaling element 102 may apply a gain that is substantially a unity gain.
Gain controller 200 also comprises scaling units 202 configured for adjusting amplitude of the I and Q input signals. The scaling elements in this embodiment are coupled to the receiving element 201 and are established in pairs in order to scale the magnitude of the I and Q components of the received digital input signal. These scaling units 202 scale a digital input signal (e.g., bit shifting the representation of the signal). For example, scaling units 202 may receive digital input signals, wherein a specified number of bits are used to represent the signal. The scaling units 202 may shift and/or truncate the number of incoming bits to decrease the number of bits representing the digital input signal and effectively scale the signal. Such truncation and scaling is a matter of design choice based on the requirements of a device coupled thereto (e.g., if a CSPE uses larger bit widths than the bit widths used by the communicatively coupled receiver). Bit widths and bit shifting are known to those skilled in the art.
A first pair of scaling units 202 (labeled scaling units U-202I and U-202Q) are configured as part of an uncanceled signal path for scaling the I and Q components of a received uncanceled signal. These scaling units 202 may apply a unity gain to the received signal components as signal cancellation was not performed on the signal. Alternatively, the scaling units U-202I and U-202Q may adjust the number of bits in order to match the requirements of a receiver coupled therewith. Scaling units U-202I and U-202Q transfer the signal components to delay elements 203, which substantially delay the signal components, if required, by an amount substantially equivalent to the delay introduced by the interference canceled signal path.
A second pair of scaling units 202 (labeled scaling units C-202I and C-202Q) are configured as part of an interference canceled signal path for scaling the I and Q components of a received interference-canceled signal (i.e., an output canceled signal). In this embodiment, scaling units C-202I and C-202Q are communicatively coupled to an AGC control loop described below herein. The scaling units C-202I and C-202Q apply a gain that is substantially unity or greater. In one embodiment, the scaling units may also adjust the number of bits representing the signal to appropriately scale the signal to an appropriate bit width as specified by the AGC loop.
Once an interference-canceled signal is scaled by scaling units C-202I and C-202Q, the I and Q components of the signal are transferred to multipliers 204I and 204Q. The multipliers 204I and 204Q multiply the signal with a feedback gain provided by the AGC loop lookup table (“LUT”) 211. The multipliers 204I and 204Q transfer the feedback-multiplied signals to scaling/clipping units 205I and 205Q to adjust the amplitude of the signal components and provide output signals that occupy an appropriate number of bits. In one embodiment, scaling/clipping units 205I and 205Q restore the amplitude of the signal components to substantially a level previously attained by front-end scaling in a receiver. Scaling/clipping units 205I and 205Q may adjust the number of bits representing the signal by truncating or rounding the number of bits as described above herein.
With the I and Q components of the signal scaled (i.e., either the scaled interference canceled signal I and Q components or the scaled uncanceled signal I and Q components), the scaled signal components are transferred to selector 206 for transfer to a device coupled thereto. For example, selector 206 is configured for selectively transferring either the scaled I and Q components of the interference-canceled signal or the scaled I and Q components of the uncanceled signal to a receiver for subsequent processing (e.g., tracking and/or demodulation). The selector 206 may select the scaled signal components for transfer based on an AGC bypass signal. For example, an AGC bypass signal may instruct selector 206 to transfer the amplitude adjusted uncanceled signal rather than the amplitude adjusted canceled signal.
Since scaling units C-202I and C-202Q and U-202I and U-202Q are communicatively coupled to receiving element 201, the scaling units may scale whichever signal is received by AGC 200. A determination may be made regarding the signal type that is actually received (i.e., either the I and Q components of the interference-canceled signal or the I and Q components of the uncanceled signal). This determination may be made either within gain controller 200 or by control circuitry external to the gain controller. For example, receiving element 201 may be configured for receiving the bypass signal and, in response to receiving that bypass signal, receiving element 201 may select the I and Q components of either the interference-canceled signal or the uncanceled signal or transmit the I and Q components to the appropriate scaling unit 202.
Such a determination may be based, at least in part, on the amplitude of the signal being transferred to gain controller 200. As stated hereinabove, while improving the actual SNR of a selected signal, interference cancellation may decrease the overall signal energy of a received signal. Accordingly, an interference-canceled signal may not demonstrate the SNR improvement in the receiver unless the signal is appropriately scaled to adjust for the reduction of total energy. Selector 206, therefore, determines which scaled I and Q components are to be transferred in response to receiving the AGC bypass signal. For example, if the AGC bypass signal indicates that a signal received by receiving element 201 is an uncanceled signal, selector 206 may selectively transfer the scaled I and Q components from scaling units U-202I and U-202Q via delay elements 203 to the device coupled thereto. If, however, the AGC bypass signal indicates that the received signal is a canceled signal, selector 206 may selectively transfer the scaled I and Q components from scaling/clipping units 205I and 205Q to the device coupled thereto.
As stated, C-202I and C-202Q are part of a control loop that provides a feedback gain for the interference-canceled signal. This control loop comprises signal squared magnitude unit 207, adder unit 208, comparator/accumulator 209, storage unit 210 (e.g., software, hardware or firmware memory) and LUT 211. Squaring unit 207 is configured for receiving the scaled I and Q components from scaling/clipping units 205I and 205Q and for element-wise squaring of each of the components. The squared components are then transferred to adder unit 208 for summing squared I components with squared Q components over a specified number of elements (e.g., a symbol period). The combination of squaring unit 207 and adder 208 essentially generates an estimate of the average output power of the interference-canceled signal via squaring and summing I and Q components.
In one embodiment, adder unit 208 is configured for summing squared I and Q values, thereby providing summed squared values. Adder 208 subsequently sums those values over a predetermined length. Adder 208 is also configured for receiving a threshold value, which is subtracted from the values summed over the predetermined length. The resulting value from adder 208 is transferred to comparator/accumulator 209 for determining whether energy of the scaled interference-canceled signal is greater than or less than the threshold. Effectively, the signal comparison is performed about the value of zero to thereby determine sign of the signal. In an alternative embodiment, the comparator/accumulator 209 may receive the threshold signal and the comparison may be against the threshold value. As the energy of the scaled interference-canceled signal changes, in either embodiment, a comparator/accumulator 209 either increments or decrements an index count in the accumulator based on the energy of the scaled interference-canceled signal as compared to a threshold.
In one preferred embodiment, if the amplitude of the scaled interference-canceled signal is less than the threshold, comparator/accumulator 209 increments the index count. If the amplitude of the scaled interference-canceled signal is greater than the threshold, comparator/accumulator 209 decrements the index count. The index counter ranges from 0 to N, whereby the accumulator is saturated at the range end values (i.e., either 0 or N). Therefore, the accumulator does not decrement a value of 0 or increment a value of N. For example, for a greater value of the index there is a greater amount of scaling (e.g., feedback gain).
The index count from comparator/accumulator 209 may be used as an index into LUT 211 configured within storage unit 210. In the preferred embodiment, there are N+1 possible gain values stored within LUT 211 in which the index count of comparator/accumulator 209 can access. The gain values may provide gains either on a linear or nonlinear scale based on index counts (e.g., gain values may be in ¼ dB increments on a linear scale). Once the gain of LUT 211 is accessed, the I and Q components of the interference-canceled signal are multiplied by the gain value via multipliers 204I and 204Q, respectively. These gain values when applied to the I and Q components of the interference-canceled signal dynamically adjust the amplitude of the interference-canceled signal.
While the count value from comparator/accumulator 209 is useful in indexing a particular gain value for application to the interference-canceled signal, this count value may also be used to retrieve a previous gain value of the interference-canceled signal if the gain value is frozen and stored in an AGC bypass situation. For example, once an AGC bypass signal is received, the control loop comprising elements 205I, 205Q, 207, 208, 209, 210 and 211 stores a gain value of the interference-canceled signal in storage unit 210 because signal cancellation has halted. When signal cancellation restarts and the AGC bypass signal has changed, the control loop may retrieve the previously stored gain value from storage unit 210 to begin scaling the amplitude of the interference-canceled signal from the previous gain value. Accordingly, the stored gain value may decrease the amount of time for the gain controller 200 to converge to an appropriate gain value for the interference-canceled signal. Those skilled in the art should readily recognize that the gain value required for scaling a symbol of the interference cancelled signal to a level substantially equivalent to a level provided by the front end of a receiver may change on a symbol by symbol basis.
Additionally, the storage unit 210 may be configured to receive a reset signal to delete a stored gain value if the AGC is reset. For example, it may be necessary to reset the AGC when an input signal changes. If an input signal changes, such as when a CSPE selects another signal to cancel interference from and thereby changes the output cancelled signal, the reset signal may be generated and transferred to reset the AGC so that the AGC does not restore the new input signal to a gain value of the previous input signal. In receiving the reset signal, the AGC resets the count value to an initial setpoint that indexes a predetermined initial gain value. In one embodiment, the initial setpoint may be set to zero, so that the initial gain value is unity. In a second embodiment, the initial setpoint value may be based on the strengths of interfering signals within processing fingers. For example, low energy interference signals may have a low initial setpoint and high energy interference signals may have a high initial setpoint. Sets of interference energy values may have the same initial setpoint. In a third embodiment, the initial setpoint value may be an arbitrary non-zero value. Selecting an appropriate setpoint may reduce the time of convergence for the AGC.
While one embodiment has been shown and described herein, those skilled in the art should readily recognize that other embodiments may fall within the scope and spirit of the invention. For example, gain controller 200 illustrates one preferred implementation that is particularly useful in adjusting amplitude of an interference-canceled signal and recovering stored gain values via the control loop as described herein. Furthermore, the preferred implementation of gain controller 200 is not intended to limit the invention to the gain control of an AGC. Rather, other types of gain control may be used and are simply a matter of design choice.
Present embodiments of the AGC may be implemented within an Application Specific Integrated Circuit (“ASIC”), Field Programmable Gate Array (“FPGA”), Digital Signal Processor (“DSP”) and/or other circuitry. However, the invention is not intended to be limited to such implementations as the embodiments may be implemented in hardware, software, firmware, optics or any combination thereof. For at least these reasons, the invention should not be limited to the preferred embodiment shown and described herein. Rather, the invention should only be limited by the language recited in the claims and their equivalents.
In this embodiment, the interference cancellation system is illustrated comprising an interference selector 301 for selecting one or more interfering signals from a received digital signal. Interference selector 301 may also receive reference codes corresponding to those interfering signals for use in selecting those interfering signals. For example, interference selector 301 may comprise signal path selector 302 and channel selector 303 for selecting certain interfering signal path and channel combinations based on on-time PN reference codes of a received signal path and covering codes of associated channels.
The selected interfering signal paths and/or channel combinations are transferred to matrix generator 304 for generating interference matrix 305, which is used to substantially cancel, or remove, the selected interferers from the digital signal. For example, as described in the TCOM0020 application, interfering signal paths, associated channels and/or the various combinations thereof may be input to matrix 305 as one or more interference vectors 306. Additionally, phase estimates of the signal paths and their associated channels may also be transferred to matrix generator 305 for imposition of phase on the interference vectors 306. Processor 307 may use interference matrix 305 to generate a cancellation operator that is subsequently applied to an input signal via applicator 308. The input signal may be a received digital signal, an output canceled signal, a reference code or an output canceled reference code, such as those described in the '777, '345, TCOM0020, and '828 applications. In one embodiment, one or more of the interference vectors 306 may comprise composite interference vectors as described in the '360 and TCOM0020 applications.
In one embodiment, the cancellation operator is a projection operator that projects an input signal onto a subspace that is substantially orthogonal to a subspace spanned by the selected interfering signals. Such a projection operator may be generated by processor 307 according to the following form:
Ps⊥=I−S(STS)−1ST (Eq. 1)
wherein Ps⊥ is the projection operator, I is an identity matrix, S is an interference matrix 305 and ST is a transpose of the matrix 305. Projection operators and their associated constructions are described in the '346, '360, '829, '219 and '834 applications.
Although described and illustrated in one preferred embodiment, those skilled in the art should readily recognized that gain controller 309 may be configured in a variety of ways to receive an output canceled signal and/or an uncanceled signal and thereby control the amplitude of that received signal. Accordingly, the invention is not intended to be limited to the embodiment shown and described herein; rather, the invention is only intended to be limited by the language recited in claims and their equivalents.
Processor 307 may use these matrices 305 to generate a plurality of cancellation operators (e.g., such as the cancellation operator described in
Each applicator 308 may apply a cancellation operator to an input signal to generate a unique output signal. The output signal may be either an output canceled signal or an uncanceled signal, wherein the latter is based on the generation of an empty matrix 305 or a pass-through of an uncanceled signal. For example, a matrix 305 of selected interfering signals represented by vectors 306 may be used to generate a cancellation operator which substantially cancels those selected interfering signals from the input signal. Alternatively, a matrix 305 may contain no interfering signals (e.g., an empty matrix), which results in the generation of a cancellation operator that is a scalar of one and no signals are, therefore, canceled from the input signal. An empty matrix 305, therefore, results in an uncanceled output signal. Control determinations for either selecting or not selecting certain interfering signals for matrix generation may be performed within CSPE 400, an external controller or directed by a receiver communicatively coupled thereto.
Each signal from applicators 308 is subsequently transferred to a corresponding gain controller 309 (labeled 3091, . . . , 309M). The gain controller 309 applies a gain to the received signal based on the type of signal received and its energy. For example, if the signal is an output canceled signal, the gain controller 309 may apply a gain greater than or equal to one to the signal, as shown and described in
While described and illustrated in one preferred embodiment, those skilled in the art should readily recognized that the embodiment is only exemplary in nature and that other embodiments may fall within the scope and spirit of the invention. Accordingly, the invention is not intended to be limited to the embodiment shown and described herein; rather, the invention is only intended to be limited by the language recited in claims and their equivalents. Moreover, those skilled in the art should readily recognize that this embodiment may be implemented for serial interference cancellation or for parallel interference cancellation as described in the '777, '836, TCOM0019 and TCOM0024 applications.
Digital receiver circuitry 504 transfers the digital signal to CSPE 505 for selective cancellation of certain signal paths and channels that interfere with an SOI within the digital signal. Such interference cancellation may be performed in accordance with the embodiments shown and described in
From these one or more interference cancellations, CSPE 505 may generate one or more output canceled signals for use by receiver 502. For example, receiver circuitry 504 may comprise one or more processing fingers which track and/or demodulate the transferred output canceled signals from CSPE 505. A connection element 506 is configured between receiver circuitry 504 and CSPE 505 to selectively transfer the one or more output signals and possibly other signals from CSPE 505 to receiver circuitry 504 for subsequent processing.
In this embodiment, gain controller 507 is configured external to CSPE 505. The gain controller 507 may be optionally configured between receiver circuitry 504 and connection element 506 or between connection element 506 and CSPE 505. In either configuration, gain controller 507 may represent a plurality of gain controllers, each configured for restoring the power of a received signal to a substantially similar level to what was produced by front-end scaling by receiver circuitry 504. For example, as CSPE 505 may decrease the overall signal power of a received digital signal, albeit while improving SNR of an SOI within the digital signal, a gain controller 507 may adjust the amplitude of an output canceled signal from CSPE 505 to compensate for any associated decrease in total energy of the signal. Amplitude adjustments of gain controller 507 may be performed in accordance with the embodiment shown and described in
The digital signal may comprise one or more interfering signals as well as an SOI. Signal cancellation may be performed on the digital signal to substantially cancel the one or more interfering signals from the digital signal, in element 602, and thereby generate an interference-canceled signal. Such signal cancellation may be performed by a CSPE, such as CSPE 400 of
The energy of the interference-canceled signal is amplitude adjusted, in element 603. For example, a gain controller, such as gain controller 200 of
Additionally, the bypass signal causes the amplitude adjustment of the received digital signal to be returned to unity, in element 607. For example, interference cancellation by a CSPE may be temporarily halted through the construction of an empty matrix and subsequent application of an associated scalar of one to the received signal. Accordingly, amplitude adjustment of the interference-canceled signal may be bypassed in favor of amplitude adjustment of the uncanceled signal in accordance with the embodiment shown and described in
Once the bypass signal is received in element 604, amplitude adjustment is performed in element 607 on the uncanceled digital signal until a gain controller reset or a change in the bypass signal is detected, in elements 607 and 608 respectively. A gain controller reset may be produced if a different signal path is sent to a matrix generator and/or a different input signal is transferred to the gain applicator. If a gain controller reset is received (i.e., element 611) then the saved gain value is deleted and the process continues to element 602. Otherwise, the process continues to element 608. In an alternative embodiment, elements 608 and 611 are exchanged in the method. If no change in the bypass signal is detected, the amplitude adjustment of the uncanceled digital signal of element 607 continues. Once a change is detected in the bypass signal, amplitude adjustment reverts to the gain value corresponding to the interference-canceled signal.
Amplitude adjustment of the interference-canceled signal is restored by retrieving a previous gain value of the interference-canceled signal if the bypass signal is received, in element 609, or reverting to an initial value if the reset signal is received, in element 613. The initial value may be fixed or based upon the strength of the interfering signal. For example, the previous gain value may be retrieved from storage unit 210 and/or LUT 211 of
While one preferred embodiment has been shown and described herein, those skilled in the art should readily recognize that the invention is not intended to be limited to the preferred embodiment. Rather, the invention is only intended to be limited by the language recited in the claims. Additionally, while the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character. Accordingly, it should be understood that only the preferred embodiment and minor variants thereof have been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.
This application is a continuation-in-part of commonly owned and co pending U.S. patent application Ser. No. 10/773,777 (filed Feb. 06, 2004; the “'777 application”), Ser. No. 10/699,954 (filed Sep. 23, 2003; the “'954 application”), Ser. No. 10/686,828 (filed Oct. 15, 2003; the “'828 application”), Ser. No. 10/686,829 (filed Oct. 15, 2003; the “'829 application”), Ser. No. 10/699,360 (filed Oct. 31, 2003; the “'360 application”), Ser. No. 10/294,834 (filed Nov. 15, 2002; the “834 application”), Ser. No. 10/686,359 (filed Oct. 15, 2003; the “359 application”) Ser. No. 10/763,346 (filed Jan. 23, 2004; the “'346 application”), TCOM0019 (filed Sep. 7, 2004; the “'TCOM19 application”), TCOM0024 (filed, 2004; the “'TCOM0024 application”) and TCOM0020 (filed Sep. 7, 2004; the “'TCOM0020 application”), which are all hereby incorporated by reference. This application is also related to Ser. No. 09/988,219 (filed Nov. 19, 2001; the “'219 application”) and to Ser. No. 10/247,836 (filed Sep. 20, 2002; the “'836 application”), which are each hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09988219 | Nov 2001 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10773777 | Feb 2004 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10669954 | Sep 2003 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10686828 | Oct 2003 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10686829 | Oct 2003 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10699360 | Oct 2003 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10294834 | Nov 2002 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10686359 | Oct 2003 | US |
| Child | 11012817 | Dec 2004 | US |
| Parent | 10763346 | Jan 2004 | US |
| Child | 11012817 | Dec 2004 | US |
