This application claims priority of U.S. provisional patent application No. 60/188,348, filed Mar. 9, 2000 entitled “Method of Gaining Access to Internal Nodes in a PLD,” which is hereby incorporated by reference. This application is related to U.S. patent application Ser. No. 08/958,435, filed Oct. 27, 1997, entitled “Embedded Logic Analyzer For A Programmable Logic Device, ” now U.S. Pat. No. 6,182,247 to U.S. patent application Ser. No. 09/186,607 filed Nov. 6, 1998, entitled “Enhanced Embedded Logic Analyzer,” now U.S. Pat. No. 6,286,114 and to U.S. patent application Ser. No. 09/186,608 filed Nov. 6, 1998, entitled “Enhanced Embedded Logic Analyzer:,” now U.S. Pat. No. 6,247,147.
Number | Name | Date | Kind |
---|---|---|---|
4696004 | Nakajima et al. | Sep 1987 | A |
4788492 | Schubert | Nov 1988 | A |
4835736 | Easterday | May 1989 | A |
4847612 | Kaplinsky | Jul 1989 | A |
4873459 | El Gamal et al. | Oct 1989 | A |
5036473 | Butts et al. | Jul 1991 | A |
5058114 | Kuboki et al. | Oct 1991 | A |
5124588 | Baltus et al. | Jun 1992 | A |
5329470 | Sample et al. | Jul 1994 | A |
5365165 | El-Ayat et al. | Nov 1994 | A |
5425036 | Liu et al. | Jun 1995 | A |
5452231 | Butts et al. | Sep 1995 | A |
5568437 | Jamal | Oct 1996 | A |
5572712 | Jamal | Nov 1996 | A |
5629617 | Uhling et al. | May 1997 | A |
5640542 | Whitsel et al. | Jun 1997 | A |
5661662 | Butts et al. | Aug 1997 | A |
5717695 | Manela et al. | Feb 1998 | A |
5717699 | Haag et al. | Feb 1998 | A |
5764079 | Patel et al. | Jun 1998 | A |
5821771 | Patel et al. | Oct 1998 | A |
5870410 | Norman et al. | Feb 1999 | A |
5960191 | Sample et al. | Sep 1999 | A |
5983277 | Heile et al. | Nov 1999 | A |
6014334 | Patel et al. | Jan 2000 | A |
6016563 | Fleisher | Jan 2000 | A |
6020758 | Patel et al. | Feb 2000 | A |
6104211 | Alfke | Aug 2000 | A |
6107821 | Kelem et al. | Aug 2000 | A |
6157210 | Zaveri et al. | Dec 2000 | A |
6182247 | Herrmann et al. | Jan 2001 | B1 |
6212650 | Guccione | Apr 2001 | B1 |
6223148 | Stewart et al. | Apr 2001 | B1 |
6247147 | Beenstra et al. | Jun 2001 | B1 |
6259271 | Couts-Martin et al. | Jul 2001 | B1 |
6286114 | Veenstra et al. | Sep 2001 | B1 |
6317860 | Heile | Nov 2001 | B1 |
6321369 | Heile et al. | Nov 2001 | B1 |
6389558 | Herrmann et al. | May 2002 | B1 |
6460148 | Veenstra et al. | Oct 2002 | B2 |
6481000 | Zaveri et al. | Nov 2002 | B1 |
Number | Date | Country |
---|---|---|
4042262 | Jul 1992 | DE |
Entry |
---|
Jaini et al. , Observing test response of embedded cores through surrounding logic, 1999, IEEE, p. I-119 to I-123.* |
Touba et al., Testing embedded cores using partial isolation rings, 1997, IEEE, p. 10-16.* |
Marantz, Joshua, “Enhanced Visibility and Performance in Functional Verification by Reconstruction”, Proceedings of the 35th Annual Conference on Design Automation Conference, pp. 164-169. 1998. |
Stroud, Charles et al., “Evaluation of FPGA Resources for Built-in-Self-test of Programmable Logic Blocks”, Proceedings of the 1996 ACM 4th International Symposium on Field-programmable Gate Arrays, p. 107. 1996. |
Collins, Robert R., “Overview of Pentium Probe Mode”, (www.x86.org/articles/problemed/ProbeMode.htm), Aug. 21, 1998, 3 pgs. |
Collins, Robert R., “ICE Mode and the Pentium Processor”, (www.x86.org/ddj/Nov97/Nov97.htm), Aug. 21, 1986, 6 Pgs. |
“PentiumPro Family Developer's Manual”, vol. 1: Specifications, Intel®Corporation, 1996, 9 Pgs. |
“Pentium® Processor User's Manual”, vol. 1, Intel®Corporation, 1993, Pgs. 3-11. |
Xilinx, Inc.: ISE Logic Design Tools: ChipScope. |
Synplicity, Inc. “Identify ™RTL Debugger”, 2003; pp. 1-2. |
Altera, Signal Tap Analysis in the Quartus II Software Version 2.0; Sep. 2002; Version. 2.1; Altera Corporation. |
Number | Date | Country | |
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60/188348 | Mar 2000 | US |