Patent Application
20240045454
This application claims priority to Chinese patent application: Serial No. 2022109386191, filed on Aug. 5, 2022, entitled “GALLIUM NITRIDE REFERENCE VOLTAGE GENERATION CIRCUIT,” which is hereby incorporated by reference in its entirety for all purposes.
The described embodiments relate generally to power converter circuits, and more particularly, the present embodiments relate to gallium nitride (GaN) reference voltage generation circuits employed in power converter circuits.
Electronic devices such as computers, servers and televisions, among others, employ one or more electrical power conversion circuits to convert one form of electrical energy to another. Some electrical power conversion circuits convert a high DC voltage to a lower DC voltage using a circuit topology called a half bridge converter. As many electronic devices are sensitive to size and efficiency of the power conversion circuit, new power converters can provide relatively higher efficiency and lower size for the new electronic devices.
In some embodiments, a circuit is disclosed. The circuit includes a first gallium nitride (GaN)-based transistor having a first gate terminal, a first source terminal and a first drain terminal, a second GaN-based transistor having a second gate terminal, a second source terminal and a second drain terminal, the second gate terminal coupled to the first drain terminal, an input terminal coupled to the first gate terminal and arranged to receive a first voltage, an output terminal coupled to the second source terminal, a power supply terminal coupled to the first drain terminal and the second drain terminal, and a feedback circuit coupled between the first source terminal and the second source terminal, where the first source terminal is coupled to a ground through a first impedance element, the first impedance element having a positive temperature coefficient, and where the circuit is arranged to generate an output voltage at the output terminal that tracks the first voltage.
In some embodiments, the circuit further includes a second impedance element coupled between the first source terminal and the first impedance element, where the second impedance element has a zero temperature coefficient.
In some embodiments, the circuit further includes a third impedance element coupled between the first drain terminal and the power supply terminal, where the third impedance element has a zero temperature coefficient.
In some embodiments, the feedback circuit includes a fourth impedance element.
In some embodiments, the output voltage stays constant while an operational temperature of the circuit varies.
In some embodiments, the first and second GaN-based transistors are formed on a monolithic substrate including GaN.
In some embodiments, the monolithic substrate includes a GaN-based power transistor operated by a GaN-based driver.
In some embodiments, the GaN-based power transistor is arranged in a high-side configuration.
In some embodiments, a circuit is disclosed. The circuit includes a first circuit having a negative temperature coefficient and including a plurality of impedance elements, and a second circuit having a positive temperature coefficient and including a first GaN-based transistor and a second GaN-based transistor and the plurality of impedance elements, the second circuit operatively coupled to the first circuit, an input terminal coupled to a gate terminal of the first GaN-based transistor, and an output terminal coupled to a source terminal of the second GaN-based transistor, where an output voltage at the output terminal tracks an input voltage at the input terminal.
In some embodiments, a first of the plurality of impedance elements is coupled between a source terminal of the first GaN-based transistor and a ground.
In some embodiments, the first of the plurality of impedance elements has a positive temperature coefficient.
In some embodiments, a second of the plurality of impedance elements is coupled between the source terminal of the first GaN-based transistor and the first of the plurality of impedance elements.
In some embodiments, the second of the plurality of impedance elements has a zero temperature coefficient.
In some embodiments, the first and second GaN-based transistors are formed on a monolithic substrate including GaN.
In some embodiments, the monolithic substrate includes a GaN-based power transistor operated by a GaN-based driver.
In some embodiments, a circuit is disclosed. The circuit includes a first gallium nitride (GaN)-based transistor having a first gate terminal, a first source terminal and a first drain terminal, a second GaN-based transistor having a second gate terminal, a second source terminal and a second drain terminal, the second source terminal coupled to the first source terminal, an input terminal coupled to the first gate terminal and arranged to receive a first voltage, an output terminal coupled to the second gate terminal, and a power supply terminal coupled to the first drain terminal and the second drain terminal, where the first source terminal is coupled to a ground through a first impedance element, the first impedance element having a zero temperature coefficient, and where the circuit is arranged to generate an output voltage at the output terminal that tracks the first voltage.
In some embodiments, the circuit further includes a second impedance element coupled between the second drain terminal and the power supply terminal, where the second impedance element has a zero temperature coefficient.
In some embodiments, the circuit further includes a third impedance element coupled between the first gate terminal and the power supply terminal.
In some embodiments, the first and second GaN-based transistors are formed on a monolithic substrate including GaN.
In some embodiments, the monolithic substrate includes a GaN-based power transistor operated by a GaN-based driver.
Circuits and related techniques disclosed herein relate generally to power conversion devices. More specifically, circuits, devices and related techniques disclosed herein relate to gallium nitride (GaN) reference voltage generation circuits. In some embodiments, a GaN-based reference voltage generation circuit can generate a reference voltage on a GaN-based integrated circuit (IC), where the reference voltage can stay at a relatively constant value while an operating temperature of the IC varies. In various embodiments, the generated reference voltage can stay at a relatively constant value while a loading of the reference voltage generation circuit varies. In some embodiments, the generated reference voltage can track an input voltage to the reference generation circuit. In various embodiments, the generated reference voltage can stay at a value that is independent of variations in the GaN-based IC power supply. In some embodiments, the generated reference voltage can track an input voltage while varying with power supply changes similar to the rest of the circuits of the GaN-based IC. In various embodiments, a reference voltage generation circuit can include a feedback circuit that can allow for compensation for variations in temperature, loading and power supply.
In some embodiments, a GaN-based reference voltage generation circuit can generate a reference voltage on a GaN-based integrated circuit (IC), thereby removing external reference voltage circuits. In this way, a GaN-based IC can operate independent of external circuitry such as silicon-based circuitry used to generate reference voltages. In various embodiments, a GaN-based reference voltage generation circuit can be used in a high-side section of a half-bridge circuit of a power converter circuit. In some embodiments, a GaN-based reference voltage generation circuit can be used in a low-side section of a half-bridge circuit of a power converter circuit. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.
Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part hereof. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
Current approaches in GaN-based IC reference voltage generation techniques may generate a reference voltage that varies with temperature, loading and power supply variations, because current GaN-based fabrication processes may only offer N-type transistors (transistors that use electrons in their operation), and may not offer P-type transistors (transistors that use holes in their operation).
Circuit 100 can further include a transistor 124 having a drain terminal 126, a gate terminal 128 and a source terminal 130. Gate terminal 128 can be coupled to the drain terminal 110. The drain terminal 126 can be coupled to the power supply 106 and the source terminal 130 can be coupled to an output node 132. Circuit 100 can further include a feedback circuit that that is coupled between the source terminal 130 and the source terminal 114. In some embodiments, the feedback circuit can include an impedance element. In the illustrated embodiment, the feedback circuit includes impedance element 122 coupled between the source terminal 130 and the source terminal 114. Impedance element 122 can be used to provide feedback from node 132 and source terminal 130 to node 127. In some embodiments, impedance element 120 can be a two-dimensional electron gas (2DEG) resistor. A 2DEG resistor can have a positive temperature coefficient, i.e., as temperature increase, a value of the 2DEG resistor increases proportionally. In various embodiments, impedance elements 116 and 118 can be formed from silicon chrome (SiCr). A SiCr resistor can have a zero temperature coefficient, i.e., as temperature increase, a value of the SiCr resistor may stay relatively constant. In some embodiments, circuit 100 can be monolithically integrated in a GaN-based IC. In various embodiments, the transistors 108 and 124 can be formed on a GaN-based die, while the other components of circuit 100 can be formed on a separate die.
The operation of circuit 100 is now described. Circuit 100 can generate a reference voltage 115 (Vout) at node 132. Circuit 100 can operate in a high-side configuration where Vout can be used in a high-side section of a GaN-based IC. In some embodiments, circuit 100 can be used in a high-side arrangement in a GaN-based half-bridge circuit used for DC-DC power conversion. In various embodiments, circuit 100 can operate in a low-side configuration where Vout can be used in a low-side section of a Ga-based IC. Input pad 104 can be configured to receive an external reference voltage 109 (Vref). When a value of Vref is relatively higher than a threshold voltage of the transistor 108, transistor 108 can turn on and allow a current to flow from power supply 106 through impedance element 116, transistor 108, and impedance elements 118 and 120 to ground node 102. When transistor 108 turns on, a voltage Vgs1 can develop across gate terminal 112 to source terminal 114. Thus, a first voltage across impedance elements 118 and 120 can develop that is equal to Vref−Vgs1. Therefore, a second voltage across impedance element 116 can develop that is equal to Vref−Vgs1 because a voltage drop across drain terminal 110 to source terminal 114 can be relatively small.
When a value of gate to source voltage of the transistor 124 is relatively higher than a threshold voltage of the transistor 124, transistor 124 can turn on and a voltage Vgs2 can develop across gate terminal 128 to source terminal 130. Impedance element 122 can provide negative feedback from source terminal 130 to source terminal 114. Feedback current 117 (IFB) can flow from source terminal 130 to source terminal 114 through impedance element 122. Thus, Vout is given by:
In equation (2), the term IFB*R3 (i.e., a voltage across impedance element 122) can cancel out variations in power supply VDD that may affect Vout. Thus, when VDD increases Vout increases as well thereby causing an increase in IFB, thus reducing a current through impedance element 116. This in turn can reduce a voltage drop from VDD to Vout, thereby Vout can increase proportional to VDD increase. For the same reasoning, Vout can decrease proportional to VDD decrease.
In some embodiments, impedance element 120 can have a positive temperature coefficient, i.e., when temperature increases, R2 (impedance of impedance element 120) can increase as well. For example, impedance element 120 can be formed from a 2DEG resistor. In various embodiments, impedance elements 118 and 116 can have a zero temperature coefficient, i.e., when temperature varies, R1 and R3 can stay relatively constant. For example, impedance elements 118 and 116 can be formed from SiChrome. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, impedance element 120 can be formed from any suitable material that has a positive temperature coefficient. Further, impedance elements 116 and 118 can be formed from any suitable material that has a zero temperature coefficient. In equation (2), the term
can have a negative temperature coefficient because R2 has a positive temperature coefficient and is in the denominator. The term
can have a positive temperature coefficient. Thus, these two terms can cancel out temperature variations in Vout, and generate Vout that can be independent of temperature variations. This is shown graphically in
as a function of temperature. The term
is denoted by 204 and the term
is denoted by 210. Temperature is shown on the x-axis 206, a first voltage is shown on left Y-axis 202 and a second voltage is shown on right Y-axis 208. As can be seen in
Circuit 540 further includes a transistor 544 having a gate terminal 548, a source terminal 550 and a drain terminal 546. Source terminal 550 can be coupled to source terminal 514. Circuit 540 can include an impedance element 530 that is coupled to the power supply 506 at one end and coupled to the drain terminal 546 at the other end. Circuit 540 can further include a transistor 524 having a gate terminal 528, a source terminal 531 and a drain terminal 526. Gate terminal 528 can be coupled to drain terminal 546. Drain terminal 526 can be coupled to the power supply 506. Circuit 540 can further include an impedance element 532. Impedance element 532 can be coupled to the on-chip ground node 502 at one end and to the source terminal 531 at the other end. Source terminal 531 may be coupled to a node 539. Impedance elements 520, 516 and 530 can be formed from SiChrome. In some embodiments, impedance element 516 can formed from a different material than impedance elements 520 and 530. In various embodiments, circuit 540 can be monolithically integrated in a GaN-based IC. In some embodiments, circuit 500 can be monolithically integrated in a GaN-based IC on a GaN-based substrate.
The operation of circuit 500 is now described. Circuit 500 can generate a reference voltage 515 (Vrefout) at node 539. Circuit 500 can operate in a low-side configuration where Vrefout can be used in a low-side section of an IC. In some embodiments, circuit 500 can be used in a low-side arrangement of a GaN-based half-bridge circuit used for DC-DC power conversion. In various embodiments, circuit 500 can operate in a high-side configuration where Vrefout can be used in a high-side section of an IC. Input pad 505 can be configured to receive a voltage 509 (Vz) generated by the Zener diode 504. When a value of Vz is relatively higher than a threshold voltage of the transistor 508, transistor 508 can turn on and allow a current to flow from power supply 506 through impedance element 520 to on-chip ground node 502. When transistor 508 turns on, a voltage Vgs3 can develop across gate terminal 512 to source terminal 514.
Thus, a voltage equal to Vz−Vg3 can appear at node 529. Since the source terminal 550 is coupled to the source terminal 514, a voltage equal to Vz can appear at the gate terminal 548 because transistors 508 and 544 can have similar gate-to-source voltage drops. Therefore, Vz can appear at output node 539. Transistor 544, impedance elements 520 and 530 and transistor 524 can form a feedback circuit that can adjust the output voltage Vrefout. For example, when Vrefout is relatively high, increased current can flow though transistor 544 and impedance element 530, therefore a voltage at gate terminal 528 may decrease resulting in reduced Vrefout. In this way, Vrefout can stay relatively constant over varying load conditions. As an example, when a value of Vz is 6 V, Vrefout can also be at 6 V.
Although GaN-based reference voltage generation circuits are described and illustrated herein with respect to one particular configuration of GaN-based reference voltage generation circuits, embodiments of the disclosure are suitable for use with other configurations of GaN-based and non-GaN-based circuits, such as for use in power converter circuits using silicon, silicon-carbide or other semiconductor devices.
In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.
Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Terms “and,” “or,” and “an/or,” as used herein, may include a variety of meanings that also is expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and/or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.
Reference throughout this specification to “one example,” “an example,” “certain examples,” or “exemplary implementation” means that a particular feature, structure, or characteristic described in connection with the feature and/or example may be included in at least one feature and/or example of claimed subject matter. Thus, the appearances of the phrase “in one example,” “an example,” “in certain examples,” “in certain implementations,” or other like phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and/or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and/or features.
In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022109386191 | Aug 2022 | CN | national |
