"Load Impedance for Transistor Circuit" by H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 12, No. 9, Feb. 1970, p. 1516. |
"Programmable Logic Chip" by M. S. Axelrod and S. Singh, IBM Technical Disclosure Bulletin, vol. 14, No. 4, Sep. 1971, p. 1056. |
"Fast-Write Search Cam Cell" by H. J. Kelly, IBM Technical Disclosure Bulletin, vol. 17, No. 3, Aug. 1974, p. 882. |
"Decoder for Ground-Up Array with STL-Compatible Output" by H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 20, No. 4, Sep. 1977, p. 1451. |
"Implementing Array and Logic Functions On a Single Chip" by J. N. Pomeranz, R. Nijhuis, R. Ehrlickman, E. Colao & R. Dennison, IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978, p. 3921. |
"Memory With Double Word Readout" by Y. M. Ting, H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, p. 2831. |
"STL Masterslice Random-Access Memory" by A. H. Dansky, R. T. Dennison & H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, p. 2833. |
"Integrated Static SCR Memory Cell" by R. T. Farley & H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, p. 135. |
"Low-Power Bipolar Random-Access Memory Array" by H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980, p. 3711. |
"I.sup.2 L/MLT Storage Cell Layout", by H. H. Berger, K. Heuber, E. Klink & S. K. Wiedmann, IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, p. 4604. |
"Lay-Out of an Emitter-Coupled Cell with PNP Loads", by G. Boudon, B. Denis & P. Mollier, IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep. 1980, p. 1473. |
"Efficient Memory Cell Useful for DC Testing" by E. F. Culican & H. D. Varadarajan, IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, p. 2309. |
"Bipolar Memory Cell with Polysilicon-Metal Cross-Coupling" by D. D. Howard & S. K. Weidmann, IBM Technical Disclosure Bulletin, vol. 23, No. 7A, Dec. 1980, p. 2727. |
"Redundancy Schmeme for High-Speed Random-Access Memories" by S. D. Malaviya, IBM Technical Disclosure Bulletin, vol. 23, No. 7B, Dec. 1980, p. 3248. |
"MLT/I.sup.2 L Storage Cell" by A. Schmitt, IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan. 1981, p. 3745. |
"Harper PNP Cell Layout with Improved PNP Characteristics" by R. Cullet, B. Denis & D. Omet, IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983, p. 658. |
"Memory Cell with Minimized Negative Resistance Effects" by M. J. Hargrove & C. J. Masenas, IBM Technical Disclosure Bulletin, vol. 26, No. 6, Nov. 1983, p. 2692. |
"SCR Cross-Coupled Memory Cell" by M. D. Hulvey, I. W. Kim & T. A. Selfridge, IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, p. 3119. |
"Low Leakage Complementary Transistor Switch Cell" by B. W. Martin, Jr., G. A. Ritter, C. G. Rivadeniera & S. C. Sullivan, IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, p. 3229. |
"High Performance Integrated Array Cell" by A. E. Barish and R. L. Ehrlickmann, IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, p. 3240. |
"Multi-Port RAM Cell Structure" by M. N. Shen, IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, p. 3588. |