Gate array

Abstract

A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

FIG. 1A is a block diagram showing a gate array of a first embodiment of the invention;

FIG. 1B is a circuit diagram showing a gate array of a first embodiment of the invention;

FIG. 2A is a block diagram showing an example of a unit cell using a gate array;

FIG. 2B is a block diagram showing an example of a unit cell using a gate array;

FIG. 2C is a block diagram showing an example of a unit cell using a gate array;

FIG. 3A is a block diagram showing an example of a conventional gate array;

FIG. 3B is a circuit diagram showing an example of a conventional gate array;

FIG. 4A is a block diagram showing a gate array of a second embodiment of the invention; and

FIG. 4B is a circuit diagram showing a gate array of a second embodiment of the invention;

Claims

1. A gate array comprising: a plurality of unit cells, the unit cells arranged in parallel on a semiconductor substrate and having the same pattern including a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor each including a gate, a source and a drain, the gate of the first MOS transistor and the gate of the second MOS transistor being connected by gate wiring, with the gate wiring having a first gate terminal portion and a second gate terminal portion;a plurality of metal wiring lines, formed, with an insulating layer between, on the unit cells;a plurality of contacts, that make electrical connection between the metal wiring lines and the first gate terminal portion, the second gate terminal portion, the source or the drain,wherein there is one of the plurality of contacts at each of the first gate terminal portion and at the second gate terminal portion in one of the unit cells in which neither the first MOS transistor nor the second MOS transistor is being used as a transistor.

2. The gate array of claim 1, wherein the unit cells also have a source potential region and a ground potential region, and the source and the drain of the one of the first MOSs that is not being used as a transistor together with the source and the drain of the one of the second MOSs that is not being used as a transistor, are connected to the source potential region or the ground potential region.

3. The gate array of claim 1, wherein the source and drain of the one of the first MOSs that is not being used as a transistor is connected to the gate of the one of the first MOSs that is not being used as a transistor, and the source and drain of the one of the second MOSs that is not being used as a transistor is connected to the gate of the second MOS that is not being used as a transistor.

4. A gate array comprising: a plurality of unit cells, the unit cells arranged in parallel on a semiconductor substrate and having the same pattern including a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor each including a gate, a source and a drain, the gate of the first MOS transistor and the gate of the second MOS transistor being connected by gate wiring, with the gate wiring having a first gate terminal portion and a second gate terminal portion;a plurality of metal wiring lines, formed, with an insulating layer between, on the unit cells and;a plurality of contacts, that make electrical connection between the metal wiring lines and the first gate terminal portion, the second gate terminal portion, the source or the drain,wherein there is one of the plurality of contacts at each of the first gate terminal portion and the second gate terminal portion in one of the unit cells in which one of the contacts is not provided at any of the source or the drain of the first MOS transistor or the source or the drain of the second MOS transistor.

5. A gate array comprising: a plurality of unit cells, the unit cells arranged in parallel on a semiconductor substrate and having the same pattern including a source potential region, a first MOS transistor, a second MOS transistor, and a ground potential region, the first MOS transistor and second MOS transistor each including a gate, a source and a drain, the gate of the first MOS transistor and the gate of the second MOS transistor being connected by gate wiring, with the gate wiring having a first gate terminal portion and a second gate terminal portion;a plurality of metal wiring lines, formed, with an insulating layer between, on the unit cells and;a plurality of contacts, that make electrical connection between the metal wiring lines and the first gate terminal portion, the second gate terminal portion, the source or the drain,wherein there is one of the plural contacts at each of the first gate terminal portion and the second gate terminal portion in one of the unit cells in which the source and the drain of the first MOS transistor and the source and the drain of the second MOS transistor are connected to the source potential region or to the ground potential region.

6. A gate array comprising: a plurality of unit cells, the unit cells arranged in parallel on a semiconductor substrate and having the same pattern including a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor each including a gate, a source and a drain, the gate of the first MOS transistor and the gate of the second MOS transistor being connected by gate wiring, with the gate wiring including a first gate terminal portion and a second gate terminal portion;a plurality of metal wiring lines, formed, with an insulating layer between, on the unit cells and;a plurality of contacts, that make electrical connection between the metal wiring lines and the first gate terminal portion, the second gate terminal portion, the source or the drain,wherein there is one of the plurality of contacts at each of the first gate terminal portion and the second gate terminal portion in one of the unit cells in which the source and the drain of the first MOS transistor are connected to the gate of the first MOS transistor and the source and the drain of the second MOS transistor are connected to the gate of the second MOS transistor.

7. The gate array of claim 1, wherein the first MOS transistor is a P channel MOS transistor, and the second MOS transistor is an N channel MOS transistor.

8. The gate array of claim 4, wherein the first MOS transistor is a P channel MOS transistor, and the second MOS transistor is an N channel MOS transistor.

9. The gate array of claim 5, wherein the first MOS transistor is a P channel MOS transistor, and the second MOS transistor is an N channel MOS transistor.

10. The gate array of claim 6, wherein the first MOS transistor is a P channel MOS transistor, and the second MOS transistor is an N channel MOS transistor.