Patent Application
20250131868
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0139803 under 35 USC ยง 119, filed on Oct. 18, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entireties.
The disclosure herein relates to a gate driver and a display apparatus including the gate driver. More particularly, the disclosure herein relates to the gate driver that stably outputs a gate output signal.
Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixels. The display panel driver includes a gate driver providing gate signals to the gate lines, a data driver providing data voltages to the data lines and a driving controller controlling the gate driver and the data driver.
Embodiments described hereinbelow provide a gate driver that stably outputs a gate output signal.
Embodiments described herein also provide a display apparatus that includes the gate driver.
In an embodiment of a gate driver, the gate driver includes a plurality of stages. At least one stage of the plurality of stages includes a first transistor including a control electrode configured to receive a clock signal, a first electrode configured to receive a previous stage gate output signal and a second electrode electrically connected to a Q node, a second transistor including a control electrode electrically connected to the Q node, a first electrode configured to receive a first power voltage and a second electrode electrically connected to a QB node, a third transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the QB node and a second electrode configured to receive a second power voltage, a fourth transistor including a control electrode electrically connected to the QB node, a first electrode configured to receive the first power voltage and a second electrode electrically connected to a GO node outputting a gate output signal, a fifth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the GO node and a second electrode configured to receive the second power voltage, a sixth transistor including a first electrode electrically connected to the GO node and a second electrode configured to receive the second power voltage and a first capacitor including a first electrode configured to receive the first power voltage and a second electrode electrically connected to the QB node.
In an embodiment, the sixth transistor may be an N-type transistor. The fifth transistor may be a P-type transistor.
In an embodiment, the sixth transistor may further include a control electrode electrically connected to the QB node.
In an embodiment, a ratio of a channel width to a channel length of the fifth transistor may be different from a ratio of a channel width to a channel length of the sixth transistor.
In an embodiment, the channel length of the sixth transistor may be longer than the channel length of the fifth transistor.
In an embodiment, the channel width of the sixth transistor may be narrower than the channel width of the fifth transistor.
In an embodiment, in a case that the gate output signal may have a low voltage, a turned-on state of the sixth transistor may be maintained.
In an embodiment, the least one stage may further include a ninth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive the first power voltage and a second electrode electrically connected to the Q node.
In an embodiment, the least one stage may further include a seventh transistor including a control electrode electrically connected to the Q node, a first electrode configured to receive a third power voltage and a second electrode electrically connected to an N node and an eighth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the N node and a second electrode configured to receive the second power voltage. The sixth transistor may further include a control electrode electrically connected to the N node.
In an embodiment, in a case that the gate output signal may have a low voltage, a turned-on state of the sixth transistor may be maintained.
In an embodiment, the third power voltage may be lower than the first power voltage.
In an embodiment, the least one stage may further include a ninth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive the first power voltage and a second electrode electrically connected to the Q node.
In an embodiment of a gate driver according to, the gate driver includes a plurality of stages. At least one stage of the plurality of stages includes a first transistor configured to apply a previous stage gate output signal to a Q node in response to a clock signal, a second transistor configured to apply a first power voltage to a QB node in response to a voltage of the Q node, a third transistor configured to apply a second power voltage to the QB node in response to the voltage of the Q node, a fourth transistor configured to apply the first power voltage to a GO node in response to a voltage of the QB node, a fifth transistor configured to apply the second power voltage to the GO node in response to the voltage of the Q node and a sixth transistor configured to apply the second power voltage to the GO node. The least one stage outputs a voltage of the GO node as a gate output signal. The sixth transistor is an N-type transistor.
In an embodiment, the sixth transistor may apply the second power voltage to the GO node in response to the voltage of the QB node.
In an embodiment, a ratio of a channel width to a channel length of the fifth transistor may be different from a ratio of a channel width to a channel length of the sixth transistor.
In an embodiment, the least one stage may further include a seventh transistor configured to apply a third power voltage lower than the first power voltage to an N node in response to the voltage of the Q node and an eighth transistor configured to apply the second power voltage to the N node in response to the voltage of the Q node. The sixth transistor may apply the second power voltage to the GO node in response to a voltage of the N node.
In an embodiment, the least one stage may further include a ninth transistor configured to apply the first power voltage to the Q node in response to an initialization signal.
In an embodiment, in a case that the gate output signal may have a low voltage, a turned-on state of the sixth transistor is maintained.
In an embodiment of a display apparatus, the display apparatus includes a display panel, a gate driver configured to apply a gate output signal to a gate line of the display panel and including a plurality of stages and a data driver configured to apply a data voltage to a data line of the display panel. At least one stage of the plurality of stages includes a first transistor including a control electrode configured to receive a clock signal, a first electrode configured to receive a previous stage gate output signal and a second electrode electrically connected to a Q node, a second transistor including a control electrode electrically connected to the Q node, a first electrode configured to receive a first power voltage and a second electrode electrically connected to a QB node, a third transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the QB node and a second electrode configured to receive a second power voltage, a fourth transistor including a control electrode electrically connected to the QB node, a first electrode configured to receive the first power voltage and a second electrode electrically connected to a GO node outputting the gate output signal, a fifth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the GO node and a second electrode configured to receive the second power voltage, a sixth transistor including a first electrode electrically connected to the GO node and a second electrode configured to receive the second power voltage and a first capacitor including a first electrode configured to receive the first power voltage and a second electrode electrically connected to the QB node. The sixth transistor is an N-type transistor.
In an embodiment, in a case that the gate output signal may have a low voltage, a turned-on state of the sixth transistor may be maintained.
According to the gate driver and the display apparatus including the gate driver, a pull down transistor of a pull downer included in the gate driver may be an N-type transistor, so that the gate output signal of the gate driver may be outputted stably not a voltage differ from a power voltage and a threshold voltage of the pull down transistor, but the power voltage.
Additionally, the pull down transistor is an N-type transistor, so that the gate output signal may be outputted stably as the power voltage in a case that the gate output signal has a low voltage in a low frame mode.
The above and other features and advantages of the present inventive concept will become more apparent by describing in detailed embodiments thereof with reference to the accompanying drawings, whereby sizes, thicknesses, ratios, and dimensions of the elements may be exaggerated for ease of description and for clarify, whereby like reference numbers and/or like reference characters refer to like elements, throughout, and in which:
Hereinafter, various embodiments will be described in more detail with reference to the accompanying drawings.
Referring to
The display panel 100 includes a display region configured to display an image and a peripheral region adjacent to the display region.
The display panel 100 includes a plurality of gate lines, a plurality of data lines and a pixel circuit P electrically connected to the gate lines and the data lines respectively. The gate lines may extend in a first direction D1 and the data lines may extend in a second direction D2 crossing the first direction D1.
The driving controller 200 receives an input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.
The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3 and a data signal DATA based on the input image data IMG and the input control signal CONT.
The driving controller 200 generates the first control signal CONT1 for controlling an operation of the gate driver 300 based on the input control signal CONT and outputs the generated first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.
The driving controller 200 generates the second control signal CONT2 for controlling an operation of the data driver 500 based on the input control signal CONT and outputs the generated second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.
The driving controller 200 generates the data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.
The driving controller 200 generates the third control signal CONT3 for controlling an operation of the gamma reference voltage generator 400 based on the input control signal CONT and outputs the generated third control signal CONT3 to the gamma reference voltage generator 400.
The gate driver 300 generates a gate output signal G[N] for driving the gate line in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate output signal G[N] to the gate lines.
In an embodiment, the gate driver 300 may be mounted on the peripheral region of the display panel 100. For example, the gate driver 300 may be integrated on the peripheral region of the display panel 100.
The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to each of the data signal DATA.
For example, the gamma reference voltage generator 400 may be disposed in the driving controller 200, or in the data driver 500.
The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver outputs a voltage data signal VDATA to the display panel 100.
In an embodiment, the data driver 500 may be mounted on the peripheral region of the display panel 100. For example, the data driver 500 may be integrated on the peripheral region of the display panel 100.
Referring to
The first transistor T1 may apply the previous stage gate output signal G[N-1] to the Q node Q in response to the clock signal CLK. The second transistor T2 may apply the first power voltage VDD1 to the QB node QB in response to a voltage of the Q node Q. The third transistor T3 may apply the second power voltage VSS to the QB node QB in response to the voltage of the Q node Q. The fourth transistor T4 may apply the first power voltage VDD1 to the GO node GO in response to a voltage of the QB node QB. The fifth transistor T5 may apply the second power voltage VSS to the GO node GO in response to the voltage of the Q node. The sixth transistor T6 may apply the second power voltage VSS to the GO node GO.
In an embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 may be P-type transistors. Additionally, in an embodiment, the third transistor T3 and the sixth transistor T6 may be N-type transistors.
A pull-down transistor of a conventional gate driver is P-type transistor, so that a gate output signal in which the conventional gate driver outputs a voltage increased by the threshold voltage of the pull-down transistor. In contrast, the gate driver 300 according an embodiment may include the sixth transistor T6. The sixth transistor T6 may be N-type transistor. The sixth transistor T6 may be N-type transistor, so that the gate output signal G[N] may not have voltage obtained by subtracting the threshold voltage of the sixth transistor T6 from the second power voltage VSS and may be stably outputted as the second power voltage VSS.
Referring to
In the first period TP1, the previous stage output signal G[N-1] may have the low voltage VGL and the clock signal CLK may have the low voltage VGL. In the first period TP1, the previous stage output signal G[N-1] having the low voltage VGL may applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned-on, the third transistor T3 may be turned-off and the fifth transistor T5 may be turned-on. The second transistor T2 may be turned-on, so that the first power voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-off and the sixth transistor T6 may be turned-on. The fourth transistor T4 may be turned-off and the fifth transistor T5 and sixth transistor T6 may be turned-on, so that the second power voltage VSS may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the low voltage VGL in the first period TP1.
In the second period TP2, the previous stage gate signal G[N-1] may have the high voltage VGH and the clock signal CLK may have the high level VGH. The second period TP2, a turned-off state of the first transistor T1 may be maintained in response to the clock signal CLK having the high voltage VGH. Accordingly, the gate output signal G[N] may have the low voltage VGL.
In the third period TP3, the previous stage gate output signal G[N-1] may have the high voltage VGH and the clock signal CLK may have the low voltage VGL. In the third period TP3, the previous stage gate output signal G[N-1] having the high voltage VGH may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be high voltage VGH. In response to the voltage of the Q node Q, the second transistor T2 may be turned-off, the third transistor T3 may be turned-on and the fifth transistor T5 may be turned-off. The third transistor T3 may be turned-on, so that the second power voltage VSS may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-on and the sixth transistor T6 may be turned-off. The fourth transistor T4 may be turned-off and the fifth transistor T5 and the sixth transistor T6 may be turned-off, so that the first power voltage VDD1 may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the high voltage VGH in the third period TP3.
The previous stage gate output signal G[N-1] may have the high voltage VGH in the fourth period TP4, so that the gate output signal G[N] may have the high voltage VGH.
In the fifth period TP5, the previous stage gate output signal G[N-1] may have the low voltage VGL, the clock signal CLK may have the high voltage VGH. The first transistor T1 may be turned-off in response to the clock signal CLK having the high voltage VGH. Accordingly, the gate output signal G[N] may have the high voltage VGH in the fifth period TP5.
In the sixth period TP6, the previous stage gate output signal G[N-1] may have the low voltage VGL, the clock signal CLK may have the low voltage VGL. In the sixth period TP6, the previous stage output signal G[N-1] having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned-on, the third transistor T3 may be turned-off and the fifth transistor T5 may be turned-on. The second transistor T2 may be turned-on, so that the first power voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-off and the sixth transistor T6 may be turned-on. The fourth transistor T4 may be turned-off and the fifth transistor T5 and sixth transistor T6 may be turned-on, so that the second power voltage VSS may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the low voltage VGL in the sixth period TP6.
In a case that the conventional gate driver is operated in the low frame rate mode, a gate output signal of the conventional gate driver may be inaccurate in the sixth period TP6 due to leakage current of transistors. In contrast, the gate driver 300 according to an embodiment may include the sixth transistor T6. The sixth transistor T6 may be N-type transistor. The sixth transistor T6 may be N-type transistor, so that the gate output signal G[N] may be stably outputted in the sixth period TP6.
In an embodiment, a ratio of a channel width to a channel length (W/L) of the sixth transistor T6 may be different from a ratio of a channel width to a channel length (W/L) of the fifth transistor T5. For example, an on-resistance of the sixth transistor T6 may be less than an on-resistance of the fifth transistor T5. Generally, an on-resistance of a transistor may refer to as a resistance that is the transistor having turned-on state. Additionally, the channel length of the sixth transistor T6 may be longer than the channel length of the fifth transistor T5. The channel width of the sixth transistor T6 may be narrower than the channel width of the fifth transistor T5.
The on-resistance of the sixth transistor T6 may be less than the on-resistance of the fifth transistor T5, so that a current may preferentially flows through the fifth transistor T5 in the sixth period TP6. Accordingly, in a case that the voltage of the GO node GO becomes a voltage obtained by subtracting a threshold voltage of the fifth transistor T5 from the low voltage VGL, the fifth transistor T5 may be turned-off. The fifth transistor T5 may be turned-off, so that a resistance of the fifth transistor T5 may be greater. The resistance of the fifth transistor T5 may be greater, so that the current may flow through the sixth transistor T6. The current may flow through the sixth transistor T6, so that the voltage of the GO node GO may be the low voltage VGL.
The on-resistance of the sixth transistor T6 is less than the on-resistance of the fifth transistor T5, the current flowing through the sixth transistor T6 may be decreased in the sixth period TP6. Accordingly, the stress applied to the sixth transistor T6 may be reduced. Accordingly, the reliability and the stability of the gate driver 300 may be improved.
A gate driver 300A is substantially same as the gate driver 300 of
Referring to
In an embodiment, the seventh transistor T7 may apply to the first power voltage VDD1 to the N node N in response to the voltage of the Q node Q. The eighth transistor T8 may apply to the second power voltage VSS to the N node N in response to the voltage of the Q node Q.
In the first period TP1, the previous stage output signal G[N-1] may have the low voltage VGL and the clock signal CLK may have the low voltage VGL. In the first period TP1, the previous stage output signal G[N-1] having the low voltage VGL may applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned-on, the third transistor T3 may be turned-off, the fifth transistor T5 may be turned-on, the seventh transistor T7 may be turned-on and the eighth transistor T8 may be turned-off. The seventh transistor T7 may be turned-on, so that the first power voltage VDD1 may be applied to the N node N. The second transistor T2 may be turned-on, so that the first power voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-off. The sixth transistor T6 may be turned-on in response to a voltage of the N node N having the high voltage VGH. The fourth transistor T4 may be turned-off and the fifth transistor T5 and sixth transistor T6 may be turned-on, so that the second power voltage VSS may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the low voltage VGL in the first period TP1.
In the second period TP2, the previous stage gate signal G[N-1] may have the high voltage VGH and the clock signal CLK may have the high level VGH. The second period TP2, the turned-off state of the first transistor T1 may be maintained in response to the clock signal CLK having the high voltage VGH. Accordingly, the gate output signal G[N] may have the low voltage VGL.
In the third period TP3, the previous stage gate output signal G[N-1] may have the high voltage VGH and the clock signal CLK may have the low voltage VGL. In the third period TP3, the previous stage gate output signal G[N-1] having the high voltage VGH may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be high voltage VGH. In response to the voltage of the Q node Q, the second transistor T2 may be turned-off, the third transistor T3 may be turned-on, the fifth transistor T5 may be turned-off, the seventh transistor T7 may be turned-off and the eighth transistor T8 may be turned-on. The seventh transistor T7 may be turned-off and the eighth transistor T8 may be turned-on, so that the second power voltage VSS may be applied to the N node N. The sixth transistor T6 may be turned-off in response to the N node having the second power voltage VSS. The third transistor T3 may be turned-on, so that the second power voltage VSS may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-on. The fourth transistor T4 may be turned-off and the fifth transistor T5 and the sixth transistor T6 may be turned-off, so that the first power voltage VDD1 may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the high voltage VGH in the third period TP3.
The previous stage gate output signal G[N-1] may have the high voltage VGH in the fourth period TP4, so that the gate output signal G[N] may have the high voltage VGH.
In the fifth period TP5, the previous stage gate output signal G[N-1] may have the low voltage VGL, the clock signal CLK may have the high voltage VGH. The first transistor T1 may be turned-off in response to the clock signal CLK having the high voltage VGH. Accordingly, the gate output signal G[N] may have the high voltage VGH in the fifth period TP5.
In the sixth period TP6, the previous stage gate output signal G[N-1] may have the low voltage VGL, the clock signal CLK may have the low voltage VGL. In the sixth period TP6, the previous stage output signal G[N-1] having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Accordingly, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned-on, the third transistor T3 may be turned-off, the fifth transistor T5 may be turned-on, the seventh transistor T7 may be turned-on and the eighth transistor T8 may be turned-off. The seventh transistor T7 may be turned-on, so that the first power voltage VDD1 may be applied to the N node N. The second transistor T2 may be turned-on, so that the first power voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned-off and the sixth transistor T6 may be turned-on. The fourth transistor T4 may be turned-off and the fifth transistor T5 and sixth transistor T6 may be turned-on, so that the second power voltage VSS may be applied to the GO node GO. Accordingly, the gate output signal G[N] may have the low voltage VGL in the sixth period TP6.
In a case that the conventional gate driver is operated in the low frame rate mode, a gate output signal of the conventional gate driver may be inaccurate in the sixth period TP6 due to leakage current of transistors. In contrast, the gate driver 300 according to an embodiment may include the sixth transistor T6. The sixth transistor T6 may be N-type transistor. The sixth transistor T6 may be N-type transistor, so that the gate output signal G[N] may be stably output in the sixth period TP6.
A gate driver 300B is substantially same as the gate driver 300A of
Referring to
In an embodiment, the third power voltage VDD2 may be lower than the first power voltage VDD1. For example, the third power voltage VDD2 may be lower than the high voltage VGH.
The third power voltage VDD2 may be lower than the high voltage VGH, so that the control electrode of the sixth transistor T6 may receive a voltage lower than the high voltage VGH. Accordingly, a stress applied to the sixth transistor T6 may be reduced. Accordingly, the stability and the reliability of the gate driver 300B may be further improved.
A gate driver 300C is substantially same as the gate driver 300 of
Referring to
In an embodiment, in a case that the initialization signal NESR has an activation level, the first power voltage VDD1 may be applied to the Q node Q. Accordingly, in a case that the initialization signal NESR has the activation level, the gate output signal G[N] of the gate driver 300C may have the high voltage VGH.
In an embodiment, the initialization signal NESR may be a global signal applied to all stages of the gate driver 300C. Accordingly, the gate output signals G[N] of the all stages of the gate driver 300C may have the high voltage VGH.
A gate driver 300D is substantially same as the gate driver 300B of
Referring to
In an embodiment, in a case that the initialization signal NESR has the activation level, the first power voltage VDD1 may be applied to the Q node Q. Accordingly, in a case that the initialization signal NESR has the activation level, the gate output signal G[N] of the gate driver 300D may have the high voltage VGH.
In an embodiment, the initialization signal NESR may be a global signal applied to all stages of the gate driver 300D. Accordingly, the gate output signals G[N] of the all stages of the gate driver 300D may have the high voltage VGH.
Referring to
According to an embodiment, as shown in
The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a micro-processor, a central processing unit (CPU), an application processor (AP) and the like. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, the processor 1010 may be coupled to an extended bus such as a peripheral component interconnection (PCI) bus.
The processor 1010 may output the input image data IMG and the input control signal CONT to the driving controller 200 of
The memory device 1020 may store data for operations of the electronic apparatus 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device and the like and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device and the like.
The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device and the like. The I/O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touch-pad, a touch-screen and the like and an output device such as a printer, a speaker and the like. In some embodiments, the display device 1060 may be included in the I/O device 1040. The power supply 1050 may provide power for operations of the electronic apparatus 1000. The display device 1060 may be coupled to other components via the buses or other communication links.
According to a gate driver and a display apparatus including the gate driver, the display apparatus that stably outputs the gate output signal may be provided.
The foregoing is illustrative of the present inventive concept and is not to be construed as limiting thereof. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the disclosure. Accordingly, all such modifications are intended to be included within the spirit and scope of the disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present inventive concept and is not to be construed as limited to the specific embodiments disclosed and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The disclosure is defined by the following claims, with equivalents of the claims to be included therein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0139803 | Oct 2023 | KR | national |
