Patent Application
20230043062
This application claims priority from Republic of Korea Patent Application No. 10-2021-0102699 filed on Aug. 4, 2021, which is hereby incorporated by reference in its entirety.
The present disclosure relates to a gate driver circuit and a method for driving the same.
In general, a display device includes a display panel, a display driving device, a timing controller, and the like.
The display driving device converts digital image data provided by the timing controller into a source signal, and provides the source signal to the display panel. The display driving device may include a gate driver integrated into a chip.
The gate driver serves to drive a gate line by transmitting a gate driving signal to the display panel.
In order for the display panel to output a normal image, a method in which a system circuit dynamically controls and adjusts the output of the gate driver is required. However, such a method may cause the system circuit to consume a large amount of power. Thus, in order to solve such a problem, a charge sharing function may be used.
Under such a background, in one aspect, various embodiments are directed to providing a circuit suitable for reducing power consumption by automatically applying a charge sharing function according to an operation of a clock signal without directly designating a channel in which the charge sharing function is performed, and a method for driving the same.
In one aspect, the present embodiment may provide a gate driver circuit including: a control circuit configured to output gate clock signals and connection control signals; a plurality of buffers configured to respectively receive the gate clock signals and to output the gate clock signals; and a plurality of charge sharing switches configured to respectively control connections between output ends of the buffers so as to connect selected buffers among the plurality of buffers through a charge sharing line and to be controlled respectively by the connection control signals.
In another aspect, the present embodiment may provide a gate driver circuit, including: a control circuit to output gate clock signals and connection control signals; a first buffer to receive a first gate clock signal from the control circuit and to output the first gate clock signal; a second buffer to receive a second gate clock signal from the control circuit and to output the second gate clock signal; a first charge sharing switch connected to an output end of the first buffer and controlled by the connection control signal; a second charge sharing switch connected with an output end of the second buffer, connected with the first charge sharing switch through a charge sharing line, and controlled by the connection control signal.
In still another aspect, the present embodiment may provide a method for driving a gate driver circuit, including: transmitting gate clock signals respectively to a plurality of buffers; transmitting a first gate clock signal and a second gate clock signal respectively to a first buffer and a second buffer among the plurality of buffers; turning on charge sharing switches corresponding to an output end of the first buffer and an output end of the second buffer when the first gate clock signal and the second gate clock signal are respectively in different edge states; and connecting the output end of the first buffer and the output end of the second buffer through a charge sharing line.
In still another aspect, the present embodiment may provide a method for driving a gate driver circuit, including: transmitting a first gate clock signal to a first buffer; transmitting a second gate clock signal to a second buffer; turning on the first charge sharing switch connected with the first buffer and the second charge sharing switch connected with the second buffer when the first gate clock signal and the second gate clock signal are respectively in different edge states; and connecting an output end of the first buffer and an output end of the second buffer through a charge sharing line.
As is apparent from the above, according to the present embodiments, it is possible to select a channel, in which charge sharing is to be adaptively achieved according to the phase of a clock signal. Furthermore, according to the present embodiments, power consumed by a display device when a gate line is driven is reduced.
Referring to
In the panel 110, a plurality of data lines DL and a plurality of gate lines GL may be disposed, and a plurality of pixels P may be disposed.
The circuits, which drive at least one configuration included in the panel 110, may be referred to as panel driving circuits. For example, the data driving circuit 120, the gate driving circuit 130, the data processing circuit 140, and the like may be referred to as panel driving circuits.
Each of the aforementioned data driving circuit 120, gate driving circuit 130, and data processing circuit 140 may be referred to as a panel driving circuit, and all or a plurality of circuits may be referred to as a panel driving circuit.
The data driving circuit 120 may drive the plurality of data lines DL.
The gate driving circuit 130 may drive the plurality of gate lines GL by supplying a scan signal (also referred to as a ‘gate signal’) to the plurality of gate lines GL.
The data processing circuit 140 may control the data driving circuit 120 and the gate driving circuit 130 by supplying various control signals to the data driving circuit 120 and the gate driving circuit 130.
In the panel driving circuit, the gate driving circuit 130 may supply a scan signal having a turn-on voltage or a turn-off voltage to the gate line GL. When the scan signal having the turn-on voltage is supplied to a pixel P, the pixel P is connected to the data line DL, and when the scan signal having the turn-off voltage is supplied to the pixel P, the pixel P is disconnected from the data line DL.
In the panel driving circuit, the data driving circuit 120 supplies a data voltage to the data line DL. The data voltage supplied to the data line DL is transferred to the pixel P, which is connected to the data line DL, according to the scan signal.
In the panel driving circuit, the data processing circuit 140 may supply various control signals to the gate driving circuit 130 and the data driving circuit 120. The data processing circuit 140 may generate a gate control signal GCS for staring a scan according to a timing implemented in each frame, and transmit the gate control signal GCS to the gate driving circuit 130. Furthermore, the data processing circuit 140 may output, to the data driving circuit 120, image data RGB obtained by converting externally inputted image data according to a data signal format used by the data driving circuit 120. Furthermore, the data processing circuit 140 may transmit a data control signal DCS for controlling the data driving circuit 120 to supply a data voltage to each pixel P according to each timing.
Meanwhile, the data driving circuit 120 may be referred to as a source driver. Also, the gate driving circuit 130 may be referred to as a gate driver. Also, the data processing circuit 140 may be referred to as a timing controller.
Although the present embodiment is not limited by such names, descriptions of some components generally known in the source driver, the gate driver, the timing controller, and the like will be omitted from the description of the following embodiment. Accordingly, in understanding the embodiment, it is necessary to consider that these some components have been omitted.
Referring to
The circuit 200 for a gate driver may include lines SW1, SW2, , SWM that connect the control circuit 210 and input ends of the plurality of buffers 220_1, 220_2, . . . , 220_M, respectively, so that the plurality of buffers 220_1, 220_2, . . . , 220_M and the control circuit 210 are connected, and charge sharing switch control lines SW_1, SW_2, . . . , SW_M that connect the control circuit 210 and the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M in order to control the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M.
The output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M may be connected to the panel 110. When viewed from the output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M, the panel 110 connected to the output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M may be understood as a panel load 250 including a resistor R and a capacitor C, and it may be understood that a plurality of panel loads 250_1, 250_2, . . . , 250_M are connected to the plurality of buffers 220_1, 220_2, . . . , 220_M, respectively.
It may be understood that the plurality of panel loads 250_1, 250_2, . . . , 250_M are connected to the output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M and the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M, and lines for connecting the plurality of panel loads 250_1, 250_2, . . . , 250_M and the output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M may be connected to the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M. Therefore, it may be understood that the plurality of panel loads 250_1, 250_2, . . . , 250_M, the plurality of buffers 220_1, 220_2, . . . , 220_M, and the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M are connected through one node.
A timing controller 150 may generate an on-clock signal and an off-clock signal and transmit the generated on-clock signal and off-clock signal to the control circuit 210, which is included in the circuit 200 for a gate driver, in order to control the circuit 200 for a gate driver.
The control circuit 210 may receive the on-clock signal and the off-clock signal from the timing controller 150 separately provided outside the circuit 200 for a gate driver, and generate the gate clock signals GCLK on the basis of the on-clock signal and the off-clock signal received from the timing controller 150.
The control circuit 210 may sequentially transmit the generated gate clock signals GCLK to the plurality of buffers 220_1, 220_2, . . . , 220_M. Accordingly, phases of the respective gate clock signals GCLK transmitted to the plurality of buffers 220_1, 220_2, . . . , 220_M are not the same as one another.
The control circuit 210 may generate the connection control signals CCS, and transmit the connection control signals CCS to the charge sharing switches 230_1, 230_2, . . . , 230_M through the charge sharing switch control lines SW_1, SW_2, . . . , SW_M that control the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M, thereby controlling the on/off of the charge sharing switches 230_1, 230_2, . . . , 230_M.
The control circuit 210 may determine whether to transmit the connection control signals CCS to the charge sharing switches 230_1, 230_2, . . . , 230_M, which correspond to the plurality of buffers 220_1, 220_2, . . . , 220_M, respectively, according to the phases of the gate clock signals GCLK transmitted to the plurality of buffers 220_1, 220_2, . . . , 220_M, respectively.
The control circuit 210 may include a counting circuit that counts the number of on-clock signal pulses between an initial on-clock signal pulse and an initial off-clock signal pulse transmitted by the timing controller 150. Since the counting circuit provided in the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150, it can be deemed that the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150.
The respective input ends of the plurality of buffers 220_1, 220_2, . . . , 220_M may be connected to the control circuit 210 through the lines SW1, SW2, . . . , SWM that connect the plurality of buffers 220_1, 220_2, . . . , 220_M, and the plurality of buffers 220_1, 220_2, . . . , 220_M may receive the gate clock signals GCLK from the control circuit 210, and amplify the gate clock signals GCLK to output the amplified gate clock signals GCLK.
The output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M may be, respectively connected to the plurality of panel loads 250_1, 250_2, . . . , 250_M and the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M through one node.
The buffer 220_1 may include a PMOS transistor QP1 and a NMOS transistor QN1, the buffer 220_2 may include a PMOS transistor QP2 and a NMOS transistor QN2, and the buffer 220_M may include a PMOS transistor QPM and a NMOS transistor QNM.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may be, respectively connected to the output ends of the plurality of buffers 220_1, 220_2, . . . , 220_M and the plurality of panel loads 250_1, 250_2, . . . , 250_M through one node.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may be interconnected by the charge sharing line 240.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may be turned on and off by the connection control signal CCS received from the control circuit 210 through the charge sharing switch control lines SW_1, SW_2, . . . , SW_M.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may each include a transistor.
The charge sharing line 240 may include one line that connects the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M.
The charge sharing line 240 may serve to connect an output end of a buffer, which outputs a gate clock signal GCLK in a falling edge state, and an output end of a buffer, which outputs a gate clock signal GCLK in a rising edge state, and thus charge sharing is achieved. Here, the falling edge may refer to a state in which a signal value is reduced from a specific value in a clock signal. For example, the falling edge may mean a moment where the value of a clock signal is changed from 1 to 0. The rising edge may refer to a state in which a signal value rises to a specific value in a clock signal. For example, the rising edge may mean a moment where the value of a clock signal is changed from 0 to 1.
Since the charge sharing line 240 includes one line, the configuration of the circuit can be simplified.
The related art has a problem in that since a charge sharing function is performed by inputting a separate signal to each channel in which charge sharing is desired to be achieved, a user needs to directly designate a channel in which the charge sharing function is to be performed.
However, in the present embodiment, the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may be connected through the one charge sharing line 240, and the control circuit 210 may control the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M by using the phase of a clock signal and adaptively select an output end of a buffer in which a charge sharing function is to be performed.
Referring to
It may be determined which of the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M are to be turned on by the control circuit 210, according to the phase of the gate clock signal GCLK received by output ends of a first buffer 220_a and a second buffer 220_b among the plurality of buffers 220_1, 220_2, . . . , 220_M connected to the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M, respectively. The first buffer 220_a and the second buffer 220_b may be selected from among the plurality of buffers 220_1, 220_2, . . . , 220_M.
Specifically, a first gate clock signal and a second gate clock signal may be transmitted to the first buffer 220_a and the second buffer 220_b, respectively among the plurality of buffers 220_1, 220_2, . . . , 220_M, and the charge sharing switches 230_a and 230_b corresponding to the output end of the first buffer 220_a and an output end of the second buffer 220_b may be turned on when the first gate clock signal and the second gate clock signal are in different edge states.
In accordance with an embodiment related to the above, the first gate clock signal and the second gate clock signal may be transmitted to the first buffer 220_a and the second buffer 220_b, respectively among the plurality of buffers 220_1, 220_2, . . . , 220_M, and when the first gate clock signal is in a falling edge state and the second gate clock signal is in a rising edge state, the control circuit 210 may turn on the charge sharing switches 230_a and 230_b corresponding to the output end of the first buffer 220_a and the output end of the second buffer 220_b. Then, when the first gate clock signal is in a rising edge state and the second gate clock signal is in a falling edge state at the same time, the control circuit 210 may turn on the charge sharing switches 230_a and 230_b corresponding to the output end of the first buffer 220_a and the output end of the second buffer 220_b.
As the first charge sharing switch 230_a connected to the first buffer 220_a and the second charge sharing switch 230_b connected to the second buffer 220_b are turned on by the control circuit 210, the output ends of the first buffer 220_a and the second buffer 220_b are connected to each other through the charge sharing line 240, so that the charge sharing function may be performed.
Accordingly, a user does not directly select a channel in which the charge sharing function is to be performed, and may adaptively select the channel according to the phase of a clock signal.
The control circuit 210 may include the counting circuit that counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150. Since the counting circuit provided in the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150, it can be deemed that the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150.
Since the gate clock signals GCLK generated by the control circuit 210 have an interval between the initial on-clock signal pulse and the initial off-clock signal pulse and are sequentially transmitted to the plurality of buffers 220_1, 220_2, . . . , 220_M at a predetermined cycle, it is possible to predict and determine the first gate clock signal and the second gate clock signal having different edge states by counting the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150.
In accordance with an embodiment related to the above, it is possible to predict and determine the first buffer 220_a that receives the first gate clock signal in a falling edge state and the second buffer 220_b that receives the second gate clock signal in a rising edge state at the same time, and it is possible to predict and determine the first buffer 220_a that receives the first gate clock signal in a rising edge state and the second buffer 220_b that receives the second gate clock signal in a falling edge state at the same time.
Accordingly, when the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse is n (n is a positive integer), the second gate clock signal may be a gate clock signal that is outputted at an n+1th time after the first gate clock signal is outputted.
The turned-on charge sharing switches 230_a and 230_b allow the output ends of the buffers 220_a and 220_b, which are connected to the turned-on charge sharing switches 230_a and 230_b, respectively, to be connected to each other through the charge sharing line 240.
When the output end of the first buffer 220_a and the output end of the second buffer 220_b are electrically balanced through the charge sharing, the control circuit 210 may turn off the charge sharing switch 230_a connected to the output end of the first buffer 220_a and the charge sharing switch 230_b connected to the output end of the second buffer 220_b.
The timing controller 150 generates an on-clock signal ONCLK and an off-clock signal OFFCLK and transmits the generated on-clock signal ONCLK and off-clock signal OFFCLK to the control circuit 210. The control circuit 210 may receive the on-clock signal ONCLK and the off-clock signal OFFCLK, generate the gate clock signals GCLK on the basis of the received signals, and transmit the generated gate clock signals GCLK to the input ends of the plurality of buffers 220_1, 220_2, . . . , 220_M, respectively, and the plurality of buffers 220_1, 220_2, . . . , 220_M may amplify the received gate clock signals GCLK to output the amplified signals.
The gate clock signals GCLK generated by the control circuit 210 may have an interval between an initial on-clock signal pulse and an initial off-clock signal pulse.
Referring to
In accordance with an embodiment related to the above, at the time t4 at which a first buffer receives a first gate clock signal GCLK1 in a falling edge state among the amplified gate clock signals GCLK outputted by the plurality of buffers 220_1, 220_2, . . . , 220_M, charge sharing switches connected to an output end of a second buffer, which receives a second gate clock signal GCLK4 in a rising edge state, are turned on, and an output end of the first buffer and the output end of the second buffer are connected to each other through the charge sharing line 240, so that charge sharing can be achieved.
A first gate clock signal and a second gate clock signal may be transmitted to the first buffer 220_a and the second buffer 220_b, respectively, among the plurality of buffers 220_1, 220_2, . . . , 220_M, and the charge sharing switches 230_a and 230_b corresponding to the output end of the first buffer 220_a and the output end of the second buffer 220_b may be turned on when the first gate clock signal and the second gate clock signal are in different edge states.
Referring to
The control circuit 210 may include the counting circuit that counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150. Since the counting circuit provided in the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150, it can be deemed that the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150.
The counting circuit included in the control circuit 210 may count the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse, and predict and calculate an output end of a buffer to be connected, on the basis of the counting information and the fact that the gate clock signals GCLK are sequentially transmitted to the plurality of buffers 220_1, 220_2, . . . , 220_M.
Referring to
In accordance with an embodiment related to the above, when it is assumed that there are n on-clock signal pulses (n is a positive integer) between the initial on-clock signal pulse and the initial off-clock signal pulse generated by the timing controller 150 and transmitted to the control circuit 210, a second gate clock signal in a rising edge state may be a gate clock signal that is outputted at an n+1th time after a first gate clock signal in a falling edge state is outputted. The first gate clock signal may be a signal generated at t1 and the second gate clock signal may be a signal generated at tn+2. Alternatively, they may be arbitrary two gate clock signals having the same interval.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230 M may each include a transistor, and even though the output ends of the buffers 220_1, 220_2, . . . , 220_M respectively connected to the charge sharing switches 230_1, 230_2, . . . , 230_M turned on by the on resistance of the transistors are connected to one another through the charge sharing line 240, the waveform of a charge-shared gate clock signal GCLK may have a gentle curve.
Referring to
Furthermore, charge sharing is achieved between output end of a buffer, which amplifies a gate clock signal in a falling edge state to output the amplified signal, and an output end of a buffer that outputs a gate clock signal at a low level as illustrated in (b) of
Accordingly, as illustrated in (c) of
As a gate clock signal GCLK at a high level and a gate clock signal GCLK at a low level are electrically balanced, a driving voltage of the gate clock signal GCLK due to charge sharing has a smaller value than when charge sharing is not achieved. Thus, in the display device 100 including the circuit 200 for a gate driver in accordance with the present embodiment, power consumed when the gate line GL is driven can be significantly reduced.
Referring to
The plurality of buffers 220_1, 220_2, . . . , 220_M may receive voltages from a first voltage source V1 and a second voltage source V2 in order to amplify the gate clock signal GCLK to output the amplified gate clock signal GCLK.
The PMOS transistor may include a gate end connected to the input end of each of the plurality of buffers 220_1, 220_2, . . . , 220_M, a source end connected to the first voltage source V1, and a drain end connected to the output end of each of the plurality of buffers 220_1, 220_2, . . . , 220 M.
The NMOS transistor may include a gate end connected to the input end of each of the plurality of buffers 220_1, 220_2, . . . , 220_M, a source end connected to the second voltage source V2, and a drain end connected to the output end of each of the plurality of buffers 220_1, 220_2, . . . , 220_M.
Referring to
An on-clock signal and an off-clock signal may be generated and outputted by the timing controller 150, and the control circuit 210 may receive the on-clock signal and the off-clock signal and generate and output a gate clock signal GCLK having an interval from an initial on-clock signal pulse to an initial off-clock signal pulse.
The control circuit 210 may be connected to the plurality of buffers 220_1, 220_2, . . . , 220_M through the input ends of the respective buffers.
The circuit driving method in accordance with the present embodiment may include a step S804 of predicting and determining buffers to which a first gate clock signal and a second gate clock signal in a falling edge state and a rising edge state, respectively, at the same time among the gate clock signals GCLK are transmitted.
The control circuit 210 may include the counting circuit that counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse, and may understand an interval of the gate clock signal GCLK by counting the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse. Since the counting circuit provided in the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150, it can be deemed that the control circuit 210 counts the number of on-clock signal pulses between the initial on-clock signal pulse and the initial off-clock signal pulse transmitted by the timing controller 150.
Accordingly, it is possible to predict and determine an output end of a buffer, in which charge sharing is to be achieved, through the cycle of the gate clock signals GCLK sequentially transmitted and the interval of the gate clock signal GCLK.
The circuit driving method in accordance with the present embodiment may include a step S806 of turning on a first charge sharing switch and a second charge sharing switch corresponding to the output ends of buffers that receive the first gate clock signal and the second gate clock signal in the falling edge state and the rising edge state.
The first charge sharing switch and the second charge sharing switch may be turned on and off by the connection control signal CCS received from the control circuit 210.
The circuit driving method in accordance with the present embodiment may include a step S808 of connecting an output end of a first buffer and an output end of a second buffer through the charge sharing line 240.
The charge sharing line 240 may include a single line, and connect the plurality of charge sharing switches 230_1, 230_2, . . . , 230_M.
The plurality of charge sharing switches 230_1, 230_2, . . . , 230_M may each include a transistor, and when a charge sharing function is exhibited by the on resistance of the transistor, the waveform of a charge-shared gate clock signal GCLK may have a gentle curve.
The circuit driving method in accordance with the present embodiment may include a step S810 of turning off the first charge sharing switch and the second charge sharing switch connected to the first buffer and the second buffer, respectively, when the output end of the first buffer and the output end of the second buffer are electrically balanced.
As a gate clock signal GCLK at a high level and a gate clock signal GCLK at a low level are electrically balanced, a driving voltage of the gate clock signal GCLK due to charge sharing has a smaller value than when charge sharing is not achieved. Thus, in the display device 100 using the circuit driving method in accordance with the present embodiment, power consumed when the gate line GL is driven can be significantly reduced.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0102699 | Aug 2021 | KR | national |
