Patent Application
20250211091
The present disclosure generally relates to a gate driver circuit, a power conversion system, and a gate driving method. More particularly, the present disclosure relates to a gate driver circuit for controlling the ON/OFF states of switching elements each including a gate terminal, a power conversion system including such a gate driver circuit, and a gate driving method for use in such a power conversion system.
Patent Literature 1 discloses a semiconductor power conversion apparatus including, for each phase, a pair of switching elements, of which the ON/OFF states are controlled to satisfy a mutually exclusive relationship with each other. The semiconductor power conversion apparatus of Patent Literature 1 further includes a gate interlocking circuit. When a gate reference signal applied to one of the pair of switching elements rises from zero to one while a gate feedback signal applied to the other switching element is zero, the gate interlocking circuit turns the one switching element from OFF to ON. In addition, once the one switching element has turned ON, the gate interlocking circuit keeps the one switching element ON until the gate reference signal falls from one to zero.
The semiconductor power conversion apparatus (power conversion system) of Patent Literature 1 may cause inconvenience depending on the combination of two or more switching elements which turn ON simultaneously and do not satisfy the mutually exclusive relationship with each other. In addition, in the semiconductor power conversion apparatus of Patent Literature 1, the gate interlocking circuit consists of only logic circuits, and therefore, may have a relatively large circuit size.
An object of the present disclosure is to provide a gate driver circuit, a power conversion system, and a gate driving method, all of which have the ability to reduce the chances of causing any inconvenience while reducing an increase in the circuit size.
A gate driver circuit according to an aspect of the present disclosure controls ON/OFF states of a first switching element, a second switching element, a third switching element, and a fourth switching element included in a power converter circuit. The power converter circuit includes the first switching element, the second switching element, the third switching element, and the fourth switching element, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode. The first, second, third, and fourth switching elements each have a gate terminal, and are connected in series between a positive electrode and a negative electrode of a DC power supply. The first diode is connected in anti-parallel to the first switching element. The second diode is connected in anti-parallel to the second switching element. The third diode is connected in anti-parallel to the third switching element. The fourth diode is connected in anti-parallel to the fourth switching element. The fifth diode has a cathode connected to a connection node between the first switching element and the second switching element and an anode connected to an intermediate potential node of the DC power supply. The sixth diode has an anode connected to a connection node between the third switching element and the fourth switching element and a cathode connected to the intermediate potential node of the DC power supply. The gate driver circuit includes a signal generator, a signal interrupter, a first interlocker, a second interlocker, and a signal outputter. The signal generator generates a first gate signal to be applied to the gate terminal of the first switching element, a second gate signal to be applied to the gate terminal of the second switching element, a third gate signal to be applied to the gate terminal of the third switching element, and a fourth gate signal to be applied to the gate terminal of the fourth switching element. The signal interrupter interrupts, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator to the power converter circuit. The first interlocker controls the power converter circuit to prevent the first switching element and the third switching element from turning ON simultaneously. The second interlocker controls the power converter circuit to prevent the second switching element and the fourth switching element from turning ON simultaneously. The signal outputter outputs the interruption signal to the signal interrupter either when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level or when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
A power conversion system according to another aspect of the present disclosure includes the gate driver circuit described above and the power converter circuit described above.
A gate driving method according to still another aspect of the present disclosure is a method for controlling ON/OFF states of a first switching element, a second switching element, a third switching element, and a fourth switching element included in a power converter circuit. The power converter circuit includes the first switching element, the second switching element, the third switching element, and the fourth switching element, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode. The first, second, third, and fourth switching elements each have a gate terminal, and are connected in series between a positive electrode and a negative electrode of a DC power supply. The first diode is connected in anti-parallel to the first switching element. The second diode is connected in anti-parallel to the second switching element. The third diode is connected in anti-parallel to the third switching element. The fourth diode is connected in anti-parallel to the fourth switching element. The fifth diode has a cathode connected to a connection node between the first switching element and the second switching element and an anode connected to an intermediate potential node of the DC power supply. The sixth diode has an anode connected to a connection node between the third switching element and the fourth switching element and a cathode connected to the intermediate potential node of the DC power supply. The gate driving method includes a signal generating step, a second interruption step, a first interlocking step, a second interlocking step, and a signal outputting step. The signal generating step includes generating a first gate signal to be applied to the gate terminal of the first switching element, a second gate signal to be applied to the gate terminal of the second switching element, a third gate signal to be applied to the gate terminal of the third switching element, and a fourth gate signal to be applied to the gate terminal of the fourth switching element. The signal interrupting step includes interrupting, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that have been generated in the signal generating step to prevent the first, second, third, and fourth gate signals from being applied to the power converter circuit. The first interlocking step includes controlling the power converter circuit to prevent the first switching element and the third switching element from turning ON simultaneously. The second interlocking step includes controlling the power converter circuit to prevent the second switching element and the fourth switching element from turning ON simultaneously. The signal outputting step includes outputting the interruption signal either when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level or when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
A gate driver circuit, a power conversion system, and a gate driving method according to an exemplary embodiment will now be described with reference to the accompanying drawings. The drawings to be referred to in the following description of embodiments are all schematic representations. Thus, the ratio of the dimensions (including thicknesses) of respective constituent elements illustrated on the drawings does not always reflect their actual dimensional ratio. Note that the exemplary embodiment to be described below is only an exemplary one of various embodiments of the present disclosure and should not be construed as limiting. Rather, the exemplary embodiment may be readily modified in various manners depending on a design choice or any other factor without departing from the scope of the present disclosure.
First of all, an overview of a gate driver circuit 1 and power conversion system 10 according to an exemplary embodiment will be described with reference to
The gate driver circuit 1 shown in
The inverter circuit 2 is a multi-level inverter, and more specifically, a three-level inverter of a diode-clamped type. A power conversion system 10 according to an exemplary embodiment includes the gate driver circuit 1 and the inverter circuit 2. That is to say, the power conversion system 10 includes the gate driver circuit 1 and the power converter circuit 21. In this embodiment, the power conversion system 10 includes a plurality of gate driver circuits 1 (only one of which is shown in
The gate driver circuit 1 according to the exemplary embodiment is a gate driver circuit 1 for controlling the ON/OFF states of the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 included in the power converter circuit 21.
The power converter circuit 21 includes the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14, a first diode D11, a second diode D12, a third diode D13, a fourth diode D14, a fifth diode D15, and a sixth diode D16.
The first, second, third, and fourth switching elements Q11, Q12, Q13, Q14 each have a gate terminal G11, G12, G13, G14, and are connected in series between a positive electrode P1 and a negative electrode N1 of a DC power supply 3. The first diode D11 is connected in anti-parallel to the first switching element Q11. The second diode D12 is connected in anti-parallel to the second switching element Q12. The third diode D13 is connected in anti-parallel to the third switching element Q13. The fourth diode D14 is connected in anti-parallel to the fourth switching element Q14. The fifth diode D15 has a cathode connected to a connection node P11 between the first switching element Q11 and the second switching element Q12 and an anode connected to an intermediate potential node M1 of the DC power supply 3. The sixth diode D16 has an anode connected to a connection node P13 between the third switching element Q13 and the fourth switching element Q14 and a cathode connected to the intermediate potential node M1 of the DC power supply 3.
The gate driver circuit 1 includes a signal generator 11, a signal interrupter 12, a first interlocker 15, a second interlocker 16, and a signal outputter 13.
The signal generator 11 generates a first gate signal to be applied to the gate terminal G11 of the first switching element Q11, a second gate signal to be applied to the gate terminal G12 of the second switching element Q12, a third gate signal to be applied to the gate terminal G13 of the third switching element Q13, and a fourth gate signal to be applied to the gate terminal G14 of the fourth switching element Q14. The signal interrupter 12 interrupts, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21. The first interlocker 15 controls the power converter circuit 21 to prevent the first switching element Q11 and the third switching element Q13 from turning ON simultaneously. The second interlocker 16 controls the power converter circuit 21 to prevent the second switching element Q12 and the fourth switching element Q14 from turning ON simultaneously. The signal outputter 13 outputs the interruption signal to the signal interrupter 12 when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level. The signal outputter 13 also outputs the interruption signal to the signal interrupter 12 when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
In the gate driver circuit 1 according to this embodiment, the signal outputter 13 outputs the interruption signal to the signal interrupter 12 in any of the two situations described above. Then, on receiving the interruption signal, the signal interrupter 12 interrupts the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21. This allows the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 to be turned OFF in any of the two situations described above. Consequently, this may reduce the chances of causing inconvenience in any of the situations described above. In addition, the gate driver circuit 1 according to this embodiment allows the signal outputter 13 to deal with the inconvenience that cannot be handled by the first interlocker 15 or the second interlocker 16. This enables reducing the circuit size of the signal outputter 13, thus eventually enabling reducing the overall size of the gate driver circuit 1. That is to say, the gate driver circuit 1 according to the exemplary embodiment may reduce the chances of causing inconvenience while reducing an increase in the circuit size of the gate driver circuit 1.
Next, the gate driver circuit 1 and power conversion system 10 according to this embodiment will be described in detail with reference to
The power conversion system 10 according to this embodiment includes a plurality of gate driver circuits 1 (only one of which is shown in
As shown in
The signal generator 11 generates the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal. The first gate signal is a signal to be applied to the gate terminal G11 of the first switching element Q11. The second gate signal is a signal to be applied to the gate terminal G12 of the second switching element Q12. The third gate signal is a signal to be applied to the gate terminal G13 of the third switching element Q13. The fourth gate signal is a signal to be applied to the gate terminal G14 of the fourth switching element Q14.
Applying the first gate signal from the signal generator 11 to the gate terminal G11 of the first switching element Q11 allows the ON/OFF states of the first switching element Q11 to be controlled. Applying the second gate signal from the signal generator 11 to the gate terminal G12 of the second switching element Q12 allows the ON/OFF states of the second switching element Q12 to be controlled. Applying the third gate signal from the signal generator 11 to the gate terminal G13 of the third switching element Q13 allows the ON/OFF states of the third switching element Q13 to be controlled. Applying the fourth gate signal from the signal generator 11 to the gate terminal G14 of the fourth switching element Q14 allows the ON/OFF states of the fourth switching element Q14 to be controlled.
The signal generator 11 is connected to the signal interrupter 12 through a plurality of (e.g., four in the example illustrated in
The signal generator 11 outputs the first gate signal to the signal interrupter 12 (to be described later) via the first signal path L11. The signal generator 11 outputs the second gate signal to the signal interrupter 12 via the first signal path L21. The signal generator 11 outputs the third gate signal to the signal interrupter 12 via the first signal path L31. The signal generator 11 outputs the fourth gate signal to the signal interrupter 12 via the first signal path L41.
The signal interrupter 12 interrupts, on receiving an interruption signal from the signal outputter 13, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21. More specifically, on receiving the interruption signal from the signal outputter 13 (to be described later), the signal interrupter 12 outputs the first, second, third, and fourth gate signals each having low level even when receiving the second gate signal having high level from the signal generator 11, for example.
The signal interrupter 12 may be a level shifter, for example. In particular, in this embodiment, the signal interrupter 12 is a buffer. While receiving no interruption signals, the signal interrupter 12 shapes and amplifies the first, second, third, and fourth gate signals supplied from the signal generator 11 and then outputs the first, second, third, and fourth gate signals thus shaped and amplified to the plurality of drive circuits 14.
The signal interrupter 12 is connected to the signal outputter 13 through a plurality of (e.g., four in the example illustrated in
The second signal path L12 corresponds to the first signal path L11. The second signal path L22 corresponds to the first signal path L21. The second signal path L32 corresponds to the first signal path L31. The second signal path L42 corresponds to the first signal path L41.
The signal outputter 13 outputs the interruption signal to the signal interrupter 12 when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level. The signal outputter 13 outputs the interruption signal to the signal interrupter 12 when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level. The signal interrupter 12 interrupts, on receiving the interruption signal from the signal outputter 13, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21 as described above. In other words, on receiving the interruption signal from the signal outputter 13, the signal interrupter 12 outputs the first, second, third, and fourth gate signals, each having low level.
More specifically, the signal outputter 13 includes a first circuit section 131, a second circuit section 132, and a third circuit section 133 as shown in
The first NOT circuit 1311 has an input terminal connected to the second signal path L42 and receives the fourth gate signal. The first AND circuit 1312 has a first input terminal connected to the second signal path L12 and a second input terminal connected to the output terminal of the first NOT circuit 1311. Thus, the first AND circuit 1312 receives the first gate signal and an output signal of the first NOT circuit 1311. The first NOR circuit 1313 has a first input terminal connected to the second signal path L22 and a second input terminal connected to the second signal path L32. Thus, the first NOR circuit 1313 receives the second gate signal and the third gate signal. The second AND circuit 1314 has a first input terminal connected to the output terminal of the first AND circuit 1312 and a second input terminal connected to the output terminal of the first NOR circuit 1313. Thus, the second AND circuit 1314 receives an output signal of the first AND circuit 1312 and an output signal of the first NOR circuit 1313.
The third AND circuit 1321 has a first input terminal connected to the second signal path L12 and a second input terminal connected to the second signal path L42. Thus, the third AND circuit 1321 receives the first gate signal and the fourth gate signal. The NAND circuit 1322 has a first input terminal connected to the second signal path L22 and a second input terminal connected to the signal path L32. Thus, the NAND circuit 1322 receives the second gate signal and the third gate signal. The fourth AND circuit 1323 has a first input terminal connected to the output terminal of the third AND circuit 1321 and a second input terminal connected to the output terminal of the NAND circuit 1322. Thus, the fourth AND circuit 1323 receives an output signal of the third AND circuit 1321 and an output signal of the NAND circuit 1322.
The second NOT circuit 1331 has an input terminal connected to the second signal path L12 and receives the first gate signal. The fifth AND circuit 1332 has a first input terminal connected to the second signal path L42 and a second input terminal connected to the output terminal of the second NOT circuit 1331. Thus, the fifth AND circuit 1332 receives an output signal of the second NOT circuit 1331 and the fourth gate signal. The second NOR circuit 1333 has a first input terminal connected to the second signal path L22 and a second input terminal connected to the second signal path L32. Thus, the second NOR circuit 1333 receives the second gate signal and the third gate signal. The sixth AND circuit 1334 has a first input terminal connected to the output terminal of the fifth AND circuit 1332 and a second input terminal connected to the output terminal of the second NOR circuit 1333. Thus, the sixth AND circuit 1334 receives an output signal of the fifth AND circuit 1332 and an output signal of the second NOR circuit 1333.
If the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal have any of the five combinations of signal levels (hereinafter referred to as “Patterns A-E,” respectively) shown in the following Table 1, the signal outputter 13 outputs an interruption signal with high level to the signal interrupter 12. In Table 1, H indicates high level and L indicates low level.
For example, according to Pattern A, the first circuit section 131 outputs a high-level interruption signal to the signal interrupter 12. According to Pattern B, the third circuit section 133 outputs a high-level interruption signal to the signal interrupter 12. Also, according to each of Patterns C-E, the second circuit section 132 outputs a high-level interruption signal to the signal interrupter 12. Furthermore, according to each of Patterns A-E, supplying the high-level interruption signal to the signal interrupter 12 causes the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21 to be interrupted. In other words, according to Patterns A-E, applying the high-level interruption signal to the signal interrupter 12 causes the signal interrupter 12 to output the first, second, third, and fourth gate signals each having low level. As a result, the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 of the power converter circuit 21 all turn OFF, thus reducing the chances of causing inconvenience such as short-circuit.
Note that according to each of combinations in first through sixth modes (to be described later), none of the first circuit section 131, the second circuit section 132, or the third circuit section 133 outputs high-level interruption signal.
As shown in
The preamplifier 142 has three input terminals (hereinafter referred to as a “first input terminal,” a “second input terminal,” and a “third input terminal,” respectively) and an output terminal. The first input terminal of the preamplifier 142 is connected to the cathode of the photodiode (photosensitive element) of the photocoupler 141. The photodiode (photosensitive element) of the photocoupler 141 has an anode connected to the base terminal of the transistor of the photocoupler 141. The second input terminal of the preamplifier 142 is connected to the collector terminal of the transistor of the photocoupler 141. The third input terminal of the preamplifier 142 is connected to the emitter terminal of the transistor of the photocoupler 141. The output terminal of the preamplifier 142 is connected to the respective base terminals of the pair of transistors 143, 144.
The transistor 143 has a collector terminal connected to a positive electrode of a first power supply and has an emitter terminal connected to the emitter terminal of the transistor 144. The transistor 144 has a collector terminal connected to a negative electrode of a second power supply. The output terminal T13 is connected to a connection node between the transistors 143, 144.
In the drive circuit 14A, the output terminal T13 is connected to the gate terminal G11 of the first switching element Q11 of the power converter circuit 21. In the drive circuit 14B, the output terminal T13 is connected to the gate terminal G12 of the second switching element Q12 of the power converter circuit 21. In the drive circuit 14C, the output terminal T13 is connected to the gate terminal G13 of the third switching element Q13 of the power converter circuit 21. In the drive circuit 14D, the output terminal T13 is connected to the gate terminal G14 of the fourth switching element Q14 of the power converter circuit 21.
The first interlocker 15 controls the power converter circuit 21 to prevent the first switching element Q11 and the third switching element Q13 from turning ON simultaneously. The first interlocker 15 has two second branch paths L14, L34 as shown in
For example, if the first gate signal has high level, the high-level first gate signal is supplied through the second branch path L14 to the drive circuit 14C as well, and therefore, the third switching element Q13 does not turn ON. If the third gate signal has high level, the high-level third gate signal is supplied through the second branch path L34 to the drive circuit 14A as well, and therefore, the first switching element Q11 does not turn ON. That is to say, the first interlocker 15 may reduce the chances of causing the inconvenience that the first switching element Q11 and the third switching element Q13 turn ON simultaneously.
The second interlocker 16 controls the power converter circuit 21 to prevent the second switching element Q12 and the fourth switching element Q14 from turning ON simultaneously. The second interlocker 16 has two second branch paths L24, L44 as shown in
For example, if the second gate signal has high level, the high-level second gate signal is supplied through the second branch path L24 to the drive circuit 14D as well, and therefore, the fourth switching element Q14 does not turn ON. If the fourth gate signal has high level, the high-level fourth gate signal is supplied through the second branch path L44 to the drive circuit 14B as well, and therefore, the second switching element Q12 does not turn ON. That is to say, the second interlocker 16 may reduce the chances of causing the inconvenience that the second switching element Q12 and the fourth switching element Q14 turn ON simultaneously.
The inverter circuit 2 is a three-level inverter of a diode-clamped type as described above. As shown in
The power converter circuit 21 includes the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14. The power converter circuit 21 further includes the first diode D11, the second diode D12, the third diode D13, the fourth diode D14, the fifth diode D15, and the sixth diode D16. The power converter circuit 21 further includes an output terminal T1.
Each of the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 may be, for example, an insulated gate bipolar transistor (IGBT). The first switching element Q11 has the gate terminal G11, a collector terminal, and an emitter terminal. The second switching element Q12 has the gate terminal G12, a collector terminal, and an emitter terminal. The third switching element Q13 has the gate terminal G13, a collector terminal, and an emitter terminal. The fourth switching element Q14 has the gate terminal G14, a collector terminal, and an emitter terminal.
The first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 are connected in series between the positive electrode P1 and negative electrode N1 of the DC power supply 3. More specifically, the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 are connected in series in this order in the direction pointing from the positive electrode P1 toward the negative electrode N1. More specifically, the first switching element Q11 has its collector terminal connected to the positive electrode P1 and its emitter terminal connected to the collector terminal of the second switching element Q12. The second switching element Q12 has its emitter terminal connected to the collector terminal of the third switching element Q13. The third switching element Q13 has its emitter terminal connected to the collector terminal of the fourth switching element Q14. The fourth switching element Q14 has its emitter terminal connected to the negative electrode N1.
In the first switching element Q11, the first gate signal supplied from the gate driver circuit 1 is applied to the gate terminal G11. In the second switching element Q12, the second gate signal supplied from the gate driver circuit 1 is applied to the gate terminal G12. In the third switching element Q13, the third gate signal supplied from the gate driver circuit 1 is applied to the gate terminal G13. In the fourth switching element Q14, the fourth gate signal supplied from the gate driver circuit 1 is applied to the gate terminal G14.
The first diode D11 is connected in anti-parallel to the first switching element Q11. More specifically, the first diode D11 has an anode connected to the emitter terminal of the first switching element Q11 and a cathode connected to the collector terminal of the first switching element Q11.
The second diode D12 is connected in anti-parallel to the second switching element Q12. More specifically, the second diode D12 has an anode connected to the emitter terminal of the second switching element Q12 and a cathode connected to the collector terminal of the second switching element Q12.
The third diode D13 is connected in anti-parallel to the third switching element Q13. More specifically, the third diode D13 has an anode connected to the emitter terminal of the third switching element Q13 and a cathode connected to the collector terminal of the third switching element Q13.
The fourth diode D14 is connected in anti-parallel to the fourth switching element Q14. More specifically, the fourth diode D14 has an anode connected to the emitter terminal of the fourth switching element Q14 and a cathode connected to the collector terminal of the fourth switching element Q14.
The fifth diode D15 has a cathode connected to the connection node P11 between the first switching element Q11 and the second switching element Q12 and an anode connected to the intermediate potential node M1 of the DC power supply 3. As used herein, the “intermediate potential node M1” refers to a node, of which the potential is intermediate between the potential at the positive electrode P1 of the DC power supply 3 and the potential at the negative electrode N1 of the DC power supply 3. In this embodiment, the intermediate potential node M1 has the ground potential. For example, if the output voltage of a main power supply 31 (to be described later) is V1, then the potential at the positive electrode P1 is +V½ and the potential at the negative electrode N1 is −V½.
The sixth diode D16 has a cathode connected to the intermediate potential node M1 and an anode connected to the connection node P13 between the third switching element Q13 and the fourth switching element Q14.
The output terminal T1 is connected to a connection node P12 between the second switching element Q12 and the third switching element Q13. The output terminal T1 is a terminal through which voltage to be applied to the connection node P12 is output.
In this embodiment, a three-phase motor, for example, is connected to the three output terminals T1, T2, T3. That is to say, the inverter circuit 2 according to this embodiment is an inverter circuit for supplying three-phase AC power to a load (e.g., the three-phase motor in this embodiment).
(2.3) DC Power Supply
The DC power supply 3 includes the main power supply 31 and two capacitors 32, 33 as shown in
Next, the basic operation of the inverter circuit 2 will be described. The plurality of power converter circuits 21-23 perform the same operation with their phases shifted from each other by 120 degrees. Thus, in the following description, only the operation of the power converter circuit 21 will be described and the operation of the other power converter circuits 22, 23 will not be described.
The power converter circuit 21 has the following first through sixth modes.
In the first mode, the second gate signal rises to high level and the first gate signal, the third gate signal, and the fourth gate signal fall to low level. That is to say, in the first mode, the second switching element Q12 turns ON, and the first switching element Q11, the third switching element Q13, and the fourth switching element Q14 turn OFF. In that case, the intermediate potential node M1 and the output terminal T1 become electrically conductive with each other via the fifth diode D15 and the second switching element Q12, and therefore, the output terminal T1 comes to have a potential of 0 V.
In the second mode, the first gate signal and the second gate signal rise to high level and the third gate signal and the fourth gate signal fall to low level. That is to say, in the second mode, the first switching element Q11 and the second switching element Q12 turn ON and the third switching element Q13 and the fourth switching element Q14 turn OFF. In that case, the positive electrode P1 and the output terminal T1 become electrically conductive with each other via the first switching element Q11 and the second switching element Q12, and therefore, the output terminal T1 comes to have the same potential as the positive electrode P1. In other words, if the output voltage of the main power supply 31 is V1, then the output terminal T1 comes to have a potential +V½.
In the third mode, the second gate signal rises to high level and the first gate signal, the third gate signal, and the fourth gate signal fall to low level. That is to say, in the third mode, the second switching element Q12 turns ON, and the first switching element Q11, the third switching element Q13, and the fourth switching element Q14 turn OFF. In that case, the intermediate potential node M1 and the output terminal T1 become electrically conductive with each other via the fifth diode D15 and the second switching element Q12, and therefore, the output terminal T1 comes to have a potential of 0 V.
In the fourth mode, the third gate signal rises to high level and the first gate signal, the second gate signal, and the fourth gate signal fall to low level. That is to say, in the fourth mode, the third switching element Q13 turns ON, and the first switching element Q11, the second switching element Q12, and the fourth switching element Q14 turn OFF. In that case, the intermediate potential node M1 and the output terminal T1 become electrically conductive with each other via the sixth diode D16 and the third switching element Q13, and therefore, the output terminal T1 comes to have a potential of 0 V.
In the fifth mode, the third gate signal and the fourth gate signal rise to high level and the first gate signal and the second gate signal fall to low level. That is to say, in the fifth mode, the third switching element Q13 and the fourth switching element Q14 turn ON and the first switching element Q11 and the second switching element Q12 turn OFF. In that case, the negative electrode N1 and the output terminal T1 become electrically conductive with each other via the third switching element Q13 and the fourth switching element Q14, and therefore, the output terminal T1 comes to have the same potential as the negative electrode N1. In other words, if the output voltage of the main power supply 31 is V1, then the output terminal T1 comes to have a potential −V½.
In the sixth mode, the third gate signal rises to high level and the first gate signal, the second gate signal, and the fourth gate signal fall to low level. That is to say, in the sixth mode, the third switching element Q13 turns ON, and the first switching element Q11, the second switching element Q12, and the fourth switching element Q14 turn OFF. In that case, the intermediate potential node M1 and the output terminal T1 become electrically conductive with each other via the third switching element Q13 and the sixth diode D16, and therefore, the output terminal T1 comes to have a potential of 0 V.
The power converter circuit 21 performs this series of operations in the first through sixth modes repeatedly in this order. Likewise, each of the other power converter circuits 22, 23 also performs this series of operations in the first through sixth modes repeatedly in this order with their phases shifted from each other by 120 degrees.
Next, a gate driving method according to this embodiment will be described with reference to
A gate driving method according to this embodiment is a method for controlling the ON/OFF states of the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 included in the power converter circuit 21.
The power converter circuit 21 includes the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14, the first diode D11, the second diode D12, the third diode D13, the fourth diode D14, the fifth diode D15, and the sixth diode D16.
The first, second, third, and fourth switching element Q11, Q12, Q13, Q14 each have a gate terminal G11, G12, G13, G14, and are connected in series between the positive electrode P1 and the negative electrode N1 of the DC power supply 3. The first diode D11 is connected in anti-parallel to the first switching element Q11. The second diode D12 is connected in anti-parallel to the second switching element Q12. The third diode D13 is connected in anti-parallel to the third switching element Q13. The fourth diode D14 is connected in anti-parallel to the fourth switching element Q14. The fifth diode D15 has its cathode connected to the connection node P11 between the first switching element Q11 and the second switching element Q12 and its anode connected to the intermediate potential node M1 of the DC power supply 3. The sixth diode D16 has its anode connected to the connection node P13 between the third switching element Q13 and the fourth switching element Q14 and its cathode connected to the intermediate potential node M1 of the DC power supply 3.
The gate driving method includes a signal generating step ST1, a signal interrupting step ST4, an interlocking step ST2 (including a first interlocking step and a second interlocking step), and a signal outputting step ST3.
The signal generating step ST1 includes generating a first gate signal to be applied to the gate terminal G11 of the first switching element Q11, a second gate signal to be applied to the gate terminal G12 of the second switching element Q12, a third gate signal to be applied to the gate terminal G13 of the third switching element Q13, and a fourth gate signal to be applied to the gate terminal G14 of the fourth switching element Q14. The signal interrupting step ST4 includes interrupting, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that have been generated in the signal generating step ST1 to prevent the first, second, third, and fourth gate signals from being applied to the power converter circuit 21. The first interlocking step includes controlling the power converter circuit 21 to prevent the first switching element Q11 and the third switching element Q13 from turning ON simultaneously. The second interlocking step includes controlling the power converter circuit 21 to prevent the second switching element Q12 and the fourth switching element Q14 from turning ON simultaneously. The signal outputting step ST3 includes outputting the interruption signal either when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level or when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
In the gate driving method according to this embodiment, the signal outputting step ST3 includes outputting the interruption signal to the signal interrupter 12 when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level. Alternatively, the signal outputting step ST3 includes outputting the interruption signal to the signal interrupter 12 when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level. This allows, in any of the two situations described above, the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 to be all turned OFF, thus reducing the chances of causing inconvenience in any of the situations described above. In addition, the gate driving method according to this embodiment allows the signal outputting step ST3 to deal with the inconvenience that cannot be handled by the interlocking step ST2 (including the first interlocking step and the second interlocking step). This enables reducing the circuit size of the signal outputter 13, thus eventually enabling reducing the overall size of the gate driver circuit 1. That is to say, the gate driving method according to the exemplary embodiment may reduce the chances of causing inconvenience while reducing an increase in the circuit size of the gate driver circuit 1.
First, the gate driver circuit 1 performs a signal generating step ST1. In the signal generating step ST1, the signal generator 11 generates a first gate signal, a second gate signal, a third gate signal, and a fourth gate signal. As described above, the first gate signal is a signal to be applied to the gate terminal G11 of the first switching element Q11. The second gate signal is a signal to be applied to the gate terminal G12 of the second switching element Q12. The third gate signal is a signal to be applied to the gate terminal G13 of the third switching element Q13. The fourth gate signal is a signal to be applied to the gate terminal G14 of the fourth switching element Q14.
Next, the gate driver circuit 1 performs an interlocking step ST2. In the interlocking step ST2, the first interlocker 15 controls the power converter circuit 21 to prevent the first switching element Q11 and the third switching element Q13 from turning ON simultaneously (first interlocking step). More specifically, the first interlocker 15 outputs the first gate signal to the drive circuit 14C through the second branch path L14 and also outputs the third gate signal to the drive circuit 14A through the second branch path L34. In addition, in the interlocking step ST2, the second interlocker 16 controls the power converter circuit 21 to prevent the second switching element Q12 and the fourth switching element Q14 from turning ON simultaneously (second interlocking step). More specifically, the second interlocker 16 outputs the second gate signal to the drive circuit 14D through the second branch path L24 and also outputs the fourth gate signal to the drive circuit 14B through the second branch path L44.
Next, the gate driver circuit 1 performs a signal outputting step ST3. In the signal outputting step ST3, the signal outputter 13 outputs a high-level interruption signal to the signal interrupter 12 when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level (if the answer is YES in ST3). Also, in the signal outputting step ST3, the signal outputter 13 outputs a high-level interruption signal to the signal interrupter 12 when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level (if the answer is YES in ST3). On the other hand, if the answer is NO in any of these cases in the signal outputting step ST3, the signal outputter 13 ends the series of processing.
Next, if the answer is YES in any of these cases in ST3, the gate driver circuit 1 performs a signal interrupting step ST4. In the signal interrupting step ST4, the signal interrupter 12 interrupts, in accordance with an interruption signal supplied from the signal outputter 13, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21. In other words, in the signal interrupting step ST4, the signal interrupter 12 outputs the first, second, third, and fourth gate signal, each having low level, in accordance with the interruption signal supplied from the signal outputter 13.
In the gate driver circuit 1 according to this embodiment, the signal outputter 13 outputs the interruption signal to the signal interrupter 12 when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level. The signal outputter 13 also outputs the interruption signal to the signal interrupter 12 when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level. Then, on receiving the interruption signal, the signal interrupter 12 interrupts the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator 11 to the power converter circuit 21. This allows the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 to be all turned OFF in any of the two situations described above. Consequently, this may reduce the chances of causing inconvenience in any of the situations described above. In addition, the gate driver circuit 1 according to this embodiment allows the signal outputter 13 to deal with the inconvenience that cannot be handled by the first interlocker 15 or the second interlocker 16. This enables reducing the circuit size of the signal outputter 13, thus eventually enabling reducing the overall circuit size of the gate driver circuit 1. That is to say, the gate driver circuit 1 according to the exemplary embodiment may reduce the chances of causing inconvenience while reducing an increase in the circuit size of the gate driver circuit 1.
In addition, in the gate driver circuit 1 according to this embodiment, the signal outputter 13 includes the first circuit section 131, the second circuit section 132, and the third circuit section 133. The first circuit section 131 includes the first NOT circuit 1311, the first AND circuit 1312, the first NOR circuit 1313, and the second AND circuit 1314. The second circuit section 132 includes the third AND circuit 1321, the NAND circuit 1322, and the fourth AND circuit 1323. The third circuit section 133 includes the second NOT circuit 1331, the fifth AND circuit 1332, the second NOR circuit 1333, and the sixth AND circuit 1334. As can be seen, the signal outputter 13 consists of only logic circuits, thus enabling reducing, using a simple configuration, the chances of causing inconvenience.
The power conversion system 10 according to this embodiment includes a plurality of gate driver circuits 1 (only one of which is shown in
In the power conversion system 10 according to this embodiment, each of the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 is an insulated gate bipolar transistor. This enables using the power conversion system 10 with a large amount of current supplied while contributing to reducing the size of the power conversion system 10.
Note that the embodiment described above is only an exemplary one of various embodiments of the present disclosure and should not be construed as limiting. Rather, the exemplary embodiment may be readily modified in various manners depending on a design choice or any other factor without departing from the scope of the present disclosure. Next, variations of the exemplary embodiment will be enumerated one after another. Note that the variations to be described below may be adopted in combination as appropriate.
In the exemplary embodiment described above, the inverter circuit 2 is a three-level inverter. However, the inverter circuit 2 does not have to be a three-level inverter but may also be a five-level inverter or a seven-level inverter, whichever is appropriate. An inverter circuit 2a implemented as a five-level inverter will be described with reference to
The inverter circuit 2a according to the first variation includes a power converter circuit 21a as shown in
Eight switching elements Q41-Q48 belonging to the plurality of switching elements Q41-Q50 are connected in series between a positive electrode P101 and a negative electrode N101 of a DC power supply. More specifically, the eight switching elements Q41, Q42, Q43, Q44, Q45, Q46, Q47, and Q48 are connected in series in this order in the direction pointing from the positive electrode P101 toward the negative electrode N101.
The switching element Q49 has a collector terminal connected to a connection node P41 between the two switching elements Q41, Q42. The switching element Q49 has an emitter terminal connected to a connection node P102 between two capacitors C41, C42 which are connected between the positive electrode P101 and an intermediate potential node M101. The switching element Q50 has a collector terminal connected to a connection node N102 between two capacitors C43, C44 which are connected between the negative electrode N101 and the intermediate potential node M101. The switching element Q50 has an emitter terminal connected to a connection node P45 between the two switching elements Q47, Q48.
The diode D41 is connected in anti-parallel to the switching element Q41. The diode D42 is connected in anti-parallel to the switching element Q42. The diode D43 is connected in anti-parallel to the switching element Q43. The diode D44 is connected in anti-parallel to the switching element Q44. The diode D45 is connected in anti-parallel to the switching element Q45. The diode D46 is connected in anti-parallel to the switching element Q46. The diode D47 is connected in anti-parallel to the switching element Q47. The diode D48 is connected in anti-parallel to the switching element Q48. The diode D49 is connected in anti-parallel to the switching element Q49. The diode D50 is connected in anti-parallel to the switching element Q50.
The four diodes D51-D54 are connected in series between a connection node P42 of the two switching elements Q42, Q43 and a connection node P44 of the two switching elements Q46, Q47. More specifically, the diodes D51, D52, D53, and D54 are connected in series in this order in the direction pointing from the connection node P42 toward the connection node P44. Also, a connection node P46 between the two diodes D52, D53 is connected to the intermediate potential node M101.
The output terminal T10 is connected to a connection node P43 between the two switching elements Q44, Q45.
The inverter circuit 2 does not have to include the three power converter circuits 21-23. Alternatively, the inverter circuit 2 may include only one power converter circuit or two power converter circuits. In that case, only one gate driver circuit or two gate driver circuits may be provided.
The configuration for the signal outputter 13 shown in
Each of the first switching element Q11, the second switching element Q12, the third switching element Q13, and the fourth switching element Q14 does not have to be an IGBT but may also be, for example, an SiC-MOSFET (silicon carbide metal-oxide semiconductor field effect transistor).
The foregoing description provides specific implementations for the following aspects of the present disclosure.
A gate driver circuit (1) according to a first aspect controls ON/OFF states of a first switching element (Q11), a second switching element (Q12), a third switching element (Q13), and a fourth switching element (Q14) included in a power converter circuit (21). The power converter circuit (21) includes the first switching element (Q11), the second switching element (Q12), the third switching element (Q13), and the fourth switching element (Q14), a first diode (D11), a second diode (D12), a third diode (D13), a fourth diode (D14), a fifth diode (D15), and a sixth diode (D16). The first, second, third, and fourth switching elements (Q11, Q12, Q13, Q14) each have a gate terminal (G11, G12, G13, G14), and are connected in series between a positive electrode (P1) and a negative electrode (N1) of a DC power supply (3). The first diode (D11) is connected in anti-parallel to the first switching element (Q11). The second diode (D12) is connected in anti-parallel to the second switching element (Q12). The third diode (D13) is connected in anti-parallel to the third switching element (Q13). The fourth diode (D14) is connected in anti-parallel to the fourth switching element (Q14). The fifth diode (D15) has a cathode connected to a connection node (P11) between the first switching element (Q11) and the second switching element (Q12) and an anode connected to an intermediate potential node (M1) of the DC power supply (3). The sixth diode (D16) has an anode connected to a connection node (P13) between the third switching element (Q13) and the fourth switching element (Q14) and a cathode connected to the intermediate potential node (M1) of the DC power supply (3). The gate driver circuit (1) includes a signal generator (11), a signal interrupter (12), a first interlocker (15), a second interlocker (16), and a signal outputter (13). The signal generator (11) generates a first gate signal to be applied to the gate terminal (G11) of the first switching element (Q11), a second gate signal to be applied to the gate terminal (G12) of the second switching element (Q12), a third gate signal to be applied to the gate terminal (G13) of the third switching element (Q13), and a fourth gate signal to be applied to the gate terminal (G14) of the fourth switching element (Q14). The signal interrupter (12) interrupts, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that are going to be applied from the signal generator (11) to the power converter circuit (21). The first interlocker (15) controls the power converter circuit (21) to prevent the first switching element (Q11) and the third switching element (Q13) from turning ON simultaneously. The second interlocker (16) controls the power converter circuit (21) to prevent the second switching element (Q12) and the fourth switching element (Q14) from turning ON simultaneously. The signal outputter (13) outputs the interruption signal to the signal interrupter (12) either when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level or when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
This aspect may reduce the chances of causing inconvenience while reducing an increase in circuit size.
In a gate driver circuit (1) according to a second aspect, which may be implemented in conjunction with the first aspect, the signal outputter (13) includes a first circuit section (131), a second circuit section (132), and a third circuit section (133). The first circuit section (131) includes a first NOT circuit (1311), a first AND circuit (1312), a first NOR circuit (1313), and a second AND circuit (1314). The first NOT circuit (1311) receives the fourth gate signal. The first AND circuit (1312) receives the first gate signal and an output signal of the first NOT circuit (1311). The first NOR circuit (1313) receives the second gate signal and the third gate signal. The second AND circuit (1314) receives an output signal of the first AND circuit (1312) and an output signal of the first NOR circuit (1313). The second circuit section (132) includes a third AND circuit (1321), a NAND circuit (1322), and a fourth AND circuit (1323). The third AND circuit (1321) receives the first gate signal and the fourth gate signal. The NAND circuit (1322) receives the second gate signal and the third gate signal. The fourth AND circuit (1323) receives an output signal of the third AND circuit (1321) and an output signal of the NAND circuit (1322). The third circuit section (133) includes a second NOT circuit (1331), a fifth AND circuit (1332), a second NOR circuit (1333), and a sixth AND circuit (1334). The second NOT circuit (1331) receives the first gate signal. The fifth AND circuit (1332) receives the first gate signal and an output signal of the second NOT circuit (1331). The second NOR circuit (1333) receives the second gate signal and the third gate signal. The sixth AND circuit (1334) receives an output signal of the fifth AND circuit (1332) and an output signal of the second NOR circuit (1333).
This aspect may reduce, using a simple circuit configuration, the chances of causing inconvenience.
A power conversion system (10) according to a third aspect includes the gate driver circuit (1) according to the first or second aspect and the power converter circuit (21).
This aspect may reduce the chances of causing inconvenience while reducing an increase in circuit size.
A power conversion system (10) according to a fourth aspect, which may be implemented in conjunction with the third aspect, includes: a plurality of the gate driver circuits (1); and a plurality of the power converter circuits (21, 22, 23). The plurality of the gate driver circuits (1) and the plurality of the power converter circuits (21, 22, 23) are arranged to correspond one to one. This aspect enables generating AC power in multiple phases.
In a power conversion system (10) according to a fifth aspect, which may be implemented in conjunction with the third or fourth aspect, each of the first switching element (Q11), the second switching element (Q12), the third switching element (Q13), and the fourth switching element (Q14) is an insulated gate bipolar transistor.
This aspect allows the power conversion system (10) to be used with a large amount of current supplied while contributing to reducing the size of the power conversion system (10).
A gate driving method according to a sixth aspect is a method for controlling ON/OFF states of a first switching element (Q11), a second switching element (Q12), a third switching element (Q13), and a fourth switching element (Q14) included in a power converter circuit (21). The power converter circuit (21) includes the first switching element (Q11), the second switching element (Q12), the third switching element (Q13), and the fourth switching element (Q14), a first diode (D11), a second diode (D12), a third diode (D13), a fourth diode (D14), a fifth diode (D15), and a sixth diode (D16). The first, second, third, and fourth switching element (Q11, Q12, Q13, Q14) each have a gate terminal (G11, G12, G13, G14), and are connected in series between a positive electrode (P1) and a negative electrode (N1) of a DC power supply (3). The first diode (D11) is connected in anti-parallel to the first switching element (Q11). The second diode (D12) is connected in anti-parallel to the second switching element (Q12). The third diode (D13) is connected in anti-parallel to the third switching element (Q13). The fourth diode (D14) is connected in anti-parallel to the fourth switching element (Q14). The fifth diode (D15) has a cathode connected to a connection node (P11) between the first switching element (Q11) and the second switching element (Q12) and an anode connected to an intermediate potential node (M1) of the DC power supply (3). The sixth diode (D16) has an anode connected to a connection node (P13) between the third switching element (Q13) and the fourth switching element (Q14) and a cathode connected to the intermediate potential node (M1) of the DC power supply (3). The gate driving method includes a signal generating step (ST1), a second interruption step (ST4), a first interlocking step (ST2), a second interlocking step (ST2), and a signal outputting step (ST3). The signal generating step (ST1) includes generating a first gate signal to be applied to the gate terminal (G11) of the first switching element (Q11), a second gate signal to be applied to the gate terminal (G12) of the second switching element (Q12), a third gate signal to be applied to the gate terminal (G13) of the third switching element (Q13), and a fourth gate signal to be applied to the gate terminal (G14) of the fourth switching element (Q14). The signal interrupting step (ST4) includes interrupting, on receiving an interruption signal, the first gate signal, the second gate signal, the third gate signal, and the fourth gate signal that have been generated in the signal generating step (ST1) to prevent the first, second, third, and fourth gate signals from being applied to the power converter circuit (21). The first interlocking step (ST2) includes controlling the power converter circuit (21) to prevent the first switching element (Q11) and the third switching element (Q13) from turning ON simultaneously. The second interlocking step (ST2) includes controlling the power converter circuit (21) to prevent the second switching element (Q12) and the fourth switching element (Q14) from turning ON simultaneously. The signal outputting step (ST3) includes outputting the interruption signal either when at least one of the first gate signal or the fourth gate signal has high level and the second gate signal and the third gate signal have low level or when the first gate signal and the fourth gate signal have high level, one signal selected from the group consisting of the second gate signal and the third gate signal has high level, and the other signal selected from the group consisting of the second gate signal and the third gate signal has low level.
This aspect may reduce the chances of causing inconvenience while reducing an increase in circuit size.
Note that the constituent elements according to the second aspect are not essential constituent elements for the gate driver circuit (1) but may be omitted as appropriate.
Note that the constituent elements according to the fourth and fifth aspects are not essential constituent elements for the power conversion system (10) but may be omitted as appropriate.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-048822 | Mar 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2023/011392 | 3/23/2023 | WO |
