Claims
- 1. A gate driver for controlling a gate voltage of each of a plurality of MOS control semiconductor devices of a semiconductor power converter in which said MOS control semiconductor devices are connected in series with each other, said gate driver comprising:a power supply line having a higher potential than a gate potential on each of said MOS control semiconductor devices when each of said MOS control semiconductor devices is in a steady ON state; and means for supplying a current from the power source line to the gate of each of said MOS control semiconductor devices so as to increase the gate voltage of each of said MOS control semiconductor devices when a potential difference between said power supply line and an emitter of each of said MOS control semiconductor devices is constant and when a collector voltage of each of said MOS control semiconductor devices exceeds a predetermined value under ON state of said MOS control semiconductor devices.
- 2. A gate driver for controlling a gate voltage of each of a plurality of MOS control semiconductor devices connected in series with each other, said gate driver comprising:a circuit for outputting a first gate voltage command value for switching each of said MOS control semiconductor devices; a circuit for outputting a second gate voltage command value which becomes higher when a collector voltage of each of said MOS control semiconductor devices is increased; and a circuit for comparing said first and second gate voltage command values with each other, and for controlling the gate voltage of each of said MOS control semiconductor devices to be the higher gate voltage command value, wherein, when the collector voltage of each of said MOS control semiconductor devices is higher than a collector voltage under steady OFF state of each of said MOS control semiconductor devices, the gate voltage of each of said MOS control semiconductor devices is increased higher than a gate voltage of each of the MOS control semiconductor devices under steady ON state.
- 3. A gate driver as claimed in claim 2, wherein:said circuit for comparing said first and second gate voltage command value with each other and for controlling the gate voltage of each of the MOS control semiconductor devices to be said higher gate voltage command value includes an npn transistor and a pnp transistor which are connected with each other in a complementary manner; a collector of said pnp transistor is connected to an output of the circuit for outputting the gate voltage command value for switching each of said MOS control semiconductor devices; and a gate of said pnp transistor and a gate of said npn transistor are connected to an output of said circuit for outputting the gate voltage command value which becomes higher when the collector voltage of each of said MOS control semiconductor devices is increased.
- 4. A gate driver as claimed in claim 3, wherein a diode is connected in inverse-parallel with said pnp transistor.
- 5. A gate driver for controlling a gate voltage of an MOS control semiconductor device, comprising:means for outputting a gate voltage command value for switching said MOS control semiconductor device; means for outputting a gate voltage adding command value which becomes higher when a collector voltage of said MOS control semiconductor device is increased; and means for controlling a gate voltage of said MOS control semiconductor device to be a voltage obtained by adding said gate voltage command value to said gate voltage adding command value.
- 6. A gate driver as claimed in claim 1, wherein said MOS control semiconductor devices include insulated gate bipolar transistors (IGBTs).
- 7. A gate driver as claimed in claim 1, wherein said MOS control semiconductor devices include metal oxide semiconductors (MOS) field effect transistors (FETs).
- 8. A gate driver for controlling a gate voltage of each of a plurality of insulated gate bipolar transistors (IGBTs) of a semiconductor power converter in which said IGBTs are connected in series with each other, said gate driver comprising:a power supply line having a higher potential than a gate potential on each of said IGBTs when each of said IGBTs is in steady ON state; and means for supplying a current from the power source line to the gate of each of said IGBTs so as to increase the gate voltage of each of said IGBTs when a potential difference between said power supply line and an emitter of each of said IGBTs is constant, and a collector voltage of each of said IGBTs exceeds a predetermined value under ON state of each of said IGBTs.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2001-259121 |
Aug 2001 |
JP |
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“CROSS-REFERENCE TO RELATED APPLICATIONS”
The application is a Continuation application of application Ser. No. 10/099,950, filed Mar. 19, 2002.
US Referenced Citations (4)
Non-Patent Literature Citations (2)
Entry |
IPEC 2000 pp. 670-675, (2000). |
The published abstract of the Japanese Electric Society Industrial Application Department Meeting in 1999, vol. 2, pp. 119-120. |
Continuations (1)
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Number |
Date |
Country |
Parent |
10/099950 |
Mar 2002 |
US |
Child |
10/436265 |
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US |