Patent Grant
11783780
This application claims priority under 35 U.S.C. 119(a) to Republic of Korea Patent Application No. 10-2020-0186713 filed on Dec. 29, 2020, which is incorporated by reference herein in its entirety.
The present disclosure relates to a gate driver and a display device including the same.
A display device includes a display panel including a plurality of pixels, a gate driver and a data driver for driving the pixels, and a timing controller. The gate driver is provided with stage circuits that are connected to gate lines, and the stage circuits apply gate signals to the gate lines that are connected thereto in response to control signals received from the timing controller.
In embodiments, there is provided a gate driver and a display device including the same, in which the gate driver is configured such that multiple buffers are connected to one shift register so as to allow gate signals to be output to a plurality of gate lines.
In addition, in embodiments, there is provided a gate driver and a display device including the same, in which the gate driver is provided with a transistor for separately charging and discharging a gate voltage of pull-up transistors that are provided at buffers.
According to an aspect of the present disclosure, there is provided a gate driver including: a plurality of stage circuits, wherein each of the plurality of stage circuits may include: a shift register configured to control charging and discharging of a Q node and a QB node; and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers may include: a first transistor configured to transmit a voltage of the Q node to a Q′ node; a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node; and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.
Each of the output buffers may further include a second transistor turned on according to the voltage of the Q node and configured to charge the Q′ node with a high-potential voltage.
A gate electrode of the first transistor may be connected to the high-potential voltage that is a direct current power source.
Each of the output buffers may further include a third transistor turned on according to the voltage of the QB node and configured to discharge the Q′ node.
The first transistor may be connected in a form of a diode between the Q node and the Q′ node.
A gate electrode of the first transistor may be configured to receive a carry signal output from a previous stage circuit.
Each of the output buffers may further include: a second transistor turned on according to the voltage of the Q node and configured to transmit a high-potential voltage to the Q′ node; and a third transistor turned on according to the voltage of the QB node and configured to transmit the low-potential voltage to the Q′ node.
A gate electrode of the first transistor may be configured to receive the high-potential voltage that is a direct current power source or receive a carry signal output from a previous stage circuit.
The first transistor may be connected in a form of a diode between the Q node and the Q′ node.
The first transistor and the second transistor may be configured to separately control charging and discharging of each Q node of the plurality of output buffers.
According to an aspect of the present disclosure, there is provided a display device including: a display panel configured to display an image; a data driver configured to apply a data signal to the display panel; and a gate driver including a plurality of stage circuits and configured to apply a gate signal to the display signal, wherein each of the plurality of the stage circuits may include: a shift register configured to control charging and discharging of a Q node and a QB node; and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers may include: a first transistor configured to transmit a voltage of the Q node to a Q′ node; a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node; and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.
According to embodiments, the gate driver and the display device including the same enable an implementation of a display device that has a narrow bezel by reducing the area of the gate driver resulting from a reduction in the number of shift registers.
In addition, according to embodiments, the gate driver and the display device including the same allow output of the gate signal to be uniform and stable by stably charging and discharging the gate voltage of the pull-up transistors that are provided at the buffers.
The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, it will be understood that when one component (or region, layer, portion) is referred to as being “on”, “connected to”, or “coupled to” another component, it can be directly disposed/connected/coupled on/to the another component, or an intervening third component may also be present.
Like reference numerals refer to like elements throughout. It will be understood that although the terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one component from other components. For example, an element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims. The terms of a singular form may include plural forms unless referred to the contrary.
The meaning of the term “include” or “comprise” specifies presence of a property, a fixed number, a step, an operation, an element, a component or a combination thereof, but does not exclude presence or addition of other properties, fixed numbers, steps, operations, elements, components or combinations thereof.
Referring to
The timing controller 10 may receive an image signal RGB and a control signal CS from outside. The image signal RGB may include a plurality of gray scale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.
The timing controller 10 may process the image signal RGB and the control signal CS to make the signals appropriate for an operation condition of the display panel 50, so that the timing controller 10 may generate and output image data DATA, a gate driving control signal CONT1, a data driving control signal CONT2, and a power supply control signal CONT3.
The gate driver 20 may generate gate signals on the basis of the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signals to the pixels PXs through multiple first gate lines GL11 to GL1n.
The gate driver 20 may provide a sensing signal to the pixels PXs through multiple second gate lines GL21 to GL2n. The sensing signal may be supplied so as to measure a characteristic of a driving transistor and/or a light-emitting element provided inside the pixels PXs.
The data driver 30 may generate data signals on the basis of the image data DATA and the data driving control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data signals to the pixels PXs through multiple data lines DL1 to DLm.
The data driver 30 may provide a reference voltage (a sensing voltage, or an initialization voltage) to the pixels PXs through multiple sensing lines SL1 to SLm, or may sense states of the pixels PXs on the basis of an electrical signal fed back from the pixels PXs.
The power supply 40 may generate a driving voltage to be provided to the display panel 50, on the basis of the power supply control signal CONT3. The driving voltage may include, for example, a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS. The power supply 40 may provide the generated driving voltages ELVDD and ELVSS to the pixels PXs, through corresponding power lines PL1 and PL2. In addition, the power supply 40 may supply a voltage required for driving the gate driver 20 and the data driver 30 and for generating a data voltage to the gate driver 20 and the data driver 30.
In the display panel 50, the multiple pixels PXs (or referred to as sub-pixels) are disposed. The pixels PXs may be, for example, arranged in a matrix form on the display panel 50. The pixels PXs may emit light with luminance corresponding to the gate signals and the data signals that are supplied through the first gate lines GL11 to GL1n and the data lines DL1 to DLm, respectively. In an embodiment, each pixel PX may display any one among red, green, blue, and white colors, but is not limited thereto.
The timing controller 10, the gate driver 20, the data driver 30, and the power supply 40 may be configured as separate integrated circuits (ICs), or ICs in which at least some thereof are integrated. For example, at least one among the data driver 30 and the power supply 40 may be configured as an integrated circuit integrated with the timing controller 10.
In addition, in
Referring to
A first electrode of the switching transistor ST is connected to the j-th data line DLj and a second electrode of the switching transistor ST is connected to a first node N1. A gate electrode of the switching transistor ST is connected to the i-th first gate line GL1i. The switching transistor ST is turned on when a gate signal at a gate-on level is applied through the i-th first gate line GL1i, and transmits a data signal applied through the j-th data line DLj, to the first node N1.
A first electrode of the storage capacitor Cst is connected to the first node N1, and a second electrode of the storage capacitor Cst may be configured to receive the high-potential driving voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to the difference between a voltage applied to the first node N1 and the high-potential driving voltage ELVDD.
A first electrode of the driving transistor DT is configured to receive the high-potential driving voltage ELVDD, and a second electrode of the driving transistor DT is connected to a first electrode (for example, an anode electrode) of the light-emitting element LD. A gate electrode of the driving transistor DT is connected to the first node N1. The driving transistor DT is turned on when a voltage at a gate-on level is applied through the first node N1, and may control the amount of a driving current flowing to the light-emitting element LD depending on a voltage provided to the gate electrode, that is, a voltage stored in the storage capacitor Cst.
A first electrode of the sensing transistor SST is connected to a j-th sensing line SLj, and a second electrode of the sensing transistor SST is connected to the first electrode of the light-emitting element LD. A gate electrode of the sensing transistor SST is connected to an i-th second gate line GL2i. The sensing transistor SST is turned on when a sensing signal at a gate-on level is applied through the i-th second gate line GL2i, and transmits a reference voltage applied through the j-th sensing line SLj, to the first electrode of the light-emitting element LD.
The light-emitting element LD outputs light corresponding to the driving current. The light-emitting element LD may be an organic light-emitting diode (OLED) or an ultra-small inorganic light-emitting diode having a size in a micro to nanoscale range, but the present disclosure is not limited thereto. Hereinafter, embodiments in which the light-emitting element LD is constructed as an organic light-emitting diode will be described.
In the present disclosure, the structure of the pixels PXs is not limited to that shown in
The gate driver 20 according to an embodiment of the present disclosure generates the gate signals on the basis of the gate driving control signal CONT1 applied from the timing controller 10, and the generated gate signals are sequentially applied to gate lines GL1 to GL8.
Referring to
Each stage circuit includes: shift registers SR1 and SR2 that are dependently connected through a carry signal line; and buffers BUF1 to BUF4 and BUF5 to BUF 8 that are connected to the shift registers SR1 and SR2, respectively.
The shift registers SR1 and SR2 of each stage circuit may receive a scan start signal SSP or a carry signal CR that is output from a previous stage circuit. For example, a first shift register SR1 of a first stage circuit may receive the scan start signal SSP, and a second shift register SR2 of the remaining stage circuits may receive the carry signal CR output from the previous stage circuit. The shift resistors SR1 and SR2 may be charged with a node voltage of an output end thereof in response to the scan start signal SSP or the carry signal CR.
In an embodiment, the shift registers SR1 and SR2 may further receive the carry signal CR output from the shift register of a next stage circuit. However, the embodiment is not limited thereto.
The shift registers SR1 and SR2 may further receive a reset signal RST. The shift registers SR1 and SR2 may discharge the node voltage of the output end thereof in response to the reset signal RST.
The buffers BUF1 to BUF4 and BUF5 to BUF8 of each stage circuit may be sequentially connected to the output end of the shift registers SR1 and SR2, respectively. In the embodiment, the stage circuit may have a multi-buffer structure in which multiple buffers BUF1 to BUF8 are connected to one of the shift registers SR1 and SR2. For example, a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1, and a fifth to an eighth buffers BUF5 to BUF8 may be connected to the second shift register SR2. Although it is illustrated in
Generally, since the shift registers SR1 and SR2 are formed of multiple transistors, the gate driver 20 occupies a large area when the gate driver 20 is disposed on the display panel 50, so that the bezel area may be widened.
In the embodiment, the stage circuit is configured such that one of the shift registers SR1 and SR2 outputs the gate signals to the plurality of gate lines GL1 to GL8. Therefore, the number of shift registers SR1 and SR2 within the gate driver 20 is reduced, and an area of the gate driver 20 is reduced, thereby enabling an implementation of a narrow bezel.
Each buffer BUF1 to BUF4 and BUF5 to BUF8 may output the clock signals CLK1 to CLKk in response to the node voltage of the output end of the connected shift registers SR1 and SR2. As the gate signals, the output clock signals CLK1 to CLKk are applied to the gate lines GL1 to GL8.
When the pixels PXs connected to the gate driver 20 have the same structure as illustrated in
The gate signals, as the carry signal CR, output from the last buffers BUF4 and BUF8 of each stage circuit may be applied to the shift register of the next stage circuit through the carry signal lines. Although it is illustrated in
Hereinafter, the multi-buffer structure of the stage circuit will be described in more detail.
Referring to
The shift resistor SR may charge and discharge a voltage of a Q node and a QB node (or simply referred as “charge and discharge a Q node and a QB node”) in response to the signals (scan start signal SSP or carry signal CR, reset signal RST) that are input. For example, the shift registers SR1 and SR2 may charge the voltage of the Q node in response to the scan start signal SSP or the carry signal CR, and may charge or discharge the node of the output end thereof in response to the clock signals CLK1 to CLKk. When the voltage of the Q node is charged, the voltage of the QB node may be discharged. When the voltage of the Q node is discharged, the voltage of the QB node may be charged.
Each buffer BUF1 to BUF4 may include respective first transistors T11, T12, T13, and T14 that are connected between the Q node and a Q′ nodes Q′1, Q′2, Q′3, and Q′4. A gate electrode of each first transistor T11, T12, T13, and T14 is connected to a high-potential voltage VDD. The high-potential voltage VDD may be a direct current voltage at a gate-on level. The first transistors T11, T12, T13, and T14 may transmit the voltage of the Q node to the Q′ nodes Q′1, Q′2, Q′3, and Q′4 while in a turn-on state.
A first end of each buffer BUF1 to BUF4 is configured to receive the clock signals CLK1 to CLK4, respectively, and a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4. Further, the buffers BUF1 to BUF4 include respective pull-up transistors TU1 to TU4 in which gate electrodes thereof are connected to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively. The pull-up transistors TU1 to TU4 are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4. The buffers BUF1 to BUF4 may further include pull-down transistors TD1 to TD4, respectively, that are turned on in response to the voltage of the QB node and output a low-potential voltage VSS to the gate lines GL1 to GL4. The low-potential voltage VSS may be a direct current voltage at a gate-off level.
In an embodiment as described above, the first transistors T11, T12, T13, and T14 remain in a turned-on state while the stage circuit is driven by the high-potential voltage VDD that is a direct current voltage. Then, the first transistors T11, T12, T13, and T14 may be quickly deteriorated, and characteristics thereof may vary. For example, when a threshold voltage of the first transistors T11, T12, T13, and T14 increases, the voltage of the Q′ node may decrease by the increased threshold voltage. Therefore, a gate-source voltage at the pull-up transistors TU1 to TU4 that are provided at the output buffers BUF1 to BUF4 is changed, so that outputs of the output buffers BUF1 to BUF4 are lowered and become inhomogeneous.
In order to avoid this problem, in the embodiment, the output buffers BUF1 to BUF4 further include second transistors T21, T22, T23, and 124 that are separately charging the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, in response to the voltage of the Q node. The second transistors T21, T22, T23, and T24 may be connected between the high-potential voltage VDD and the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, and a gate node thereof may be connected to the Q node. The second transistors T21, T22, T23, and T24 are turned-on when the Q node is charged, and transmit the high-potential voltage VDD to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, so that the Q′ nodes Q′1, Q′2, Q′3, and Q′4 may be effectively charged. In other words, the first transistor and the second transistor may be configured to separately control charging and discharging of each Q node of the plurality of output buffers BUF1 to BUF4.
In the embodiment, although the first transistors T11, T12, T13, and 114 are deteriorated, the Q′ nodes Q′1, Q′2, Q′3, and Q′4 are capable of being charged through the second transistors T21, T22, T23, and T24. Therefore, the pull-up transistors TU1 to TU4 of each of the output buffers BUF1 to BUF4 may be stably turned-on. Therefore, in the embodiment, an effect caused by the deterioration of the first transistors T11, T12, T13, and 114 may be minimized, and an output of the gate-on voltage to the gate lines may be uniformly performed and stabilized.
Compared with the embodiment in
Each buffer BUF1 to BUF4 may include: respective pull-up transistors TU1 to TU4 that are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4; and respective pull-down transistors TD1 to TD4 that are turned-on in response to the voltage of the QB node, and output the low-potential voltage VSS to the gate lines GL1 to GL4.
In the embodiment, the buffers BUF1 to BUF4 further includes third transistors T31, T32, T33, and 134, respectively, that are separately discharging the Q′ nodes Q′1, Q′2, Q′3, and Q′4 in response to the voltage of the QB node. The third transistors T31, T32, T33, and 134 may be connected between the low-potential voltage VSS and the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, and the gate node thereof may be connected to the QB node. The third transistors T31, T32, T33, and 134 are turned-on when the QB node is charged, and transmit the low-potential voltage VSS to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, so that the Q′ nodes Q′1, Q′2, Q′3, and Q′4 may be effectively discharged.
In the embodiment, although the first transistors T11′, T12′, T13′, T14′ are deteriorated, the Q′ nodes Q′1, Q′2, Q′3, and Q′4 are capable of being discharged through the third transistors T31, T32, T33, and T34. Therefore, the pull-up transistors TU1 to TU4 of the output buffers BUF1 to BUF4 may be stably turned-off. Therefore, in the embodiment, an effect caused by the deterioration of the first transistors T11′, T12′, T13′, and T14′ may be minimized, and an output of the gate-off voltage to the gate lines may be uniformly performed and stabilized.
Compared with the embodiment in
Each buffer BUF1 to BUF4 may include: respective pull-up transistors TU1 to TU4 that are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4; and respective pull-down transistors TD1 to TD4 that are turned-on in response to the voltage of the QB node, and output the low-potential voltage VSS to the gate lines GL1 to GL4.
In the embodiment, the buffers BUF1 to BUF4 further includes third transistors T31, T32, T33, and 134, respectively, that are separately discharging the Q′ nodes Q′1, Q′2, Q′3, and Q′4 in response to the voltage of the QB node. The third transistors T31, T32, T33, and T34 may be connected between the low-potential voltage VSS and the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, and the gate node thereof may be connected to the QB node. The third transistors T31, T32, T33, and 134 are turned-on when the QB node is charged, and transmit the low-potential voltage VSS to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, so that the Q′ nodes Q′1, Q′2, Q′3, and Q′4 may be effectively discharged.
Referring to
In the embodiment, each buffer BUF1 to BUF4 further includes respective second transistors T21, T22, T23, and 124 that are separately charging the Q′ nodes Q′1, Q′2, Q′3, and Q′4 in response to the voltage of the Q node. The second transistors T21, T22, T23, and T24 may be connected between the high-potential voltage VDD and the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, and the gate node thereof may be connected to the Q node. The second transistors T21, T22, T23, and T24 are turned-on when the Q node is charged, and transmit the high-potential voltage VDD to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, so that the Q′ nodes Q′1, Q′2, Q′3, and Q′4 may be effectively charged.
In addition, in the embodiment, each buffer BUF1 to BUF4 further includes respective third transistors T31, T32, T33, and 134 that are separately discharging the Q′ nodes Q′1, Q′2, Q′3, and Q′4 in response to the voltage of the QB node. The third transistors T31, T32, T33, and 134 may be connected between the low-potential voltage VSS and the Q′ nodes Q′1, Q′2, Q′3, and Q′4, respectively, and the gate node thereof may be connected to the QB node. The third transistors T31, T32, T33, and 134 are turned-on when the QB node is charged, and transmit the low-potential voltage VSS to the Q′ nodes Q′1, Q′2, Q′3, and Q′4, so that the Q′ nodes Q′1, Q′2, Q′3, and Q′4 may be effectively discharged.
In
It will be understood by those skilled in the art that the present disclosure can be embodied in other specific forms without changing the technical idea or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. The scope of the present disclosure is characterized by the appended claims rather than the detailed description described above, and it should be construed that all alterations or modifications derived from the meaning and scope of the appended claims and the equivalents thereof fall within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0186713 | Dec 2020 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20130100007 | Yamamoto | Apr 2013 | A1 |
| 20130222357 | Tseng | Aug 2013 | A1 |
| 20140044228 | Jang | Feb 2014 | A1 |
| 20140241487 | Yamazaki | Aug 2014 | A1 |
| 20150015474 | Miyake | Jan 2015 | A1 |
| 20200135132 | Tanaka | Apr 2020 | A1 |
| 20200394960 | Yuan | Dec 2020 | A1 |
| Number | Date | Country |
|---|---|---|
| 10-20150025784 | Mar 2015 | KR |
| 10-2020-0081071 | Jul 2020 | KR |
| 10-2138318 | Aug 2020 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20220208114 A1 | Jun 2022 | US |
