Patent Grant
10089948
This application is a national phase entry under 35 U.S.C. § 371 of PCT patent application No. PCT/CN2016/109406, filed on Dec. 12, 2016, which claims priority of Chinese Patent Application No. 201610192823.8, filed Mar. 30, 2016, the entire contents of both of which are incorporated herein by reference.
The present invention relates to display technology, more particularly, to a gate driver on array (GOA) unit, a related GOA unit, a display device containing the GOA unit, and a method for driving the GOA unit.
Liquid crystal display (LCD) devices often include active-matrix LCDs (AMLCDs) and passive-matrix LCDs (PMLCDs). In an AMLCD, each pixel includes a thin-film transistor (TFT). Often, the gate electrode of the TFT is coupled to a horizontally arranged scanning line, i.e., horizontal scanning line. The drain electrode of the TFT is coupled to a vertically arranged data line, i.e., vertical data line. The source electrode of the TFT is coupled to a pixel electrode. A suitable voltage is applied on the horizontal scanning line to turn on all the TFTs coupled to the horizontal scanning line such that the pixel electrodes coupled to these TFTs are electrically coupled to the vertical data lines. Display signals transmitted by the vertical data lines can be written into corresponding pixels to control the light-transmission levels of the LC molecules. By controlling the light-transmission levels, the colors displayed by the AMLCD can be controlled or changed.
Currently, an external gate driving integrated circuit or gate driving IC coupled to the display panel is often used to drive the horizontal scanning lines in the display panel of an AMLCD. The gate driving IC is often configured to control the charging and discharging of each level of horizontal scanning lines. Meanwhile, gate driver on array (GOA) technology integrates the gate driving ICs on the array substrate. By applying the GOA technology, fewer GOA ICs need to be used in the AMLCD device. The fabrication cost and power consumption of the AMLCD device can be reduced. The GOA technology also enables narrow bezel to be formed in the AMLCD device.
However, in a conventional GOA unit, parasitic capacitance in the transistor of the pull-up module often causes the pull-up node, i.e., the node connecting the gate electrode of the transistor in the pull-up module and the gate output terminal, susceptible to noise.
In one aspect, the present invention provides a gate driver on array (GOA) unit, including: a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module, a pull-up node being coupled to the buffering module, the discharging module, the pull-up module, and the charging module, and a pull-down node being coupled to the discharging module and the retaining module. The buffering module, being coupled to an input signal terminal and a pull-up node and controlled by a voltage of the input signal terminal, is configured to output the voltage of the input signal terminal into the pull-up node. The pull-up module, being coupled to a first clock signal terminal, the pull-up node, and an output signal terminal and controlled by a voltage of the pull-up node, is configured to output a voltage of the first clock signal terminal into the output signal terminal. The pull-down module, being coupled to the output signal terminal, a reset signal terminal, and a power signal terminal and controlled by a voltage of the reset signal terminal, is configured to output a voltage of the power signal terminal into the output signal terminal. The retaining module, being coupled to the first clock signal terminal, the power signal terminal, the pull-up node, the pull-down node, and a second clock signal terminal and controlled by a voltage of the second clock signal terminal, is configured to output the voltage of the second clock signal terminal into the pull-down node or write a voltage of the first clock signal terminal into the pull-down node. The charging module, being coupled to the pull-up node and the output signal terminal, is configured to store voltages of the pull-up node and the output signal terminal. The discharging module, being coupled to the reset signal terminal, the pull-up node, the power signal terminal, the pull-down node, and the output signal terminal, is configured to output the voltage of the power signal terminal into the pull-up node or into the output signal terminal when the discharging module is controlled by voltages of the pull-down node and the reset signal terminal, and configured to write the voltage of the power signal terminal into the pull-up node and the output signal terminal when the discharging module is controlled by the voltage of the pull-down node.
Optionally, the retaining module further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a diode, the first transistor having a first electrode coupled to the second clock signal terminal, a second electrode of the first transistor coupled to a switch electrode of the second transistor, a switch electrode of the fifth transistor, and a second electrode of the fourth transistor, and a switch electrode of the first transistor coupled to the second clock signal terminal; the second transistor having a first electrode coupled to the second clock signal terminal, a second electrode coupled to the pull-down node; the third transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-down node, and a switch electrode coupled to the pull-up node and a switch electrode of the fourth transistor; the fourth transistor having a first electrode coupled to the power signal terminal; the fifth transistor having a first electrode coupled to a cathode of the diode, and a second electrode coupled to the pull-down node; and the diode having an anode coupled to the first clock signal terminal.
Optionally, the buffering module further includes a sixth transistor, the sixth transistor having a first electrode coupled to the input signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the input signal terminal.
Optionally, the pull-up module includes a seventh transistor, the seventh transistor having a first electrode coupled to the first clock signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the pull-up node.
Optionally, the pull-down module includes an eighth transistor, the eighth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the reset signal terminal.
Optionally, the charging module includes a capacitor, the capacitor having a terminal coupled to the pull-up node, and another terminal coupled to the output signal terminal.
Optionally, the discharging module includes a ninth transistor, a tenth transistor, and an eleventh transistor, the ninth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the reset signal terminal; the tenth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the pull-down node; and the eleventh transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the pull-down node.
Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are N-type transistors.
Optionally, the first electrode of any of the transistors is a source electrode, the second electrode of any of the transistors is a drain electrode, and the switch electrode of any of the transistors is a gate electrode.
Another aspect of the present disclosure provides a method for driving a disclosed GOA unit, including implementing a pull-down stage and a retaining stage. The pull-down stage includes: applying a first-level voltage on the first clock signal terminal, the input signal terminal, and the power signal terminal; applying a second-level voltage on the second clock signal terminal and the reset signal terminal; applying the second-level voltage on a terminal of the discharging module coupled to the retaining module, applying the first-level voltage on the output signal terminal. The retaining stage includes: applying the first-level voltage on the second clock signal terminal, the input signal terminal, the reset signal terminal, and the power signal terminal; applying the second-level voltage on the first clock signal terminal; applying the second-level voltage on the pull-down node; and applying the first-level voltage of the power signal terminal on the pull-up node and the output signal terminal.
Optionally, the first-level voltage is a voltage of low voltage level and the second-level voltage is a voltage of high voltage level.
Optionally, the retaining module includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the diode; the buffering module includes the sixth transistor; the pull-up module including the seventh transistor; the pull-down module includes the eighth transistor; the charging module includes the capacitor; the discharging module includes the ninth transistor, the tenth transistor, and the eleventh transistor. In the pull-down stage, the first-level voltage is applied on the first clock signal terminal, the input signal terminal, and the power signal terminal, and the second-level voltage is applied on the second clock signal terminal and the reset signal terminal, so that, the first transistor, the second transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are turned on, the second transistor writing the second-level voltage of the second clock signal terminal into the pull-down node, the tenth transistor and the ninth transistor writing the first-level voltage of the power signal terminal into the pull-up node, the eleventh transistor and the eighth transistor writing the first-level voltage of the power signal terminal into the output signal terminal; and in the retaining stage, a first-level voltage is applied on the second clock signal terminal, the input signal terminal, the reset signal terminal, and power signal terminal, and a second-level voltage is applied on the first clock signal terminal, so that, the second transistor, the fifth transistor, the tenth transistor, and the eleventh transistor are turned on, the fifth transistor writing the second-level voltage of the first clock signal terminal into the pull-down node, the tenth transistor writing the first-level voltage of the power signal terminal into the pull-up node and the output signal terminal.
Another aspect of the present disclosure provides a GOA circuit, including at least two disclosed GOA units cascading together.
Another aspect of the present disclosure provides a display device, including one or more of the disclosed GOA units.
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.
The disclosure will now describe more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
Often, a conventional GOA circuit includes a plurality of cascading GOA units. Each GOA unit corresponds to a pixel group, where one pixel group includes a plurality of pixels. A conventional GOA unit often includes a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module. The buffering module is used as the input module of the GOA unit for inputting the output voltage, of the gate output terminal of the gate of the previous level, into the present GOA unit. The pull-up module is often configured to pull the output voltage of the gate output terminal up to a high voltage level. The pull-down module is often configured to pull the output voltage of the gate output terminal to a low voltage level. The retaining module is often configured to retain the voltage level of the output voltage of the gate output terminal. The charging module is often configured to ensure the transistor contained in the pull-up module to be turned on properly during operation. The discharging module is often configured to discharge the charging module and turn off the pull-up module.
In a discharging-retaining phase, the transistor contained in the pull-up module of the conventional GOA unit often has parasitic capacitance. The voltage at the pull-up node, i.e., the node connecting to the gate electrode of the transistor in the pull-up module, is pulled up to a higher voltage level. As a result, the transistor in the pull-up module is turned on, and the first clock signal of the GOA unit starts charging the gate output terminal again. Thus, noise exists at the pull-up node and the gate output terminal.
The transistors used in the embodiments of the present disclosure may be TFTs, field effect transistors (FETs), and/or any other suitable devices with similar properties. Based on the functions of a transistor in a circuit, the transistors applied in the embodiments of the present disclosure are mostly switching transistors. Because the source electrode and the drain electrode of a switching transistor are symmetric, the source electrode and the drain electrode of a switching transistor can switch or exchange. In the disclosed embodiments, to distinguish the source electrode and the drain electrode from the gate electrode, the source electrode is referred as a first electrode and the drain electrode is referred as a second electrode. Accordingly, a gate electrode is referred as a switch electrode. For illustrative purposes, in the figures of the present disclosure, the gate electrode of a transistor is located at the middle terminal of the transistor, the source electrode is located at the input signal terminal, and the drain electrode is located at the output signal terminal. The switching transistors used in the embodiments of the present disclosure may be N type switching transistors, which can be turned on when a high-level voltage is applied on the gate electrode of a switching transistor and are turned off when a low-level voltage is applied on the gate electrode of a switching transistor. In the present disclosure, the first-level voltage is a low-level voltage and the second-level voltage is a high-level voltage.
In the present disclosure, for illustrative purposes, the term “a voltage of a certain object”, “a voltage at a certain location”, or the alike may represent the voltage provided, outputted and/or applied by the object or location. The object or location may be any suitable signal terminals and/or nodes in a circuit. Also, the voltage level of a terminal may represent the voltage level of the signal/voltage applied by the terminal.
One aspect of the present disclosure provides a GOA unit.
The GOA unit according to the present disclosure may include a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module. In a GOA unit of the present disclosure, the retaining module, controlled by the voltage of a clock signal terminal, may write the voltage of the clock signal terminal into the pull-down node or may write the voltage of the first clock signal terminal into the pull-down node. The discharging module, controlled by the voltages of the pull-down node and the reset signal terminal, may write the voltage of the power signal terminal into the pull-up node or into the output signal terminal. As a result, embodiments of the present disclosure may lower the voltages at the pull-up node and the output signal terminal, and reduce the noise at the pull-up node and the output signal terminal of the GOA unit.
The buffering module 110 may be coupled to an input signal terminal IPT and a pull-up node pu. Controlled by the voltage of the input signal terminal IPT, the buffering module 110 may write the voltage of the input signal terminal IPT into the pull-up node pu. In the present disclosure, being “coupled to” may refers to any suitable direct or indirect connection, e.g., electrical connection or mechanical connection, between two objects.
The pull-up module 120 may be coupled to the first clock signal terminal CLK, the pull-up node pu, and an output signal terminal OPT. Controlled by the voltage of the pull-up node pu, the pull-up module 120 may write the voltage of the first clock signal terminal CLK into the output signal terminal OPT.
The pull-down terminal 130 may be coupled to the output signal terminal OPT, a reset signal terminal RST, and a power signal terminal VSS. Controlled by the voltage of the reset signal terminal RST, the pull-down module 130 may write the voltage of the power signal terminal VSS into the output signal terminal OPT.
The retaining module 140 may be coupled to the first clock signal terminal CLK, the power signal terminal VSS, the pull-up node pu, a pull-down node pd, and a second clock signal terminal CLKB. Controlled by the voltage of the second clock signal terminal CLKB, the retaining module 140 may write the voltage of the second clock signal terminal CLKB into the pull-down node pd. Alternatively, controlled by the voltage of the second signal terminal CLKB, the regaining module 140 may write the voltage of the first clock signal terminal CLK into the pull-down node pd.
The charging module 150 may be coupled to the pull-up node pu and the output signal terminal OPT to store the voltages of the pull-up node pu and the output signal terminal OPT.
The discharging module 160 may be coupled to the reset signal terminal RST, the pull-up node pu, the power signal terminal VSS, the pull-down terminal pd, and the output signal terminal OPT. Controlled by the voltages of the pull-down node pd and the reset signal terminal RST, the discharging module 160 may write the voltage of the power signal terminal VSS into the pull-up node pu or into the output signal terminal OPT. Alternatively, controlled by the voltage of the pull-down node pd, the discharging module 160 may write the voltage of the power signal terminal VSS into the pull-up node pu and the output signal terminal OPT.
According to the disclosed GOA unit, the retaining module, controlled by the voltage of the second clock signal terminal, may write the voltage of the second clock signal terminal to the pull-down node or write the voltage of the first clock signal terminal to the pull-down node. Thus, the discharging module, controlled by the voltages of the pull-down node and the reset signal terminal, may write the voltage of the power signal terminal to the pull-up node or to the output signal terminal. Compared to conventional technology, the voltages at the pull-up node and the output signal terminal may be lower, and noise at the pull-up node and the output signal terminal of the disclosed GOA unit may be reduced.
Further,
As shown in
The buffering module 110 may be coupled to the input signal terminal IPT and the pull-up node pu. Controlled by the voltage of the input signal terminal IPT, the buffering module 110 may write the voltage of the input signal terminal IPT into the pull-up node pu.
The pull-up module 120 may be coupled to the first clock signal terminal CLK, the pull-up node pu, and the output signal terminal OPT. Controlled by the voltage of the pull-up node pu, the pull-up module 120 may write the voltage of the first clock signal terminal CLK into the output signal terminal OPT.
The pull-down terminal 130 may be coupled to the output signal terminal OPT, the reset signal terminal RST, and the power signal terminal VSS. Controlled by the voltage of the reset signal terminal RST, the pull-down module 130 may write the voltage of the power signal terminal VSS into the output signal terminal OPT.
The retaining module 140 may be coupled to the first clock signal terminal CLK, the power signal terminal VSS, the pull-up node pu, the pull-down node pd, and the second clock signal terminal CLKB. Controlled by the voltage of the second clock signal terminal CLKB, the retaining module 140 may write the voltage of the second clock signal terminal CLKB into the pull-down node pd or write the voltage of the first clock signal terminal CLK into the pull-down node pd.
The charging module 150 may be coupled to the pull-up node pu and the output signal terminal OPT to store the voltages of the pull-up node pu and the output signal terminal OPT.
The discharging module 160 may be coupled to the reset signal terminal RST, the pull-up node pu, the power signal terminal VSS, the pull-down terminal pd, and the output signal terminal OPT. Controlled by the voltages of the pull-down node pd and the reset signal terminal RST, the discharging module 160 may write the voltage of the power signal terminal VSS into the pull-up node pu or write the voltage of the power signal terminal VSS to the output signal terminal OPT. Alternatively, controlled by the voltage of the pull-down node pd, the discharging module 160 may write the voltage of the power signal terminal VSS to the pull-up node pf and the output signal terminal OPT.
As shown in
The first electrode of the first transistor M1 may be coupled to the second clock signal terminal CLKB. The second electrode of the first transistor M1 may be coupled to the switch electrode of the second transistor M2, a switch electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4. The switch electrode of the first transistor M1 may be coupled to the second clock signal terminal CLKB. The node PD-CN in
The first electrode of the second transistor M2 may be coupled to the second clock signal terminal CLKB. The second electrode of the second transistor M2 may be coupled to the pull-down node pd.
The first electrode of the third transistor M3 may be coupled to the power signal terminal VSS. The second electrode of the third transistor M3 may be coupled to the pull-down node pd. The switch electrode of the third transistor M3 may be coupled to the pull-up node pu and the switch electrode of the fourth transistor M4.
The first electrode of the fourth transistor M4 may be coupled to the power signal terminal VSS.
The first electrode of the fifth transistor M5 may be coupled to the cathode of the diode D1. The second electrode of the fifth transistor M5 may be coupled to the pull-down node pd.
The anode of the diode D1 may be coupled to the first clock signal terminal CLK.
The buffering module 110 may include a sixth transistor M6.
The first electrode of the sixth transistor M6 may be coupled to the input signal terminal IPT. The second electrode of the sixth M6 may be coupled to the pull-up node pu. The switch electrode of the sixth transistor M6 may be coupled to the input signal terminal IPT.
The pull-up module 120 may include a seventh transistor M7.
The first electrode of the seventh transistor M7 may be coupled to the first clock signal terminal CLK. The second electrode of the seventh transistor M7 may be coupled to the output signal terminal OPT. The switch electrode of the seventh transistor M7 may be coupled to the pull-up node pu.
The pull-down module 130 may include an eighth transistor M8.
The first electrode of the eighth transistor M8 may be coupled to the power signal terminal VSS. The second electrode of the eighth transistor M8 may be coupled to the output signal terminal OPT. The switch electrode of the eighth transistor M8 may be coupled to the reset signal terminal RST.
The charging module 150 may include a capacitor C1.
One terminal of the capacitor C1 may be coupled to the pull-up node pu. The other terminal of the capacitor C1 may be coupled to the output signal terminal OPT.
The discharging module 160 may include a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
The first electrode of the ninth transistor M9 may be coupled to the power signal terminal VSS. The second electrode of the ninth transistor M9 may be coupled to the pull-up node pu. The switch electrode of the ninth transistor M9 may be coupled to the reset signal terminal RST.
The first electrode of the tenth transistor M10 may be coupled to the power signal terminal VSS. The second electrode of the tenth transistor M10 may be coupled to the pull-up node pu. The switch electrode of the tenth transistor M10 may be coupled to the pull-down node pd.
The first electrode of the eleventh transistor M11 may be coupled to the power signal terminal VSS. The second electrode of the eleventh transistor M11 may be coupled to the output signal terminal OPT. The switch electrode of the eleventh electrode may be coupled to the pull-down node pd.
In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 may be N-type transistors. In certain other embodiments, dependent on the applications, the transistors M1-M11 may also be P-type transistors. The specific types of transistors M1-M11 should not be limited by the embodiments of the present disclosure.
In some embodiments, from the first transistor M1 to the eleventh transistor M11, each first electrode of a transistors may be the source electrode or the transistor, each second electrode of a transistor may be the drain electrode of the transistor, and each switch electrode of a transistor may be the gate electrode of the transistor.
As shown in
In a discharging-retaining phase, the first clock signal terminal CLK may input a second-level voltage, the second clock signal terminal CLKB may input a first-level voltage, the input signal terminal IPT may input a first-level voltage, the reset signal terminal RST may input a first-level voltage, and the power signal terminal VSS may input a first-level voltage. Accordingly, the node PD-CN may maintain a high voltage level. The second transistor M2 and the fifth transistor M5 may be kept on. The first clock signal terminal CLK may continue to pull up the voltage level at the pull-down node pd through the diode D1 and the fifth transistor M5. The tenth transistor M10 and the eleventh transistor M11 may be kept on. The tenth transistor M10 may write the first-level voltage of the power signal terminal VSS into the pull-up node pu and the output signal terminal OPT. The pull-up node pu and the output signal terminal OPT may maintain a low voltage level such that the noise at the pull-up node pu and the output signal terminal OPT may be reduced.
In the embodiments of the present disclosure, the fifth transistor M5 and the diode D1 may be added in the disclosed GOA unit, as shown in
Thus, according to the disclosed GOA unit, the retaining module, controlled by the voltage of the second clock signal terminal, may write the voltage of the second clock signal terminal into the pull-down node or may write the voltage of the first clock signal terminal into the pull-down node. The discharging module, controlled by the voltages of the pull-down node and the reset signal terminal, may write the voltage of the power signal terminal into the pull-up node or into the output signal terminal. Compared to conventional technology, the voltages at the pull-up node and the output signal terminal may be lower, and the noise at the pull-up node and the output signal terminal of the GOA unit may be reduced.
Step S301 may be performed in a pull-down stage T1. In the pull-down stage T1, the first clock signal terminal CLK may input a first-level voltage, the second clock signal terminal CLKB may input a second-level voltage, the input signal terminal IPT may input a first-level voltage, the reset signal terminal RST may input a second-level voltage, and the power signal terminal VSS may input a first-level voltage. Accordingly, the second-level voltage of the second clock signal terminal CLKB may be written into the pull-down node pd, and the first-level voltage of the power signal terminal VSS may be written into the pull-up node pu and the output signal terminal OPT.
Step S302 may be performed in a retaining stage T2. In the retaining stage T2, the first clock signal terminal CLK may input a second-level voltage, the second clock signal terminal CLKB may input a first-level voltage, the input signal terminal IPT may input a first-level voltage, the reset signal terminal RST may input a first-level voltage, and the power signal terminal VSS may input a first-level voltage. Accordingly, the second-level voltage of the first clock signal terminal CLK may be written into the pull-down node pd, and the first-level voltage of the power signal terminal VSS may be written into the pull-up node pu and the output signal terminal OPT.
Optionally, as shown in
Step S301 may include, in the pull-down stage T1, the first clock signal terminal CLK inputting a first-level voltage, the second clock signal terminal CLKB inputting a second-level voltage, the input signal terminal IPT inputting a first-level voltage, the reset signal terminal RST inputting a second-level voltage, and the power signal terminal VSS inputting a first-level voltage. Accordingly, the first transistor M1, the second transistor M2, and the fifth transistor M5 may be turned on. The second transistor M2 may write the second-level voltage of the second clock signal terminal CLKB into the pull-down node pd. The tenth transistor M10 and the eleventh transistor M11 may be turned on, and the ninth transistor M9 and the eighth transistor M8 may be turned on. The tenth transistor M10 and the ninth transistor M9 may write the first-level voltage of the power signal terminal VSS into the pull-up node pu. The eleventh transistor M11 and the eighth transistor M8 may write the first-level voltage of the power signal terminal VSS into the output signal terminal OPT.
The pull-down stage in step S301 may be the discharging-pull down phase. In the discharging-pull down phase, the first clock signal terminal CLK may input a first-level voltage, the second clock signal terminal CLKB may input a second-level voltage, the input signal terminal IPT may input a first-level voltage, the reset signal terminal RST may input a second-level voltage, and the power signal terminal VSS may input a first-level voltage. The second signal terminal CLKB may be at a high voltage level. The first transistor M1, the second transistor M2, and the fifth transistor M5 may be turned on. The voltage level at the pull-down node pd may be pulled up. The tenth transistor M10 and the eleventh transistor M11 may be turned on. The voltage of the reset signal terminal RST may be at a high voltage level. The ninth transistor M9 and the eighth transistor M8 may be turned on. At this point, the tenth transistor M10 and the ninth transistor M9 may write the first-level voltage of the power signal terminal VSS into the first pull-up node pu. The eleventh transistor M11 and the eighth transistor M8 may write the first-level voltage of the power signal terminal VSS into the output signal terminal OPT. Accordingly, the power signal terminal VSS may pull down the voltage levels of the pull-up node pu and the power signal terminal OPT. Meanwhile, the diode D1, having one directional conductivity, may prevent the first clock signal terminal CLK from pulling down the voltage level of the pull-down node pd and adversely affecting the discharging process.
The step S302 may include, in the retaining stage T2, the first clock signal terminal CLK inputting a second-level voltage, the second clock signal terminal CLKB inputting a first-level voltage, the input signal terminal IPT inputting a first-level voltage, the reset signal terminal RST inputting a first-level voltage, and the power signal terminal VSS inputting a first-level voltage. The second transistor M2 and the fifth transistor M5 may be turned on. The fifth transistor M5 may write the second-level voltage of the first clock signal terminal CLK into the pull-down node pd. The tenth transistor M10 and the eleventh transistor M11 may be turned on. The tenth transistor M10 may write the first-level voltage of the power signal terminal VSS into the pull-up node pu and the output signal terminal OPT.
The retaining stage T2 of step S302 may be the discharging-retaining phase. In the discharging-retaining phase, the first clock signal terminal CLK may input a second-level voltage, the second clock signal terminal CLKB may input a first-level voltage, the input signal terminal IPT may input a first-level voltage, the reset signal terminal RST may input a first-level voltage, and the power signal terminal VSS may input a first-level voltage. The voltage at PD-CN node may be at a high voltage level. The second transistor M2 and the fifth transistor M5 may be kept on. The fifth transistor M5 may write the second-level voltage of the first clock signal terminal CLK into the pull-down node pd. Accordingly, the first clock signal terminal CLK may pull up the voltage level at the pull-down node pd through the diode D1 and the fifth transistor M5. Meanwhile, the tenth transistor M10 and the eleventh transistor M11 may be kept on. The tenth transistor M10 may write the first-level voltage of the power signal terminal VSS to the pull-up node pu. The eleventh transistor M11 may write the first-level voltage of the power signal terminal VSS to the output signal terminal OPT. The voltages at the pull-up node pu and the output signal terminal OPT may be kept at a low voltage level such that the noise at the pull-up node pu and the output signal terminal OPT may be reduced.
In the disclosed embodiments, the voltage changes, in the pull-down stage T1 and the retaining stage T2, of the input signal terminal IPT, the first clock signal terminal CLK, the second clock signal terminal CLKB, the pull-up node pu, the pull-down node pd, the output signal terminal OPT, and the reset signal terminal RST may be illustrated in
The voltage changes, in the pull-down stage T1 and the retaining stage T2, of the conventional GOA unit shown in
In the present disclosure, the retaining module, controlled by the voltage of the second clock signal terminal, may write the voltage of the second clock signal terminal into the pull-down node or write the voltage of the first clock signal terminal into the pull-down node. Thus, the discharging module, controlled by the voltages of the pull-down node and the reset signal terminal, may write the voltage of the power signal terminal to the pull-up node or to the output signal terminal. Compared to conventional technology, the voltages at the pull-up node and the output signal terminal may be lower, and noise at the pull-up node and the output signal terminal of the disclosed GOA unit may be reduced.
Another aspect of the present disclosure provides a GOA circuit. The GOA circuit may include at least two cascading GOA units. Each GOA unit may be the GOA unit shown in
The disclosed GOA circuit may include at least two cascading GOA units. For each GOA unit, the retaining module, controlled by the voltage of the second clock signal terminal, may write the voltage of the second clock signal terminal to the pull-down node or write the voltage of the first clock signal terminal to the pull-down node. Thus, the discharging module, controlled by the voltages of the pull-down node and the reset signal terminal, may write the voltage of the power signal terminal to the pull-up node or to the output signal terminal. Compared to conventional technology, the voltages at the pull-up node and the output signal terminal may be lower, and noise at the pull-up node and the output signal terminal of the disclosed GOA unit may be reduced.
Another aspect of the present disclosure provides a display device. The display device may include one or more of the disclosed GOA circuits. The display device may be an LCD panel, an electronic paper, an organic light-emitting diode (OLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital frame, a navigation device, or any suitable parts or products with display functions.
The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first”, “second”, etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016 1 0192823 | Mar 2016 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2016/109406 | 12/12/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/166867 | 10/5/2017 | WO | A |
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| 102012591 | Apr 2011 | CN |
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| State Intellectual Property Office of the P.R.C (SIPO) Office Action 1 for 201610192823.8 dated Aug. 28, 2017 21 Pages (including translation). |
| The World Intellectual Property Organization (WIPO) International Search Report and Written Opinion for PCT/CN2016/109406 dated Mar. 1, 2017; 14 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20180197496 A1 | Jul 2018 | US |
