Gate driving circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of stage circuits. The stage circuit includes an input module, a first output module, a second output module, a voltage stabilizing module, and a first driving control module. The voltage stabilizing module includes a first transistor whose gate receives a clock signal. When the gate driving circuit operates in a low power consumption mode, the clock signal turns on the first transistor to reduce a power consumption of the gate driving circuit by reducing a frequency of the clock signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a US national phase application based upon an International Application No. PCT/CN2023/128882, filed on Oct. 31, 2023, which claims priority to Chinese Patent Application No. 202311300460.1, filed on Oct. 8, 2023, and entitled “GATE DRIVING CIRCUIT AND DISPLAY PANEL”. The entire disclosures of the above application are incorporated herein by reference.

FIELD OF INVENTION

The present application relates to the field of display technology, more specifically to a gate driving circuit and a display panel.

BACKGROUND

In display panels, gate driving circuits are usually used to provide corresponding gate driving signals for different transistors. The gate driving signal includes a plurality of stage circuits, and each stage circuit outputs a gate driving signal of a corresponding stage.

In the related art, in order to reduce a power consumption of the stage circuit, an operation mode of a gate circuit includes a normal mode and a low power consumption mode. In the low power consumption mode, frequencies of multiple input signals of the stage circuit are reduced compared to the normal mode. For example, reduce frequencies of a start signal (STV) and a clock signal (CK). However, reducing the frequency of the clock signal may cause a control node used for an output of a control stage circuit to be in a floating state. This further causes a voltage of a control node to leak, causing abnormalities in a display panel.

SUMMARY

This application provides a gate driving circuit and a display panel to improve technical problems of related technologies, wherein in a low power consumption mode, a frequency of a clock signal is reduced, causing a control node used for an output of a control stage circuit to be in a floating state, which further causes a voltage of a control node to leak and causes abnormalities in a display panel.

In the first aspect, this application provides a gate driving circuit, the gate driving circuit comprises a plurality of cascaded stage circuits, wherein the stage circuit comprises: an input module configured to receive a start signal or a stage transmission signal output by other stage circuits and configured to control a voltage of a second node; a first output module configured to output a first gate driving signal according to a potential of a third node and a potential of a fourth node; a second output module configured to output a second gate driving signal according to a potential of the second node; a voltage stabilizing module electrically connected to a first power line and a second power line and configured to transmit a voltage on the first power line or a voltage on the second power line to the second node according to a voltage of the fourth node; a first driving control module configured to control the voltage of the fourth node according to the voltage of the second node; wherein the voltage stabilizing module comprises a first transistor, a gate of the first transistor is configured to receive a clock signal, and an operation mode of the gate driving circuit comprises a low power consumption mode, when the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

In one embodiment, the first transistor is an N-channel thin film transistor, and the first voltage is a high potential.

In one embodiment, the first transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both configured to receive the clock signal.

In one embodiment, the voltage stabilizing module further comprises a second transistor, a gate of the second transistor is electrically connected to the fourth node, one of a source or a drain of the second transistor is electrically connected to the first power line, the other one of the source or the drain of the second transistor is electrically connected to one of a source or a drain of the first transistor, the other one of the source or the drain of the first transistor is electrically connected to the second node; wherein the first transistor and the second transistor have different channel types.

In one embodiment, when the gate driving circuit is in the low power consumption mode, the voltage of the fourth node turns on the second transistor to transmit the voltage on the first power line to one of the source or the drain of the first transistor.

In one embodiment, the voltage stabilizing module further comprises a third transistor, one of a source or a drain of the third transistor is electrically connected to the second power line, and another one of the source or the drain of the third transistor is electrically connected to the second node, and a gate of the third transistor is connected to the fourth node.

In one embodiment, when the gate driving circuit is in a low power consumption mode, a voltage of the fourth node turns off the third transistor.

In one embodiment, the third transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the third transistor and a second gate of the third transistor are both electrically connected to the fourth node.

In one embodiment, the stage circuit further comprises a reset module, and the reset module controls a voltage of the second node according to a reset signal.

In one embodiment, the reset module comprises a fourth transistor, one of a source or a drain of the fourth transistor is connected to the first power line, another of the source or the drain of the fourth transistor is electrically connected to the second node, and a gate of the fourth transistor receives the reset signal.

In one embodiment, in a first frame of operation of the gate driving circuit, the reset signal controls the fourth transistor to turn on before a pulse of the start signal arrives, such that a voltage on the first power line is transmitted to the second node.

In one embodiment, the first driving control module is electrically connected to the second node and the fourth node, and the first driving control module outputs a voltage inverted with a voltage of the second node to the fourth node.

In one embodiment, the first driving control module comprises a fifth transistor and a sixth transistor, one of a source or a drain of the fifth transistor is electrically connected to the first power line, another of the source or the drain of the fifth transistor is electrically connected to the fourth node, one of a source or a drain of the sixth transistor is electrically connected to a third power line, another of the source or the drain of the sixth transistor is electrically connected to the fourth node, and a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the second node;

• • wherein the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

In one embodiment, the sixth transistor is a double-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node.

In one embodiment, when the gate driving circuit is in a low power consumption mode, the sixth transistor is turned on and outputs a voltage on the third power line to the fourth node.

In one embodiment, the stage circuit further comprises: a second driving control module, wherein the second driving control module is electrically connected between the second node and the third node, a control terminal of the second driving control module is electrically connected to a driving control line, and the second driving control module is configured to control a conduction between the second node and the third node.

In one embodiment, the second driving control module is configured to eliminate a first pulse of the second node appearing in one frame and retain a second pulse of the second node appearing in the same frame.

In a second aspect, this application provides a display panel, the display panel comprises a pixel circuit and the gate driving circuit in at least one of the above embodiments. The pixel circuit comprises a writing transistor configured to control input of a data signal and a compensation transistor configured to control input of the data signal to a gate of a driving transistor. An output terminal of the first output module is electrically connected to a gate of the writing transistor, and an output terminal of the second output module is electrically connected to a gate of the compensation transistor.

Advantageous Effect

Advantageous effect of this application: The voltage stabilizing module is electrically connected to the second node. When the gate driving circuit is in the low power consumption mode, the first transistor may be turned on to maintain the potential of the second node. Therefore, when the clock signal is of low frequency, the potential of the second node may not decrease due to the influence of leakage. This can keep the potential of the second node at a high potential. Therefore, the gate driving circuit provided in this embodiment can reduce the power consumption of the gate driving circuit by reducing the frequency of the clock signal, and no display abnormality may occur. This further solves issues in related technologies that the reduction in clock signal frequency may cause the output of the stage circuit to be abnormal, resulting in display issues on the display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a gate driving circuit in the related art.

FIG. 2 is a timing diagram of some signals in the gate driving circuit shown in FIG. 1.

FIG. 3 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present application.

FIG. 4 is a timing diagram of some signals in the gate driving circuit shown in FIG. 3.

FIG. 5 is a timing diagram of some signals in the gate driving circuit shown in FIG. 1.

FIG. 6 is a timing diagram of some signals in the gate driving circuit shown in FIG. 3.

FIG. 7 is a timing diagram of the gate driving circuit shown in FIG. 3.

FIG. 8 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a first stage in FIG. 7.

FIG. 9 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a second stage in FIG. 7.

FIG. 10 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a third stage in FIG. 7.

FIG. 11 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a fourth stage in FIG. 7.

FIG. 12 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a fifth stage in FIG. 7.

FIG. 13 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a sixth stage in FIG. 7.

FIG. 14 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a seventh stage in FIG. 7.

FIG. 15 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in an eighth stage in FIG. 7.

FIG. 16 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a ninth stage in FIG. 7.

FIG. 17 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in a tenth stage in FIG. 7.

FIG. 18 is a schematic diagram of a state of the gate driving circuit shown in FIG. 3 in an eleventh stage in FIG. 7.

FIG. 19 is a schematic structural diagram of a cascade connection between different stages of circuits in the gate driving circuit shown in FIG. 3.

FIG. 20 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

FIG. 21 is a schematic structural diagram of a pixel circuit in the display panel shown in FIG. 20.

FIG. 22 is a timing diagram of the pixel circuit shown in FIG. 21.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

It should be understood that embodiments described here are only used to explain the present application and are not used to limit the present application.

Refer to FIGS. 1 and 2, FIG. 1 is a schematic structural diagram of a gate driving circuit in the related art. The gate driving circuit includes at least one of an input module 10, a second driving control module 70, a first driving control module 50, a first output module 20, a second output module 30, and a voltage stabilizing module 40.

The first output module 20 outputs a first gate driving signal. The second output module 30 outputs a second gate driving signal. For detailed description of the gate driving circuit, refer to the following related descriptions.

In order to reduce the power consumption of the stage circuit, in the low power consumption mode, frequencies of multiple input signals of the stage circuit are reduced. For example, reduce frequencies of a start signal (STV) and clock signals (CK, XCK).

However, during the application process, the inventor found that the reduction in the frequency of the clock signal may cause abnormal display of the display panel. As shown in a of FIG. 2, when the clock signal is in a high potential state for a long time, a transistor T2 and a first transistor T4 are all in an off state, and a second node K is in a floating state. However, due to a leakage current of the transistor T2, a potential of the second node K cannot be maintained for a long time, causing the second node K to leak through the transistor T2, and the potential of the second node K continues to decrease. When the potential of the second node K decreases to a certain potential, Vgs of a fifth transistor T3 becomes smaller and smaller, and finally reaches a critical value for turning on the fifth transistor T3. When the fifth transistor T3 is turned on, point P is at a high potential, and a third transistor T14 is turned on, pulling the potential of the second node K down to a low potential. Eventually, a transistor T9 is turned on and outputs a second gate driving signal, resulting in abnormal output.

That is to say, when a clock signal frequency is reduced in the gate driving circuit shown in FIG. 1, the above-mentioned specific issue may be caused. That is, when the frequency of the clock signal is reduced, the output of the stage circuit may be abnormal, causing display issues on the display panel.

In view of this, this embodiment provides a gate driving circuit. Referring to FIG. 1 to FIG. 22, as shown in FIG. 3, the gate driving circuit includes multiple stage circuits. The stage circuit includes at least one of an input module 10, a first output module 20, a second output module 30, a first driving control module 50, and a voltage stabilizing module 40.

The input module 10 receives a start signal or a stage transmission signal output by other stage circuits, and controls a voltage of the second node K. The first output module 20 outputs a first gate driving signal according to a potential of a third node Q and a potential of a fourth node P. The second output module 30 outputs a second gate driving signal according to the potential of the second node K. The voltage stabilizing module 40 is electrically connected to a first power line and a second power line and transmits a voltage on the first power line or a voltage on the second power line to the second node K according to the voltage of the fourth node P. The first driving control module 50 controls the voltage of the fourth node P according to the voltage of the second node K.

The voltage stabilizing module 40 includes a first transistor T4. A gate of the first transistor T4 is configured to receive a clock signal, and an operation mode of the gate driving circuit includes a low power consumption mode. When the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

It can be understood that the gate driving circuit provided in this embodiment is electrically connected to the second node K by arranging the voltage stabilizing module 40. When the gate driving circuit is in the low power consumption mode, the first transistor T4 may be turned on to maintain the potential of the second node K. Therefore, when the clock signal is of low frequency, the potential of the second node K may not decrease due to the influence of leakage, and the potential of the second node K can be kept at a high potential. Therefore, the gate driving circuit provided in this embodiment can reduce the power consumption of the gate driving circuit by reducing the frequency of the clock signal, and no display abnormality may occur. This further solves issues in related technologies that a reduction in clock signal frequency may cause the output of the stage circuit to be abnormal, resulting in display issues on the display panel.

In one embodiment, the first transistor T4 is an N-channel thin film transistor. The clock signal includes a first clock signal (XCK). The gate of the first transistor T4 is configured to receive the first clock signal. When the gate driving circuit is in the low power consumption mode, the voltage of the first clock signal is a first voltage, the first voltage is a high potential, and the first transistor T4 is turned on.

Specifically, the first transistor is a double-gate indium gallium zinc oxide thin film transistor, and the first gate of the first transistor and the second gate of the first transistor are both configured to receive the first clock signal.

What needs to be explained is that, when the first clock signal maintains a high potential state at a low frequency, the gate driving circuit in this embodiment can maintain the potential of the second node K through the first transistor T4 in the voltage stabilizing module 40. Therefore, while reducing the frequency of the clock signal, the gate driving circuit may not output abnormally. Therefore, in this application, the power consumption of the gate driving circuit can be reduced by keeping the clock signal at a high potential at a low frequency.

In one embodiment, the first transistor T4 is a P-channel thin film transistor. When the gate driving circuit is in the low power consumption mode, the voltage of the first clock signal is the first voltage. The first voltage is low potential, and the first transistor T4 is turned on.

What needs to be explained is that, when the first clock signal maintains a low potential state at a low frequency, the gate driving circuit in this embodiment can maintain the potential of the second node K through the first transistor T4 in the voltage stabilizing module 40. Therefore, while reducing the frequency of the clock signal, the gate driving circuit may not output abnormally. Therefore, in this application, the power consumption of the gate driving circuit can be reduced by keeping the clock signal at a high potential at a low frequency.

In one embodiment, the first driving control module 50 is electrically connected to the second node K and the fourth node P, and the first driving control module 50 is configured to control the voltage of the fourth node P according to the voltage of the second node K. An input terminal of the first driving control module 50 is electrically connected to an output terminal of the input module 10, and an output terminal of the first driving control module 50 is electrically connected to the fourth node P.

The voltage stabilizing module 40 is electrically connected to the second node K, a first power line, and a second power line. The voltage stabilizing module 40 is configured to maintain the potential of the second node K to be the potential of the first power line or the potential of the second power line according to the first clock signal and the potential of the fourth node P.

In one embodiment, the first driving control module 50 includes a fifth transistor T3 and a sixth transistor T1. One of a source or a drain of the fifth transistor T3 is electrically connected to the first power line, and another of the source or the drain of the fifth transistor T3 is electrically connected to one of a source or a drain of the sixth transistor T1 and the fourth node P. Another of the source or the drain of the sixth transistor T1 is electrically connected to the third power line. The output terminal of the input module 10 is electrically connected to a gate of the fifth transistor T3, a first gate of the sixth transistor T1, and a second gate of the sixth transistor T1.

It should be noted that the fifth transistor T3 is a P-channel thin film transistor. The sixth transistor T1 is a double-gate N-channel thin film transistor. In this way, a dynamic performance of the fifth transistor T3 and the sixth transistor T1 can be improved, thereby improving the dynamic performance of the first driving control module 50.

The voltage stabilizing module 40 includes a first transistor T4 and a second transistor T5. One of a source or a drain of the first transistor T4 is electrically connected to the output terminal of the input module 10 and the second node K. A gate of the first transistor T4 is electrically connected to the first clock line to receive the first clock signal. Another of the source or the drain of the first transistor T4 is electrically connected to one of a source or a drain of the second transistor T5. Another of the source or the drain of the second transistor T5 is electrically connected to the first power line. A gate of the second transistor T5 is electrically connected to the output terminal of the first driving control module 50 and the fourth node P.

It should be noted that the voltage stabilizing module 40 can maintain the second node K at a high potential according to the potential of the fourth node P and the potential of the first clock line. That is to say, when the fourth node P is at a low potential, the first power line can control the potential of the second node K to the potential of the first power signal PVGH.

In an embodiment, the voltage stabilizing module 40 further includes a third transistor T14. One of the source or the drain of the third transistor T14 is electrically connected to the second power line. Another of the source or the drain of the third transistor T14 is electrically connected to the second node K. A gate of the third transistor T14 is connected to the fourth node P.

It should be noted that the voltage stabilizing module 40 can maintain the potential of the second node K at a low potential according to the potential of the fourth node P. That is to say, when the fourth node P is at a high potential, the second power line can control the potential of the second node K to the potential of the second power signal VGL.

The third transistor T14 is an N-channel thin film transistor. The third transistor T14 is a double-gate thin film transistor. This can not only improve ability to control current flowing through itself, but also reduce a drift amplitude of a threshold voltage.

In an embodiment, the sixth transistor T1, the first transistor T4, and the third transistor T14 may all be indium gallium zinc oxide thin film transistors.

In one embodiment, the gate driving circuit further includes a second driving control module 70. The second driving control module 70 is electrically connected between the second node K and the third node Q. An input terminal of the second driving control module 70 is electrically connected to the output terminal of the input module 10. A control terminal of the second driving control module 70 is electrically connected to the driving control line.

The input terminal of the second output module 30 is electrically connected to the output terminal of the input module 10. The output terminal of the second output module 30 is electrically connected to a Nth stage positive pulse gate driving line. The number of positive pulses output by the Nth stage positive pulse gate driving line in one frame is greater than the number of negative pulses output by the Nth stage negative pulse gate driving line in one frame.

It should be noted that the Nth stage positive pulse gate driving line, that is, the second gate driving line, is used to transmit the Nth stage positive pulse gate driving signal Nout[N], that is, the second gate driving signal. The second gate driving signal can be used as a stage transmission signal of the stage circuit. The Nth stage negative pulse gate driving line, that is, the first gate driving line, is used to transmit the Nth stage negative pulse gate driving signal Pout[N], that is, the first gate driving signal.

What needs to be explained is that, the gate driving circuit provided in this embodiment can not only output a second gate driving signal with a larger number of pulses through the input module 10 and the second output module 30, but also the second gate driving signal can also be selected as a stage transmission signal between different stage circuits. The input module 10, the second driving control module 70, the first driving control module 50, and the first output module 20 can output a first gate driving signal with a smaller number of pulses. This can meet the needs of the corresponding pixel circuit in terms of time and quantity of gate driving signal pulses in one frame, thereby driving the pixel circuit to achieve image quality display.

In one embodiment, the second driving control module 70 includes a transistor T11. One of a source or a drain of the transistor T11 is electrically connected to the output terminal of the input module 10. Another one of the source or the drain of the transistor T11 is electrically connected to the control terminal of the first output module 20. A gate of the transistor T11 is electrically connected to the driving control line. The transistor T11 is a P-channel thin film transistor. The driving control line is configured to transmit the driving control signal RST.

It should be noted that the output terminal of the input module 10 is the second node K. One of the control terminals of the first output module 20 is the third node Q. Another one of the source or the drain of the transistor T11 is the node W. The second driving control module 70 is configured to reduce the double pulse appearing in one frame of the second node K into a single pulse appearing in one frame of the third node Q. Specifically, the first pulse appearing in one frame of the second node K is eliminated, while the second pulse appearing in the same frame is retained.

It should be noted that this embodiment is conducive to ensuring the output stability of the Nth potential negative pulse gate driving signal Pout[N] and avoiding the coupled pull-down phenomenon before the negative pulse arrives.

In one embodiment, the second driving control module 70 further includes a first capacitor C2. One end of the first capacitor C2 is electrically connected to the gate of the transistor T11, and the other end of the first capacitor C2 is electrically connected to the other one of the source or the drain of the transistor T11.

It should be noted that this embodiment is conducive to further improving the output stability of the Nth potential negative pulse gate driving signal Pout[N].

It should be noted that the output terminal of the input module 10 is the second node K. The control terminal of the first output module 20 is the third node Q. The other one of the source or the drain of the transistor T11 is the node W. The second driving control module 70 is configured to reduce the double pulse appearing in one frame of the second node K into a single pulse appearing in one frame of the third node Q. Specifically, the first pulse appearing in one frame of the second node K is eliminated, while the second pulse appearing in the same frame is retained.

In one embodiment, the first output module 20 includes a transistor T6 and a second capacitor C1. A gate of the transistor T6 is electrically connected to one of the source or the drain of the transistor T11. One of the source or the drain of the transistor T6 is electrically connected to a second clock line. The other one of the source or the drain of the transistor T6 is electrically connected to the Nth stage negative pulse gate driving line. One end of the second capacitor C1 is electrically connected to the gate of the transistor T6, and the other end of the second capacitor C1 is electrically connected to the other one of the source or the drain of the transistor T6. An ratio of capacities of the first capacitor C2 and the second capacitor C1 is greater than or equal to 0.5.

It should be noted that in this embodiment, the ratio of the capacities of the first capacitor C2 and the second capacitor C1 is designed to further ensure the output stability of the Nth stage negative pulse gate driving signal Pout[N]. This avoids coupling pull-down behavior before a negative pulse occurs.

Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF. The capacity of the second capacitor C1 may be greater than or equal to 100 fF. In some embodiments, the transistor T6 may be a P-channel thin film transistor.

In one of the embodiments, the first output module 20 includes a transistor T7. One of the source or the drain of the transistor T7 is electrically connected to the first power line. The other one of the source or the drain of the transistor T7 is electrically connected to the Nth stage negative pulse gate driving line. The gate of the transistor T7 is electrically connected to the output terminal of the first driving control module 50, that is, the fourth node P.

It should be noted that the transistor T7 may be a P-channel thin film transistor. Under the joint action of the first output module 20 and the first output module 20, the required Nth stage negative pulse gate driving signal Pout[N] can be modulated.

In one embodiment, the input module 10 includes a transistor T2, a transistor T13, and a transistor T12. One of a source or a drain of the transistor T13 is electrically connected to a third power line. The other one of the source or the drain of the transistor T13 is electrically connected to the input terminal of the input module 10. A first gate of the transistor T13 is electrically connected to a start control line or the N−Yth stage positive pulse gate driving line. The first gate of the transistor T13 is electrically connected to a second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor. One of the source or the drain of the transistor T12 is electrically connected to the first power line. The other one of the source or the drain of the transistor T12 is electrically connected to the other one of the source or the drain of the transistor T13. A gate of the transistor T12 is electrically connected to the first gate of the transistor T13. The transistor T12 is a P-channel thin film transistor. One of the source or the drain of the transistor T2 is electrically connected to the output terminals of the transistors T13 and T12. The other one of the source or the drain of the transistor T2 is electrically connected to the input terminal of the second driving control module 70. The gate of transistor T2 is electrically connected to the first clock line. In some embodiments, the transistor T2 may be a P-channel thin film transistor.

It should be noted that in this embodiment, the input module 10 not only has an objective inversion effect, that is, the input signal and the output signal have opposite potentials at the same time, but also plays the role of making the Nth stage positive pulse gate driving signal Nout[N] serve as a stage transmission signal between stage circuits. Otherwise, stage transmission cannot be achieved between circuits at all stages, resulting in the gate driving circuit being unable to provide the corresponding gate driving signal normally.

In one embodiment, the second output module 30 includes a P-channel transistor T9 and an N-channel transistor T10. The first electrode of the transistor T9 is electrically connected to the fourth power line, and the gate of the transistor T9 is electrically connected to the second node K. The first electrode of the transistor T10 is electrically connected to the second electrode of the transistor T9 to output the second gate driving signal, and the gate of the transistor T10 is electrically connected to the gate of the transistor T9.

In one embodiment, the gate of the transistor T10 includes a first gate and a second gate. The second node K is electrically connected to the first gate of the transistor T10 and the second gate of the transistor T10.

It should be noted that in this embodiment, the transistor T10 may be a double-gate thin film transistor. It can not only improve ability to control the current flowing through itself, but also reduce a drift amplitude of a threshold voltage. The transistor T10 is an indium gallium zinc oxide thin film transistor.

The first power line is configured to transmit a first power signal PVGH. The first power signal PVGH can control the N-channel thin film transistor to turn on or control the P-channel thin film transistor to turn off. The second power line is configured to transmit a second power signal NVGL. The second power signal NVGL can control the P-channel thin film transistor to turn on or the N-channel thin film transistor to turn off. The third power line is configured to transmit the third power signal PVGL, and the fourth power line is configured to transmit the second power signal NVGH.

In one embodiment, the third power signal PVGL is smaller than the second power signal NVGL, so that the third transistor T14 is turned off more completely when it is in the off state.

In one embodiment, the second output module 30 outputs the second gate driving signal according to the potential of the second node K. The number of pulses of the second gate driving signal in one frame is greater than the number of pulses of the first gate driving signal in one frame.

The transistor T9 is a P-channel thin film transistor. The transistor T10 is a double-gate N-channel thin film transistor. In this way, the dynamic performance of the transistor T9 and the transistor T10 can be improved, and thus the dynamic performance of the second output module 30 can be improved.

It should be noted that the Nth stage positive pulse gate driving line is used to transmit the Nth stage positive pulse gate driving signal Nout[N]. The Nth stage negative pulse gate driving line is used to transmit the Nth stage negative pulse gate driving signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The N−Yth stage positive pulse gate driving line is used to transmit the N−Yth stage positive pulse gate driving signal Nout [N−Y]. The N−Xth stage positive pulse gate driving line is used to transmit the N−Xth stage positive pulse gate driving signal Nout [N−X]. The driving control line is used to transmit the driving control signal RST.

In one embodiment, the second driving control module 70 further includes an anti-leakage transistor T8. One of the source or the drain of the anti-leakage transistor T8 is electrically connected to the other of the source or the drain of the transistor T11. The other one of the source or the drain of the anti-leakage transistor T8 is electrically connected to the control terminal of the first output module 20. A gate of the anti-leakage transistor T8 is electrically connected to an anti-leakage signal line to receive an anti-leakage signal.

The anti-leakage signal line may be a positive pulse gate drive line N[n-X]. Specifically, it can be the N−2th stage positive pulse gate driving line, and the anti-leakage signal is the N−2th stage positive pulse gate driving signal N[n−2].

As shown at c in FIG. 5, when the first clock signal XCK signal of the transistor T2 does not start to operate, the second node K is in the floating state. When the second node K randomly reaches a low potential state, the second output module 30 outputs a high potential. This causes a series of cascading reactions, causing the first frame output of all lines to be abnormal.

In order to solve the above issues, in one embodiment, the Nth stage circuit further includes a reset module 60. The reset module 60 controls the voltage of the second node according to the reset signal control. The reset module 60 includes a fourth transistor T15. One of the source or the drain of the fourth transistor T15 is connected to the first power line. The other one of the source or the drain of the fourth transistor T15 is connected to the second node. The gate of the fourth transistor T15 receives the reset signal control.

The reset signal control is only turned on once every time the gate driving circuit is powered on. That is, the fourth transistor T15 is turned on to pull the potential of the second node K to a high potential. At this time, the above-mentioned start signal STV, first clock signal XCK, second clock signal CK, anti-leakage signal N[n−2], and driving control signal RST have not started to transmit signals.

It can be understood that the reset module 60 can ensure that the second node K is at a high level every time the gate drive circuit is powered on, so that the above abnormal output situation will not occur, as shown at d in FIG. 6.

The working process of the above-mentioned stage circuit in one frame can include the following stages as shown in FIG. 7:

The first stage S1: As shown in FIG. 7 and FIG. 8, the start control signal STV, the driving control signal RST, the first clock signal XCK, and the anti-leakage signal N[n−2] are all at low potential. The second clock signal CK is at a high potential. The first node O, the second node K, and the third node Q are all at high potential. The fourth node P is at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential, and the Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The second stage S2: As shown in FIG. 7 and FIG. 9, the start control signal STV, the second clock signal CK, and the anti-leakage signal N[n−2] are all at low potential. The driving control signal RST and the first clock signal XCK are at a high potential. The first node O, the second node K, and the third node Q are all at high potential. The fourth node P is at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The third stage S3: As shown in FIG. 7 and FIG. 10, the start control signal STV, the first clock signal XCK, and the anti-leakage signal N[n−2] are all at low potential. The driving control signal RST and the second clock signal CK are both at a high potential. The first node O, the second node K, and the third node Q are all at high potential. The fourth node P is at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The fourth stage S4: As shown in FIG. 7 and FIG. 11, the driving control signal RST and the start control signal STV are at low potential. The first clock signal XCK, the second clock signal CK, and the anti-leakage signal N[n−2] are all at high potential. The first node O, the second node K, and the third node Q are all at high potential. The fourth node P is at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The fifth stage S5: As shown in FIG. 7 and FIG. 12, the driving control signal RST and the first clock signal XCK are both at low potential. The start control signal STV, the second clock signal CK, and the anti-leakage signal N[n−2] are all at high potential. The third node Q and the fourth node P are both at high potential. The first node O and the second node K are both at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a high potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The sixth stage S6: As shown in FIG. 7 and FIG. 13, the start control signal STV, the first clock signal XCK, the second clock signal CK, and the driving control signal RST are all at a high potential. The anti-leakage signal N[n−2] is at low potential. The third node Q and the fourth node P are both at high potential. The first node O and the second node K are at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a high potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The seventh stage S7: As shown in FIG. 7 and FIG. 14, the start control signal STV, the first clock signal XCK, and the anti-leakage signal N[n−2] are all at low potential. The second clock signal CK and the driving control signal RST are both at a high potential. The fourth node P is both at low potential. The first node O, the second node K, and the third node Q are at high potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The eighth stage S8: As shown in FIG. 7 and FIG. 15, the start control signal STV, the first clock signal XCK, and the anti-leakage signal N[n−2] are all at high potential. The driving control signal RST is at a low potential. The first node O and the fourth node P are at low potential. The third node Q and the second node K are both at high potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The ninth stage S9: As shown in FIG. 7 and FIG. 16, the driving control signal RST and the first clock signal XCK are both at low potential. The start control signal STV, the second clock signal CK, and the anti-leakage signal N[n−2] are at high potential. The first node O and the second node K are at low potential. The fourth node P and the third node Q are both at high potential. The Nth stage positive pulse gate driving signal Nout[N] is at a high potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

The tenth stage S10: As shown in FIG. 7 and FIG. 17, the start control signal STV, the driving control signal RST, the second clock signal CK, and the anti-leakage signal N[n−2] are all at low potential. The first clock signal XCK is at a high potential. The first node O and the fourth node P are at high potential. The third node Q and the second node K are at low potential. The Nth stage positive pulse gate driving signal Nout[N] is at a high potential. The Nth stage negative pulse gate driving signal Pout[N] is at a low potential.

The eleventh stage S11: As shown in FIG. 7 and FIG. 18, the start control signal STV, the driving control signal RST, the first clock signal XCK, and the anti-leakage signal N[n−2] are all at low potential. The second clock signal CK is at a high potential. The fourth node P is at low potential. The first node O, the third node Q, and the second node K are at high potential. The Nth stage positive pulse gate driving signal Nout[N] is at a low potential. The Nth stage negative pulse gate driving signal Pout[N] is at a high potential.

It should be noted that the “crosses” in FIG. 8 to FIG. 18 indicate that the transistors covered by them are in the off state, and the transistors not covered by the “crosses” are in the on state.

It can be seen from FIG. 7 that the Nth stage positive pulse gate driving signal Nout[N] has a first positive pulse and a second positive pulse in one frame. The Nth stage negative pulse gate driving signal Pout[N] has a first negative pulse in one frame.

In one frame, the duration of the second positive pulse is longer than the duration of the first negative pulse, and the duration of the first negative pulse is located within the duration of the second positive pulse.

FIG. 19 is a schematic structural diagram of the cascade connection between different stages of circuits in the gate driving circuit shown in FIG. 3. Arranged from top to bottom are a first-stage circuit 101, a second-stage circuit 102, a third-stage circuit 103, a fourth-stage circuit 104, a fifth-stage circuit 105, a sixth-stage circuit 106 . . . and so on. The first clock line is electrically connected to each stage circuit respectively, and the second clock line is also electrically connected to each stage circuit respectively.

The first-stage circuit 101 respectively outputs the corresponding first-stage negative pulse gate driving signal Pout[1] and the first-stage positive pulse gate driving signal Nout[1] through the first-stage negative pulse gate driving line and the first-stage positive pulse gate driving line.

The second-stage circuit 102 respectively outputs the corresponding second-stage negative pulse gate driving signal Pout[2] and the second-stage positive pulse gate driving signal Nout[2] through the second-stage negative pulse gate driving line and the second-stage positive pulse gate driving line.

The third-stage circuit 103 respectively outputs the corresponding third-stage negative pulse gate driving signal Pout[3] and the third-stage positive pulse gate driving signal Nout[3] through the third-stage negative pulse gate driving line and the third-stage positive pulse gate driving line.

The fourth-stage circuit 104 respectively outputs the corresponding fourth-stage negative pulse gate driving signal Pout[4] and the fourth-stage positive pulse gate driving signal Nout[4] through the fourth-stage negative pulse gate driving line and the fourth-stage positive pulse gate driving line.

The fifth-stage circuit 105 respectively outputs the corresponding fifth-stage negative pulse gate driving signal Pout[5] and the fifth-stage positive pulse gate driving signal Nout[5] through the fifth-stage negative pulse gate driving line and the fifth-stage positive pulse gate driving line.

The sixth-stage circuit 106 respectively outputs the corresponding sixth-stage negative pulse gate driving signal Pout[6] and the sixth-stage positive pulse gate driving signal Nout[6] through the sixth-stage negative pulse gate driving line and the sixth-stage positive pulse gate driving line. Other stage circuits can be deduced in sequence.

The input terminal (IN) of the input module 10 in the first-stage circuit 101 is electrically connected to the start control line to receive the start control signal STV. The input terminals (IN) of the input module 10 in other stage circuits are connected to the positive pulse gate driving signal of the previous stage. For example, the input terminal (IN) of the input module 10 in the second-stage circuit 102 is connected to the first-stage positive pulse gate driving signal Nout[1]. The input terminal (IN) of the input module 10 in the third-stage circuit 103 is connected to the second-stage positive pulse gate driving signal Nout[2]. The input terminal (IN) of the input module 10 in the fourth-stage circuit 104 is connected to the third-stage positive pulse gate driving signal Nout[3]. The input terminal (IN) of the input module 10 in the fifth-stage circuit 105 is connected to the fourth-stage positive pulse gate driving signal Nout[4]. The input terminal (IN) of the input module 10 in the sixth-stage circuit 106 is connected to the fifth-stage positive pulse gate driving signal Nout[5]. Others can be deduced in turn. It is understandable that multiple stage circuits can also be cascaded at other intervals, which is not covered in this application.

The control terminal of the second driving control module 70 (transistor T8) in the fifth-stage circuit 105 is connected to the third-stage positive pulse gate driving signal Nout[3]. The control end of the second driving control module 70 in the sixth-stage circuit 106 is connected to the fourth-stage positive pulse gate driving signal Nout[4], and the others can be deduced in sequence. X can also be 3, 4, 5, 6, 7, etc. Here, X is equal to 2 as an example.

It should be noted that the output terminals of some stage circuits are connected to virtual pixels or are floating. Therefore, each output terminal of the Nth stage circuit is connected to not the Nth row pixel circuit. Instead, the number of rows of connected pixel circuits needs to be determined based on the number of connected dummy pixels or floating stage circuits.

The upper picture in FIG. 20 is a schematic structural diagram of a display panel in traditional technology. Gate driving circuits for providing a light emitting control signal EM, a gate driving signal Nscan1, and a gate driving signal Pscan are respectively arranged on the left side (non-display area or frame area) of the display area (AA area). Gate driving circuits for providing the gate driving signal Pscan, the gate driving signal Nscan2, and the gate driving signal Pscan2 are respectively arranged on the right side (non-display area or frame area) of the display area (AA area).

Each gate driving signal Pscan drives one row of pixel circuits. The operation modes of the gate driving signal Nscan1 and the gate driving signal Nscan2 are also the same as the gate driving signal Pscan respectively. However, one gate driving signal Nscan1/gate driving signal Nscan2 needs to drive two rows of pixel circuits. In actual operation, in order to achieve a narrower frame, the gate driving circuit for outputting the gate driving signal Nscan1 and the gate driving circuit for outputting the gate driving signal Nscan2 are both set to single-sided driving. However, this may cause the driving capabilities of the two gate driving circuits to deteriorate and the power consumption to increase.

In view of this, in this embodiment, the gate driving circuit shown in FIG. 3 is configured as a bilateral drive as shown in the lower diagram of FIG. 20. That is, a gate driving circuit as shown in FIG. 3 is provided on both sides of the AA area. Corresponding gate driving signals are simultaneously input from both ends of each gate driving line. This not only improves the driving capability of the Nth stage negative pulse gate driving signal Pout[N] and the positive pulse gate driving signal Nout, but also reduces power consumption. It also reduces the space occupied by the frame, which is conducive to the development of narrower frame solutions.

The positive pulse gate driving signal Nout includes the Nth stage positive pulse gate driving signal Nout[N] and the N−Lth stage positive pulse gate driving signal Nout[N−L]. L may be an integer greater than or equal to 1, for example, it may be 2, 3, 4, 5, 6 . . . , etc.

In one embodiment, this embodiment provides a display panel. The display panel includes the gate driving circuit and the pixel circuit in at least one of the above embodiments. One row of pixel circuits is electrically connected to the Nth stage positive pulse gate driving line and the Nth stage negative pulse gate driving line.

It can be understood that the display panel provided by this embodiment includes the gate driving circuit in at least one of the above embodiments. It can also be electrically connected to the second node K through the voltage stabilizing module 40. The voltage stabilizing module 40 controls the potential of the fourth node P according to the potential of the second node K, and maintains the potential of the second node K. Therefore, when the clock signal is of low frequency, the potential of the second node K may not decrease due to the influence of leakage. The potential of the second node K can be maintained. Therefore, the gate driving circuit provided in this embodiment can reduce the power consumption of the gate driving circuit by reducing the frequency of the clock signal, and no display abnormality may occur. This further solves the issues in related technologies that lowering the frequency of the clock signal may cause the output of the stage circuit to be abnormal, resulting in display issues on the display panel.

FIG. 21 is a schematic structural diagram of the pixel circuit in the display panel shown in FIG. 20. It can be understood that the gate driving circuit shown in FIG. 3 can provide the corresponding Nth stage positive pulse gate driving signal Nout[N], N−Lth stage positive pulse gate driving signal Nout[N−L], and Nth stage negative pulse gate driving signal Pout[N].

The pixel circuit shown in FIG. 21 may include at least one of a writing transistor T2P, a driving transistor TIP, a first light emitting control transistor T5P, a second light emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor Cboost.

The first power line is electrically connected to the first electrode of the first light emitting control transistor T5P and one end of the storage capacitor Cst. The second electrode of the first light emitting control transistor T5P is electrically connected to the first electrode of the driving transistor TIP and the first electrode of the writing transistor T2P. The second electrode of the driving transistor TIP is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light emitting control transistor T6P. The second electrode of the second light emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and an anode of the light emitting device D1. A cathode of the light emitting device D1 is electrically connected to the second power line. The light emitting control line is electrically connected to the gate of the first light emitting control transistor T5P and the gate of the second light emitting control transistor T6P. The second electrode of the writing transistor T2P is electrically connected to the data line. The gate of the writing transistor T2P is electrically connected to the Nth stage negative pulse gate driving line (first gate driving line) and one end of the bootstrap capacitor Cboost. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line. The gate of the second initialization transistor T7P is electrically connected to the third gate driving line. The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor TIP. The gate of the compensation transistor T3P is electrically connected to the Nth stage positive pulse gate driving line (second gate driving line). The gate of the driving transistor TIP is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost and the first electrode of the first initialization transistor T4P. The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line. The gate of the first initialization transistor T4P is electrically connected to the N−Lth stage positive pulse gate driving line (second gate driving line). The first electrode of the third initialization transistor T8P is electrically connected to the first electrode of the driving transistor TIP. The second electrode of the third initialization transistor T8P is electrically connected to the third initialization line. The gate of the third initialization transistor T8P and the gate of the second initialization transistor T7P share the third gate driving line.

It should be noted that the second initialization line can also be replaced by the first initialization line. This can reduce one trace required for the pixel circuit and help increase the density of the pixel circuit in the display panel.

The first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain. For example, when the first electrode is the source, the second electrode is the drain. Or, when the first electrode is the drain, the second electrode is the source.

The first power line is used to transmit the positive power signal VDD. The second power line is used to transmit the negative power signal VSS. The potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit the data signal Data. The light emitting control line is used to transmit the light emitting control signal EM. The first initialization line is used to transmit the first initialization signal Vil. The second initialization line is used to transmit a second initialization signal. The third initialization line is used to transmit the third initialization signal Vi3. The first gate driving line is used to transmit the Nth stage negative pulse gate driving signal Pout[N]. The Nth stage positive pulse gate driving line (second gate driving line) is used to transmit the Nth stage positive pulse gate driving signal Nout[N]. The N−L-th stage positive pulse gate driving line (second gate driving line) is used to transmit the N−L-th stage positive pulse gate driving signal Nout[N−L]. The third gate driving line is used to transmit the gate driving signal Pscan2.

The operation timing of the pixel circuit shown in FIG. 21 in one frame is shown in FIG. 22. Under the common driving of Nth stage negative pulse gate driving signal Pout[N], the gate driving signal Pscan2, the N−Lth stage positive pulse gate driving signal Nout[N−L], the Nth stage positive pulse gate driving signal Nout[N], and the light emitting control signal EM, the pixel circuit shown in FIG. 21 can perform normal display.

The Nth stage negative pulse gate driving signal Pout[N], the N−Lth stage positive pulse gate driving signal Nout[N−L], and the Nth stage positive pulse gate driving signal Nout[N] can be provided by the gate driving circuit shown in FIG. 3.

For those skilled in the art, there may be changes in the specific implementation and application scope based on the ideas of this application. In summary, the contents of this specification should not be construed as limiting this application.

Claims

1. A gate driving circuit comprising a plurality of cascaded stage circuits, wherein each stage circuit comprises: an input subcircuit configured to receive a start signal or a stage transmission signal output by other stage circuits and configured to control a voltage of a second node;a first output subcircuit configured to output a first gate driving signal according to a potential of a third node and a potential of a fourth node;a second output subcircuit configured to output a second gate driving signal according to a potential of the second node;a voltage stabilizing subcircuit electrically connected to a first power line and a second power line and configured to transmit a voltage on the first power line or a voltage on the second power line to the second node according to a voltage of the fourth node;a first driving control subcircuit configured to control the voltage of the fourth node according to the voltage of the second node;wherein the voltage stabilizing subcircuit comprises a first transistor, a gate of the first transistor is configured to receive a clock signal, and an operation mode of the gate driving circuit comprises a low power consumption mode, when the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

2. The gate driving circuit according to claim 1, wherein the first transistor is an N-channel thin film transistor, and the first voltage is a high potential.

3. The gate driving circuit according to claim 2, wherein the first transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both configured to receive the clock signal.

4. The gate driving circuit according to claim 2, wherein the voltage stabilizing subcircuit further comprises a second transistor, a gate of the second transistor is electrically connected to the fourth node, one of a source and a drain of the second transistor is electrically connected to the first power line, the other one of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor, the other one of the source and the drain of the first transistor is electrically connected to the second node; wherein the first transistor and the second transistor have different channel types.

5. The gate driving circuit according to claim 4, wherein when the gate driving circuit is in the low power consumption mode, the voltage of the fourth node turns on the second transistor to transmit the voltage on the first power line to one of the source and the drain of the first transistor.

6. The gate driving circuit according to claim 2, wherein the first driving control subcircuit is electrically connected to the second node and the fourth node, and the first driving control subcircuit outputs a voltage inverted with a voltage of the second node to the fourth node.

7. The gate driving circuit according to claim 6, wherein the first driving control subcircuit comprises a fifth transistor and a sixth transistor, one of a source and a drain of the fifth transistor is electrically connected to the first power line, the other one of the source and the drain of the fifth transistor is electrically connected to the fourth node, one of a source and a drain of the sixth transistor is electrically connected to a third power line, the other one of the source and the drain of the sixth transistor is electrically connected to the fourth node, and a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the second node; wherein the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

8. The gate driving circuit according to claim 7, wherein the sixth transistor is a double-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node.

9. The gate driving circuit according to claim 8, wherein when the gate driving circuit is in a low power consumption mode, the sixth transistor is turned on and outputs a voltage on the third power line to the fourth node.

10. The gate driving circuit according to claim 1, wherein the voltage stabilizing subcircuit further comprises a third transistor, one of a source and a drain of the third transistor is electrically connected to the second power line, and the other one of the source and the drain of the third transistor is electrically connected to the second node, and a gate of the third transistor is connected to the fourth node.

11. The gate driving circuit according to claim 10, wherein when the gate driving circuit is in a low power consumption mode, a voltage of the fourth node turns off the third transistor.

12. The gate driving circuit according to claim 11, wherein the third transistor is a dual-gate indium gallium zinc oxide thin film transistor, and a first gate of the third transistor and a second gate of the third transistor are both electrically connected to the fourth node.

13. The gate driving circuit according to claim 1, wherein each stage circuit further comprises a reset subcircuit, and the reset subcircuit controls a voltage of the second node according to a reset signal.

14. The gate driving circuit according to claim 13, wherein the reset subcircuit comprises a fourth transistor, one of a source and a drain of the fourth transistor is connected to the first power line, the other one of the source and the drain of the fourth transistor is electrically connected to the second node, and a gate of the fourth transistor receives the reset signal.

15. The gate driving circuit according to claim 14, wherein in a first frame of operation of the gate driving circuit, the reset signal controls the fourth transistor to turn on before a pulse of the start signal arrives, such that a voltage on the first power line is transmitted to the second node.

16. The gate driving circuit according to claim 1, wherein each stage circuit further comprises: a second driving control subcircuit, wherein the second driving control subcircuit is electrically connected between the second node and the third node, a control terminal of the second driving control subcircuit is electrically connected to a driving control line, and the second driving control subcircuit is configured to control a conduction between the second node and the third node.

17. The gate driving circuit according to claim 16, wherein the second driving control subcircuit is configured to eliminate a first pulse of the second node appearing in one frame and retain a second pulse of the second node appearing in the same frame.

18. The gate driving circuit according to claim 16, wherein the second driving control subcircuit comprises a transistor, one of a source and a drain of the transistor is electrically connected to an output terminal of the input subcircuit, another the other one of the source and the drain of the transistor is electrically connected to a control terminal of the first output subcircuit, and a gate of the transistor is electrically connected to the driving control line; wherein the transistor is a P-channel thin film transistor; the driving control line is configured to transmit driving control signals.

19. The gate driving circuit according to claim 18, wherein the second driving control subcircuit comprises a first capacitor, one end of the first capacitor is electrically connected to the gate of the transistor, and the other end of the first capacitor is electrically connected to the other one of the source and the drain of the transistor.

20. A display panel, wherein the display panel comprises: a pixel circuit, wherein the pixel circuit comprises a writing transistor configured to control input of a data signal and a compensation transistor configured to control input of the data signal to a gate of a driving transistor; anda gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded stage circuits, and each stage circuit comprises:an input subcircuit configured to receive a start signal or a stage transmission signal output by other stage circuits and configured to control a voltage of a second node;a first output subcircuit configured to output a first gate driving signal according to a potential of a third node and a potential of a fourth node;a second output subcircuit configured to output a second gate driving signal according to a potential of the second node;a voltage stabilizing subcircuit electrically connected to a first power line and a second power line and configured to transmit a voltage on the first power line or a voltage on the second power line to the second node according to a voltage of the fourth node;a first driving control subcircuit configured to control the voltage of the fourth node according to the voltage of the second node;wherein the voltage stabilizing subcircuit comprises a first transistor, a gate of the first transistor is configured to receive a clock signal, and an operation mode of the gate driving circuit comprises a low power consumption mode, when the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor;wherein an output terminal of the first output subcircuit is electrically connected to a gate of the writing transistor, and an output terminal of the second output subcircuit is electrically connected to a gate of the compensation transistor.