Patent Grant
10923063
The present application claims priority to Chinese Patent Application No. 201811132950.4 and filed Sep. 27, 2018, the entire contents of which are incorporated herein by reference.
The present disclosure relates to the field of display technology, and more particularly to a gate driving circuit and a driving method, an array substrate and a display device.
At present, the most commonly used liquid crystal display is a Thin Film Transistor (TFT) liquid crystal display. The TFT liquid crystal display uses a source driver to supply a driving voltage corresponding to a screen to be displayed to a data line to drive a display panel to display the image.
In the related art, a display stage of the liquid crystal display generally includes a heavy-load screen stage and a normal screen stage. In the heavy-load screen stage, the refresh rate of the liquid crystal display is high, and thus the load of the source driver is large, causing the temperature of the source driver to be excessively high.
It should be noted that the information disclosed in the Background section above is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
According to an aspect of the present disclosure, a gate driving circuit is provided. The gate driving circuit includes 4n stages of shift register units, and n stages of inversion units. One of the inversion units is disposed between every two groups of four adjacent stages of shift register units. A (n+1)th stage of the inversion units is disposed between two of the shift register units, and configured to, in response to a control signal, output in inverted phases gate driving signals outputted by the two shift register units in a heavy-load screen stage, and output in positive phases gate driving signals outputted by the two shift register units in a normal screen stage. The two of the shift register units are the (4n+1)th stage of the shift register units and the (4n+2)th stage of the shift register units, the (4n+2)th stage of the shift register units and the (4n+3)th stage of the shift register units, the (4n+3)th stage of the shift register units and the (4n+4)th stage of the shift register units, or the (4n+1)th stage of the shift register units and the (4n+4)th stage of the shift register units. n is greater than or equal to 0.
In an exemplary arrangement of the present disclosure, every four adjacent stages of the shift register units are provided with two of the inversion units. Each of the inversion units is disposed between every two of the shift register units.
In an exemplary arrangement of the present disclosure, the inversion unit is disposed between every adjacent two of the shift register units. The (n+1)th stage of the inversion unit is configured to, in response to a control signal, output in inverted phases or positive phases the gate driving signals outputted by the (2n+1)th stage of the shift register units and the (2n+2)th stage of the shift register units.
In an exemplary arrangement of the present disclosure, the inversion unit includes a positive-phase output circuit, an inverted-phase output circuit and a signal input circuit. The positive-phase output circuit is connected to an output end of the (2n+1)th stage of shift register unit, an output end of the (2n+2)th stage of shift register unit, a gate-driving-signal input end of the (2n+1)th row of pixel units, and a gate driving signal input end of the (2n+2)th row of pixel units. The positive-phase output circuit is configured to, in response to the control signal, transmit a gate driving signal outputted from the output end of the (2n+1)th stage of shift register unit to the gate-driving-signal input end of the (2n+1)th row of pixel units, and transmit a gate driving signal outputted from the output end of the (2n+2)th stage of shift register unit to the gate-driving-signal input end of the (2n+2)th row of pixel units. The inverted-phase output circuit is connected to an output end of the (2n+1)th stage of shift register unit, an output end of the (2n+2)th stage of shift register unit, a gate-driving-signal input end of the (2n+1)th row of pixel units, and a gate driving signal input end of the (2n+2)th row of pixel units, and configured to, in response to a signal of a first node, transmit a gate driving signal outputted from the output end of the (2n+1)th stage of shift register unit to the gate-driving-signal input end of the (2n+2)th row of pixel units, and transmit a gate driving signal outputted from the output end of the (2n+2)th stage of shift register unit to the gate-driving-signal input end of the (2n+1)th row of pixel units. The signal input circuit is connected to a first signal end and a second signal end, and configured to transmit the signal of the first signal end to the first node, in response to the signal of the first signal end, and transmit a signal of the second signal end to the first node in response to the control signal.
In an exemplary arrangement of the present disclosure, the normal phase output circuit includes a first transistor and a second transistor. The first transistor has a first end connected to the output end of the (2n+1)th stage of shift register unit, a second end connected to the gate-driving-signal input end of the (2n+1)th row of pixel units and a control end for receiving the control signal; and the second transistor has a first end connected to the output end of the (2n+2)th stage of shift register unit, a second end connected to the gate-driving-signal input end of the (2n+2)th row of pixel units and a control end for receiving the control signal.
In an exemplary arrangement of the present disclosure, the inverted-phase output circuit includes a third transistor and a fourth transistor. The third transistor has a first end connected to the output end of the (2n+2)th stage of shift register unit, a second end connected to the gate-driving-signal input end of the (2n+1)th row of pixel units, and a control end for receiving a signal from the first node. The fourth transistor has a first end connected to the output end of the (2n+1)th stage of shift register unit, a second end connected to the gate-driving-signal input end of the (2n+2)th row of pixel units, and a control end for receiving a signal from the first node.
In an exemplary arrangement of the present disclosure, the signal input circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a first end connected to the first signal end, a control end connected to the first signal end, and a second end forming the first node. A sixth transistor has a first end connected to the first node, a second end connected to the second signal end, and a control end for receiving the control signal.
In an exemplary arrangement of the present disclosure, when the gate driving signal outputted from the shift register unit has no pre-charge time period, a plurality of the inversion units shares the same control signal.
In an exemplary arrangement of the present disclosure, the gate driving circuit is a 2M clock signal driving circuit, the gate driving signal outputted from the shift register unit has a pre-charge time period, and the N-th stage of inversion unit and the (N+M)th stage of inversion unit share the same control signal, where N and M each is greater than or equal to 1.
According to an aspect of the present disclosure, a driving method of a gate driving circuit is provided. The method includes, in a heavy-load screen stage, outputting gate driving signals outputted by two shift register units in inverted phases. The method includes in a normal screen stage, outputting gate driving signals outputted by the two shift register units in positive phases. The two of the shift register units are the (4n+1)th stage of the shift register units and the (4n+2)th stage of the shift register units, the (4n+2)th stage of the shift register units and the (4n+3)th stage of the shift register units, the (4n+3)th stage of the shift register units and the (4n+4)th stage of the shift register units, or the (4n+1)th stage of the shift register units and the (4n+4)th stage of the shift register units. n is greater than or equal to 0. In a normal screen stage, a pulse time period of a source driving signal is equal to a pulse time period of a gate driving signal.
In a heavy-load screen phase, the source driving signal has a pulse time period twice of that in the normal screen stage.
According to an aspect of the present disclosure, there is provided an array substrate including the gate driving circuit described above.
According to an aspect of the present disclosure, there is provided a display device including the array substrate described above.
The present exemplary arrangement provides a gate driving circuit and a driving method, an array substrate and a display device. One inversion unit is disposed between every two groups of four adjacent stages of shift register units in the gate driving circuit, and the inversion unit is configured to output in inverted phases, gate driving signals outputted by the two shift register units in a reloaded screen stage, and output in positive phases, gate driving signals outputted by the two shift register units in a normal screen stage.
It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate arrangements consistent with the disclosure and, together with the description, serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some of the arrangements of the present disclosure, and other drawings may be obtained from these drawings by those skilled in the art without paying creative effort.
Exemplary arrangements will now be described more fully with reference to the accompanying drawings. However, the exemplary arrangements can be embodied in a variety of forms and should not be construed as being limited to the examples set forth herein. Rather, these arrangements are provided to make the present disclosure more comprehensive and complete, and to fully convey the concept of the exemplary arrangements to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed description thereof will be omitted.
Although the relative terms such as “on” and “under” are used in the specification to describe the relative relationship of one component to another component as illustrated, these terms are used in this specification for convenience only, for example, according to the direction of the example illustrated in the accompanying drawings. It will be understood that if the device as illustrated is flipped upside down, the component described as “on” will become the component “under”. Other relative terms, such as “high”, “low”, “top”, “bottom”, “left”, “right”, etc., also have similar meanings. When a structure is “on” another structure, it may mean that a structure is integrally formed on another structure, or that a structure is “directly” disposed on another structure, or that a structure is “indirectly” disposed on another structure via other structures.
The terms “a”, “an”, and “the” are used to mean the presence of one or more elements/components, etc. The terms “including” and “having” are used to have a non-exclusive meaning of including, and mean that other elements/components/etc. may be present in addition to the listed elements/components/etc.
The present exemplary arrangement first provides a gate driving circuit including 4n stages of shift register units and n stages of inversion units. One of the inversion units is disposed between every two groups of four adjacent stages of shift register units. A (n+1)th stage of the inversion units is disposed between two of the shift register units, and configured to, in response to a control signal, output in inverted phases gate driving signals outputted by the two shift register units in a heavy-load screen stage, and output in positive phases gate driving signals outputted by the two shift register units in a normal screen stage. The two of the shift register units are respectively the (4n+1)th stage of the shift register units and the (4n+2)th stage of the shift register units, or the (4n+2)th stage of the shift register units and the (4n+3)th stage of the shift register units, or the (4n+3)th stage of the shift register units and the (4n+4)th stage of the shift register units, or the (4n+1)th stage of the shift register units and the (4n+4)th stage of the shift register units, where n is greater than or equal to 0.
The gate driving circuit provided by the exemplary arrangement is suitable for a display method, in which a frequency of polarity change of the source driving signal can be reduced to one-half of the original frequency in a heavy-load screen stage, while can ensure proper display of pixels by outputting in an inverted phase a gate driving signal outputted by a shift register unit. As shown in
The present exemplary arrangement provides a gate driving circuit. One inversion unit is disposed between every two groups of four adjacent stages of shift register units in the gate driving circuit, and the inversion unit is configured to output in inverted phases, gate driving signals outputted by the two shift register units in a heavy-load screen stage, and output in positive phases, gate driving signals outputted by the two shift register units in a normal screen stage. On the one hand, in the present disclosure, by outputting in an inverted phase the gate driving signals outputted by the two shift register units in the heavy-load screen stage, it can realize reduction of load of the source driver by reducing the change frequency of the source driving signal. On the other hand, in the present disclosure, it can realize switching between outputting in an inverted phase and outputting in a positive phase through an inversion unit, and realize switching between a heavy-load screen and a normal screen.
In the exemplary arrangement, one inversion unit is provided for every four adjacent stages of shift register units, and the inversion unit is disposed between two shift register units of the four shift register units, and the remaining two shift register units are directly connected to corresponding pixel units. Such arrangement makes the signals outputted by the shift registers connected to the inversion unit have different output path from that of the signals outputted by the shift registers not connected to the inversion unit. In this way, the strengths of the gate driving signals may be changed, and the timing sequence may be disordered. In the exemplary arrangement, the gate driving circuit may include 2n stages of inversion units; every four adjacent stages of shift register units are provided with two of the inversion units. The inversion unit is disposed between two of the shift register units. In every four adjacent shift register units, one inversion unit is disposed between two shift register units according to the above connection manner, and the other inversion unit is disposed between the other two shift register units. Such arrangement can make the gate driving signals outputted by each stage of the shift register units to have the same output path.
In the exemplary arrangement, the inversion unit may be formed on an array substrate by a patterning process. The inversion unit is disposed between the first stage of shift register unit and the fourth stage of shift register unit in the same group, which may improve the difficulty of the patterning process. In the exemplary arrangement, the inversion unit is preferably disposed between every adjacent two of the shift register units; the (n+1)th stage of inversion unit is configured to, in response to a control signal, output, in inverted phases or positive phases, the gate driving signals outputted by the (2n+1)th stage of the shift register units and the (2n+2)th stage of the shift register units, where n is greater than 0. That is, an inversion unit is disposed between the (4n+1)th stage of shift register and the (4n+2)th stage of shift register, and an inversion unit is disposed between the (4n+3)th stage of shift register and the (4n+4)th stage of shift register.
In an exemplary arrangement, as shown in
In the present exemplary arrangement, as shown in
In an exemplary arrangement, the first inverted-phase output sub-circuit 21 may include a fourth transistor T4, and the second inverted-phase output sub-circuit 22 may include a third transistor T3. The third transistor T3 has a first end connected to the output end output-E of the (2n+2)th stage of shift register unit, a second end connected to the gate-driving-signal input end input-O of the (2n+1)th row of pixel units, and a control end for receiving a signal from the first node N. The fourth transistor T4 has a first end connected to the output end output-O of the (2n+1)th stage of shift register unit, a second end connected to the gate-driving-signal input end input-E of the (2n+2)th row of pixel units, and a control end for receiving a signal from the first node N. When the signal of the first node N is at a high level, the third transistor T3 and the fourth transistor T4 are turned on; the gate driving signal outputted from the output end output-O of the (2n+1)th stage of shift register unit is transmitted to the gate-driving-signal input end input-E of the (2n+2)th row of pixel units; and the gate driving signal outputted from the output end output-E of the (2n+2)th stage of shift register unit is transmitted to the gate-driving-signal input end input-O of the (2n+1)th row of pixel units.
In the present exemplary arrangement, the signal input circuit 3 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 has a first end connected to the first signal end VDD, a control end connected to the first signal end, and a second end forming the first node. The sixth transistor T6 has a first end connected to the first node, a second end connected to the second signal end VSS, and a control end for receiving the control signal. When the control signal is at a high level, the first transistor T1 and the second transistor T2 are turned on. At the same time, the sixth transistor T6 is turned on, and the signal VSS of the second signal terminal is transmitted to the first node N. The third transistor T3 and the fourth transistors T4 are turned off. At this time, the first transistor T1 and the second transistor T2 are turned on; the signal outputted from the output end output-O of the (2n+1)th stage of shift register unit is transmitted to the gate-driving-signal input end input-O of the (2n+1)th row of pixel units through the first transistor T1; and the signal outputted from the output end output-E of the (2n+2)th stage of shift register unit is transmitted to the gate-driving-signal input end input-E of the (2n+2)th row of pixel units through the second transistor T2. When the control signal is at a low level, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, the fifth transistor is turned on under the action of VDD, and the signal of the first signal end VDD is transmitted to the first node N. The third transistors T3 and the fourth transistor T4 are turned on; the signal outputted by the output end output-O of the (2n+1)th stage of shift register unit is transmitted to the gate-driving-signal input end input-E of the (2n+2)th row of pixel units through the fourth transistor T4; and the signal outputted by the output end output-E of the (2n+2)th stage of shift register unit is transmitted to the gate-driving-signal input end input-O of the (2n+1)th row of pixel units through the fourth transistor T3.
In an exemplary arrangement, a plurality of the inversion units may share the same control signal. As shown in
In the present exemplary arrangement, as shown in
An exemplary arrangement further provides a driving method of the gate driving circuit, as shown in
In block S1, in a heavy-load screen stage, gate driving signals outputted by the two shift register units are outputted in inverted phases.
In block S2, in a normal screen stage, gate driving signals outputted by the two shift register units are outputted in positive phases.
The two shift register units are the (4n+1)th stage of shift register unit and the (4n+2)th stage of shift register unit, or the (4n+2)th stage of shift register unit and the (4n+3)th stage of shift register unit, or the (4n+3)th stage of shift register unit and the (4n+4)th stage of shift register unit, or the (4n+1)th stage of shift register unit and (4n+4)th stage of shift register unit, where n is greater than or equal to 0.
The driving method of the gate driving circuit provided by the exemplary arrangement has the same technical features and working principles as the above-described gate driving circuit, details of which will not be repeated herein.
An exemplary arrangement also provides an array substrate including the gate driving circuit described above.
The array substrate provided by the exemplary arrangement has the same technical features and working principles as the above-mentioned gate driving circuit, details of which will not be repeated herein.
The present exemplary arrangement also provides a display device including the above array substrate.
The display device provided by the exemplary arrangement has the same technical features and working principles as the above array substrate, details of which will not be repeated herein. Other arrangements of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed here. This application is intended to cover any variations, uses, or adaptations of the disclosure following the general principles thereof and including such departures from the present disclosure as come within known or customary practice in the art. It is intended that the specification and arrangements be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
The features, structures, or characteristics described above may be combined in any suitable manner in one or more arrangements, and the features discussed in the various arrangements are interchangeable, if possible. In the above description, numerous specific details are set forth to provide a thorough understanding of the arrangements of the present disclosure. However, one skilled in the art will appreciate that the technical solution of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, and the like may be employed. In other instances, well-known structures, materials or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201811132950.4 | Sep 2018 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20060001638 | Jeon | Jan 2006 | A1 |
| 20090278782 | Chen | Nov 2009 | A1 |
| 20100194716 | Park | Aug 2010 | A1 |
| 20110007040 | John | Jan 2011 | A1 |
| 20150310815 | Deng | Oct 2015 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20200105217 A1 | Apr 2020 | US |
