Patent Application
20250166541
This application claims priority to Chinese Patent Application No. 202311549993.3 filed Nov. 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to the field of display technology and, in particular, to a gate driving circuit and a driving method thereof, and a display device.
With the development of display technology, customers have increasingly high requirements for display panels. Existing gate driving circuits can no longer meet the design of display panels. Therefore, a better gate driving circuit is urgently needed.
The present invention provides a gate driving circuit and a driving method thereof, and a display device to reduce the power consumption of the gate driving circuit.
In a first aspect, embodiments of the present invention provide a gate driving circuit. The gate driving circuit includes an input module and a storage module.
The input module is connected to each of a first node and a signal input terminal of the gate driving circuit and configured to control a potential of the first node according to a potential of the signal input terminal.
An input terminal of the storage module is connected to the first node. The storage module is configured to store the potential of the first node and control a potential of an output terminal of the storage module according to the potential of the first node.
Optionally, the gate driving circuit further includes an output module connected between the output terminal of the storage module and a signal output terminal of the gate driving circuit and configured to control a potential of the signal output terminal of the gate driving circuit according to the potential of the output terminal of the storage module.
Preferably, the input module is configured to transmit a potential hop of the signal input terminal to the first node in a delayed manner.
Preferably, the storage module is configured to invert the potential of the first node and then outputs the inverted potential of the first node to the output terminal of the storage module.
Preferably, the output module is configured to invert the potential of the output terminal of the storage module and then outputs the inverted potential of the output terminal of the storage module to the signal output terminal of the gate driving circuit.
Optionally, the storage module includes a first inversion unit and a second inversion unit.
A control terminal of the first inversion unit is connected to the first node. A first input terminal of the first inversion unit is connected to a first power terminal. A second input terminal of the first inversion unit is connected to a second power terminal. An output terminal of the first inversion unit is connected to the output terminal of the storage module.
A control terminal of the second inversion unit is connected to the output terminal of the storage module. A first input terminal of the second inversion unit is connected to the first power terminal. A second input terminal of the second inversion unit is connected to the second power terminal. An output terminal of the second inversion unit is connected to the first node.
Preferably, the first inversion unit includes a first transistor and a second transistor. A gate of the first transistor and a gate of the second transistor are each connected to the first node. A first electrode of the first transistor is connected to the first power terminal. A first electrode of the second transistor is connected to the second power terminal. A second electrode of the first transistor and a second electrode of the second transistor are each connected to the output terminal of the first inversion unit.
The second inversion unit includes a third transistor and a fourth transistor. Agate of the third transistor and a gate of the fourth transistor are each connected to the output terminal of the storage module. A first electrode of the third transistor is connected to the first power terminal. A first electrode of the fourth transistor is connected to the second power terminal. A second electrode of the third transistor and a second electrode of the fourth transistor are each connected to the output terminal of the second inversion unit.
A channel type of the first transistor is opposite to a channel type of the second transistor. A channel type of the third transistor is opposite to a channel type of the fourth transistor. The channel type of the first transistor is the same as the channel type of the third transistor.
Preferably, the second transistor and the fourth transistor are each an n-type transistor.
Preferably, the second transistor and the fourth transistor each include a second gate. The second gate of the second transistor and the second gate of the fourth transistor are each connected to a third power terminal.
Optionally, the gate driving circuit further includes a transmission control module connected between the first node and the output terminal of the second inversion unit and configured to control whether the first node communicates with the output terminal of the second inversion unit.
Preferably, the transmission control module includes a fifth transistor connected between the first node and the output terminal of the second inversion unit. A gate of the fifth transistor is connected to a second clock terminal.
Preferably, the transmission control module includes a sixth transistor connected between the first node and the output terminal of the second inversion unit. A gate of the sixth transistor is connected to a first clock terminal.
A signal connected to the first clock terminal and a signal connected to the second clock terminal are mutually inverse signals. A channel type of the fifth transistor is opposite to a channel type of the sixth transistor.
Preferably, the sixth transistor is an n-type transistor.
Preferably, the sixth transistor includes a second gate. The second gate of the sixth transistor is connected to the third power terminal.
Optionally, the input module further includes an eighth transistor connected between the signal input terminal and the first node. A gate of the eighth transistor is connected to a second clock terminal.
Preferably, the input module further includes an eighth transistor connected between the signal input terminal and the first node. A gate of the eighth transistor is connected to a second clock terminal.
A signal connected to the first clock terminal and a signal connected to the second clock terminal are mutually inverse signals. A channel type of the seventh transistor is opposite to a channel type of the eighth transistor.
Preferably, the eighth transistor is an n-type transistor.
Preferably, the eighth transistor includes a second gate. The second gate of the eighth transistor is connected to the third power terminal.
Optionally, the output module includes a ninth transistor and a tenth transistor. A gate of the ninth transistor and a gate of the tenth transistor are each connected to the output terminal of the storage module. A first electrode of the ninth transistor is connected to a first power terminal. A first electrode of the tenth transistor is connected to a second power terminal. A second electrode of the ninth transistor and a second electrode of the tenth transistor are each connected to the signal output terminal of the gate driving circuit.
A channel type of the ninth transistor is opposite to a channel type of the tenth transistor.
Preferably, the tenth transistor is an n-type transistor.
Preferably, the tenth transistor includes a second gate. The second gate of the tenth transistor is connected to a third power terminal.
Optionally, a potential connected to the first power terminal is higher than a potential connected to the second power terminal. A potential connected to the third power terminal is lower than or equal to the potential connected to the second power terminal.
In a second aspect, embodiments of the present invention further provide a driving method of a gate driving circuit for driving the gate driving circuit provided in any embodiment of the present invention. The driving method includes the following.
In a first working mode, the input module is controlled to be turned on, where the input module transmits a potential of the signal input terminal to a first node, and the storage module controls a potential of the output terminal of the storage module according to a potential of the first node.
In a second working mode, the input module is controlled to be turned off, where the storage module stores the potential acquired by the first node before the input module is turned off, and the storage module controls the potential of the output terminal of the storage module according to the potential of the first node.
Optionally, the driving method of a gate driving circuit includes the following.
At a first stage, an input signal connected to the signal input terminal hops from a first potential to a second potential to control the gate driving circuit to perform the second working mode in which the input module is turned off, the first node maintains the first potential, and the storage module inverts the first potential into the second potential and then outputs the second potential.
At a second stage, the input signal maintains the second potential to control the gate driving circuit to perform the first working mode and the second working mode alternately, where in the first working mode, the input module is turned on and transmits the second potential of the input signal to the first node, and the storage module inverts the second potential into the first potential and then outputs the first potential; and in the second working mode, the input module is turned off, the first node maintains the second potential, and the storage module inverts the second potential into the first potential and then outputs the first potential.
At a third stage, the input signal hops from the second potential to the first potential to control the gate driving circuit to perform the second working mode in which the input module is turned off, the first node maintains the second potential, and the storage module inverts the second potential into the first potential and then outputs the first potential.
At a fourth stage, the input signal maintains the first potential to control the gate driving circuit to perform the first working mode and the second working mode alternately, where in the first working mode, the input module is turned on and transmits the first potential of the input signal to the first node, and the storage module inverts the first potential into the second potential and then outputs the second potential; and in the second working mode, the input module is turned off, the first node maintains the first potential, and the storage module inverts the first potential into the second potential and then outputs the second potential.
Optionally, the gate driving circuit includes an output module. In the first working mode and the second working mode, the output module inverts the potential of the output terminal of the storage module and then outputs the inverted potential of the output terminal of the storage module to a signal output terminal of the gate driving circuit.
Moreover/alternatively, the gate driving circuit includes a transmission control module configured to control whether a control terminal of a first inversion unit in the storage module communicates with an output terminal of a second inversion unit in the storage module; in the first working mode, the transmission control module is controlled to be turned off; and in the second working mode, the transmission control module is controlled to be turned on.
In a third aspect, embodiments of the present invention further provide a display device. The display device includes the gate driving circuit provided in any embodiment of the present invention.
The display device includes an input signal line and multi-level gate driving circuits connected in a cascade manner. A signal input terminal of a first-level gate driving circuit among the multi-level gate driving circuits is connected to the input signal line. A signal output terminal of a current-level gate driving circuit among the multi-level gate driving circuits is connected to a signal input terminal of a next-level gate driving circuit among the multi-level gate driving circuits.
Optionally, the gate driving circuit further includes a first clock terminal and a second clock terminal.
The display device further includes a first clock signal line and a second clock signal line. The first clock signal line is connected to a first clock terminal of the odd-level gate driving circuit and a second clock terminal of the even-level gate driving circuit. The second clock signal line is connected to a second clock terminal of the odd-level gate driving circuit and a first clock terminal of the even-level gate driving circuit.
Preferably, in a refresh frame, a signal transmitted by the first clock signal line and a signal transmitted by the second clock signal line are each a pulse signal.
Preferably, in a retention frame, a signal transmitted by the first clock signal line and a signal transmitted by the second clock signal line are each a direct current signal.
Preferably, on the same occasion, a signal transmitted by the first clock signal line and a signal transmitted by the second clock signal line are mutually inverse signals.
Preferably, a high-potential duty cycle of signals transmitted by the first clock signal line and a high-potential duty cycle of signals transmitted by the second clock signal line are each 50%.
Optionally, the display device further includes a driver chip.
The driver chip is connected to each of the first clock signal line and the second clock signal line.
Alternatively, the display device further includes an inverter. The driver chip is connected to an input terminal of the inverter and the first clock signal line. An output terminal of the inverter is connected to the second clock signal line.
The input module and the storage module are disposed in the gate driving circuit provided in embodiments of the present invention. The input module may be controlled to be turned on to adjust the potential of the first node based on the potential of the signal input terminal. The write information is supplied to the input terminal of the storage module so that the storage module adjusts the potential of the output terminal of the storage module according to the potential of the first node. The input module may be controlled to be turned off to disconnect the signal input terminal from the first node so that the storage module is in the latch state, thereby implementing the potential maintaining of the output terminal of the storage module. The structure of the gate driving circuit is simple and easy to implement, helping reduce the power consumption of the circuit. Moreover, the gate driving circuit uses the storage module to store signals. The storage module has the function of constantly maintaining the stored in the state of powering on. Therefore, the working state of the input module and the working state of the storage module in the retention frame do not need to be adjusted periodically as those in a refresh frame, thus effectively reducing the static power consumption of the circuit.
It is to be understood that the content described in this section is neither intended to identify key or critical features of embodiments of the present invention nor intended to limit the scope of the present invention. Other features of the present invention become easily understood through the description hereinafter.
To illustrate solutions of embodiments of the present invention more clearly, the drawings used in the description of the embodiments are briefly described hereinafter. Apparently, the drawings described hereinafter illustrate part of the embodiments of the present invention, and those of ordinary skill in the art may obtain other drawings based on the drawings described hereinafter on the premise that no creative work is done.
To make solutions of the present invention better understood by those skilled in the art, solutions of embodiments of the present invention are described hereinafter clearly and completely in conjunction with drawings in embodiments of the present invention. Apparently, the embodiments described hereinafter are part, not all, of embodiments of the present invention. Based on embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art are within the scope of the present invention on the premise that no creative work is done.
It is to be noted that terms “first”, “second”, and the like in the description, claims, and drawings of the present invention are used for distinguishing between similar objects and are not necessarily used for describing a particular order or sequence. It is to be understood that data used in this manner are interchangeable in appropriate cases so that embodiments of the present invention described herein can be implemented in an order not illustrated or described herein. In addition, terms “comprising”, “including” and any other variations thereof are intended to encompass a non-exclusive inclusion.
As mentioned in BACKGROUND, an existing gate driving circuit has a relatively high power consumption. The reason for this problem is exemplified hereinafter. In the related art, a gate driving circuit generally includes multiple transistors and multiple capacitors. As shown in
To solve the preceding problem, an embodiment of the present invention provides a gate driving circuit.
Exemplarily, the input module 10 may be composed of transistors or other controllable switch elements. The input module 10 may control the communication state between the input terminal 11 and the output terminal 12. When the input module 10 is turned on, the input terminal 11 communicates with the output terminal 12, and the input signal may be transmitted to the first node N1. When the input module 10 is turned off, the input terminal 11 is disconnected from the output terminal 12, and the input signal cannot be transmitted to the first node N1. The adjustment of the on-off time of the input module 10 may implement the adjustment of the corresponding relationship between the input signal and the potential of the first node N1. Exemplarily, the on-off state switching occasion of the input module 10 is controlled to be later than the occasion of the potential hopping of the input signal so that a potential hop (or pulse) of the input signal is transmitted to the first node N1 in a delayed manner.
Exemplarily, the storage module may be composed of two cross-coupled inverters. When the input module 10 is turned on, it is equivalent to supplying write information to the input terminal 22 of the storage module 20 so that the storage module 20 adjusts the potential of the output terminal 22 according to the potential of the first node N1, for example, inverts the potential of the first node N1 and outputs the inverted potential of the first node N1 to the output terminal 22 of the storage module 20. When the input module 10 is turned off, the storage module 20 is in the latch state so that the output terminal 22 can maintain the potential before the input module 10 is turned off until the input module 10 is turned on again. As long as the storage module 20 keeps powering on, data stored in the storage module 100 can be constantly maintained. During the driving process of the gate driving circuit 100, especially in a retention frame, the data at the input terminal 21 of the storage module 20 does not need to be refreshed periodically. The working state of the input module 10 and the working state of the storage module 20 do not need to be adjusted frequently, thus effectively reducing power consumption.
The input module 10 and the storage module 20 are disposed in the gate driving circuit 100 provided in this embodiment of the present invention. The input module 10 may be controlled to be turned on to adjust the potential of the first node N1 based on the potential of the signal input terminal IN. The write information is supplied to the input terminal 21 of the storage module 20 so that the storage module 20 adjusts the potential of the output terminal 22 according to the potential of the first node N1. The input module 10 may be controlled to be turned off to disconnect the signal input terminal IN from the first node N1 so that the storage module 20 is in the latch state, thereby implementing the potential maintaining of the output terminal 22 of the storage module 20. The structure of the gate driving circuit 100 is simple and easy to implement, helping reduce the power consumption of the circuit. Moreover, the gate driving circuit 100 uses the storage module 20 to store signals. The storage module 20 has the function of constantly maintaining the stored in the state of powering on. Therefore, the working state of the input module 10 and the working state of the storage module 20 in the retention frame do not need to be adjusted periodically as those in a refresh frame, thus effectively reducing the static power consumption of the circuit.
In the preceding embodiments, functions of various modules in the gate driving circuit 100 are exemplified. Specific structures that the gate driving circuit 100 may have are described hereinafter.
In this embodiment, the input module 10 is configured as the transmission gate structure, effectively improving the reliability of the gate driving circuit 100. Specifically, a p-type transistor has a threshold voltage loss when the low potential is transmitted so that a high potential can pass without loss and a low potential passes with loss. On the contrary, an n-type transistor has a threshold voltage loss when a high potential is transmitted so that only a low potential can pass without loss. The transmission gate is composed of two transistors with opposite channel types, and gates of the two transistors are connected to two mutually inverse signals respectively, guaranteeing that the on-off states of the two transistors are consistent. In this case, when the input module 10 is turned on, the seventh transistor T7 and the eighth transistor T8 are turned on simultaneously so that a low potential and a high potential can pass without loss, effectively guaranteeing the potential transmission capability of the input module 10 and extending the range of potentials that the input module 10 can transmit. Therefore, such an arrangement guarantees that when the input module 10 is turned on, the potential of the first node N1 is consistent with the potential of the input signal, avoiding an output anomaly caused by a threshold voltage loss.
The channel type of the first transistor T1 is opposite to the channel type of the second transistor T2. The channel type of the third transistor T3 is opposite to the channel type of the fourth transistor T4. The channel type of the first transistor T1 is the same as the channel type of the third transistor T3. In
The structure in
In this embodiment, the storage module 20 is composed of four transistors so that the storage module 20 has a simple structure, requires a small number of elements, and occupies a small layout space, helping reduce circuit cost and implement a narrow bezel.
At a first stage T01, although the input signal GIN hops high, the first clock signal GCK hops high and the second clock signal GCKB hops low. The seventh transistor T7 and the eighth transistor T8 are each turned off. The high potential of the input signal GIN cannot be transmitted to the first node N1. The potential VN1 of the first node N1 is maintained at the low potential of the previous stage. In this case, the fifth transistor T5 and the sixth transistor T6 are each turned on. The first node N1 communicates with the output terminal 24 of the second inversion unit. The storage module 20 is connected as a standard structure of two cross-coupled inverters. The potential V22 of the output terminal 22 of the storage module 20 is a high potential. The tenth transistor T10 and the ninth transistor T9 are controlled to be turned on and off respectively so that the output module 30 inverts the potential V22 of the output terminal 22 of the storage module 20. The gate driving signal GOUT has a low potential.
At a second stage T02, at the beginning of this stage, the first clock signal GCK hops low, and the second clock signal GCKB hops high. The seventh transistor T7 and the eighth transistor T8 are each turned on. The high potential of the input signal GIN is transmitted to the first node N1 so that the potential VN1 of the first node N1 is set high. Inverted by the first inversion unit, the potential V22 of the output terminal 22 of the storage module 20 is set low. The ninth transistor T9 and the tenth transistor T10 are controlled to be turned on and off respectively so that the gate driving signal GOUT hops to a high potential. After the first clock signal GCK hops high (and the second clock signal GCKB hops low), although the seventh transistor T7 and the eighth transistor T8 are each turned off and the input signal GIN is no longer transmitted, the fifth transistor T5 and the sixth transistor T6 are each turned on. In this case, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 constitute a structure of two cross-coupled inverters and are in the latch state so that the potential VN1 of the first node N1 and the potential V22 of the output terminal 22 of the storage module 20 are maintained. Therefore, the gate driving signal GOUT maintains the high potential at the second stage T02.
At a third stage T03, although the input signal GIN hops low, the first clock signal GCK hops high and the second clock signal GCKB hops low. The seventh transistor T7 and the eighth transistor T8 are each turned off. The low potential of the input signal GIN cannot be transmitted to the first node N1. The potential VN1 of the first node N1 is maintained at the high potential of the previous stage. Correspondingly, the potential V22 of the output terminal 22 of the storage module 20 is maintained at the historical state of the previous stage and is a low potential. Therefore, the gate driving signal GOUT still has the high potential.
At a fourth stage T04, at the beginning of this stage, the first clock signal GCK hops low, and the second clock signal GCKB hops high. The seventh transistor T7 and the eighth transistor T8 are each turned on. The low potential of the input signal GIN is transmitted to the first node N1 so that the potential VN1 of the first node N1 is set high. Inverted by the first inversion unit, the potential V22 of the output terminal 22 of the storage module 20 is set high. Inverted by the output module 30, the gate driving signal GOUT hops to a low potential. After the first clock signal GCK hops high, although the seventh transistor T7 and the eighth transistor T8 are each turned off and the input signal GIN is no longer transmitted, the fifth transistor T5 and the sixth transistor T6 are each turned on. In this case, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 constitute a structure of two cross-coupled inverters and are in the latch state so that the potential VN1 of the first node N1 and the potential V22 of the output terminal 22 of the storage module 20 are maintained. Therefore, the gate driving signal GOUT maintains the low potential at the fourth stage T04.
The driving process of the gate driving circuit 100 may be repeated in a cycle from the first stage T01 to the fourth stage T04. For example, a stage before the first stage T01 in
This embodiment exemplifies the driving process of the gate driving circuit 100. The gate driving circuit 100 can effectively eliminate the step phenomenon during the potential hopping process of the gate driving signal GOUT. Specifically, it can be seen from
To verify the reliability of the gate driving circuit 100, an inventor carried out a test according to the circuit structure shown in
Based on the preceding embodiments, optionally, a functional transistor in a pixel circuit which the gate driving circuit 100 specifically acts on may be set according to actual requirements. For example, the gate driving circuit 100 shown in
Based on the preceding embodiments, optionally, the period and low-potential width of each clock signal may be set according to actual requirements. Exemplarily, the period of a clock signal may be set to two pieces of row time. A low-potential width is one piece of row time. The high-potential duty cycle is 50%. Alternatively, if the output terminal 22 of the storage module 22 needs to be used for supplying a gate control signal to a p-type data write transistor, the low-potential pulse width of the output terminal 22 of the storage module 22 needs to be within one piece of row time. Correspondingly, the period of a clock signal may be set to be less than or equal to one piece of row time.
It is to be noted that the driving process from the first stage T01 to the fourth stage T04 in
In a low-frequency display scenario, at least one retention frame is inserted between two adjacent refresh frames. In a retention frame, the gate driving signal GOUT can maintain an off potential of a controlled transistor. The gate driving signal GOUT is presented as a direct current signal without potential hopping in the retention frame.
Alternatively, in another embodiment, optionally, in the retention frame, the first clock signal GCK and the second clock signal GCKB are each presented as a direct current signal without potential hopping to reduce circuit power consumption. Specifically, the circuit structure in
It is to be noted that in the preceding embodiments, the first electrode of each transistor may be referred to as a source or a drain, and the second electrode of each transistor may be referred to as a drain or a source. Since the structure of each transistor is symmetrical, the source and the drain here are not differentiated from each other.
Above all, embodiments of the present invention provide a gate driving circuit based on a complementary thin-film transistor, eliminating the threshold voltage loss caused by low-level transmission and thus eliminating a falling-edge step. Moreover, the circuit requires a small number of elements, narrowing the bezel of the display panel. Besides, embodiments of the present invention use the storage module to store signals. In a low refresh condition, a clock signal does not need to hop continuously, having an obvious advantage in saving low-frequency power consumption.
An embodiment of the present invention further provides a driving method of a gate driving circuit for driving the gate driving circuit provided in any embodiment of the present invention. The method has corresponding beneficial effects.
In S110, in a first working mode, an input module is controlled to be turned on. The input module transmits the potential of a signal input terminal to a first node. A storage module controls the potential of an output terminal of the storage module according to the potential of the first node.
In S120, in a second working mode, the input module is controlled to be turned off. The storage module stores the potential acquired by the first node before the input module is turned off. Moreover, the storage module controls the potential of the output terminal of the storage module according to the potential of the first node.
In the driving process of the gate driving circuit, the gate driving circuit may be controlled to execute the first working mode and the second working mode alternately according to actual requirements. Based on the first working mode, an input signal connected to the signal input terminal may be transmitted to the storage module so that the output of the storage module is synchronously controlled by the input signal. Based on the second working mode, the transmission of the input signal to the storage module may be disconnected so that the storage module maintains the output state before the input module is turned off. Exemplarily, the switching timing of the first working mode and the second working mode is adjusted to adjust the on-off time of the input module, thereby adjusting the correspondence relationship between the input signal and the potential of the first node and thus controlling whether the output signal of the storage module changes synchronously with the input signal. Exemplarily, the switching occasion of switching from the second working mode to the first working mode is controlled to be later than the occasion of the potential hopping of the input signal so that a potential hop (or pulse) of the input signal is transmitted to the first node N1 in a delayed manner, thereby implementing the shift output of the input signal.
In S210, at a first stage, the input signal connected to the signal input terminal hops from a first potential to a second potential to control the gate driving circuit to perform the second working mode.
The first potential and the second potential are different potentials. For example, the first potential is a low potential, and the second potential is a high potential. At this stage, the input module is turned off. The first node maintains the first potential. The storage module inverts the first potential into the second potential and then outputs the second potential. For the driving process at this stage, reference may be made to the specific explanation of the first stage T01 in
In S220, at a second stage, the input signal maintains the second potential to control the gate driving circuit to perform the first working mode and the second working mode alternately.
At this stage, in the first working mode, the input module is turned on and transmits the second potential of the input signal to the first node, and the storage module inverts the second potential into the first potential and then outputs the first potential. In the second working mode, the input module is turned off, the first node maintains the second potential, and the storage module inverts the second potential into the first potential and then outputs the first potential. For the driving process at this stage, reference may be made to the specific explanation of the second stage T02 in
In S230, at a third stage, the input signal hops from the second potential to the first potential to control the gate driving circuit to perform the second working mode.
At this stage, the input module is turned off. The first node maintains the second potential. The storage module inverts the second potential into the first potential and then outputs the first potential. For the driving process at this stage, reference may be made to the specific explanation of the third stage T03 in
In S240, at a fourth stage, the input signal maintains the first potential to control the gate driving circuit to perform the first working mode and the second working mode alternately.
At this stage, in the first working mode, the input module is turned on and transmits the first potential of the input signal to the first node, and the storage module inverts the first potential into the second potential and then outputs the second potential. In the second working mode, the input module is turned off, the first node maintains the first potential, and the storage module inverts the first potential into the second potential and then outputs the second potential. For the driving process at this stage, reference may be made to the specific explanation of the fourth stage T04 in
Based on the preceding embodiments, optionally, for an output module in the gate driving circuit, in the first working mode and the second working mode, the output module inverts the potential of the output terminal of the storage module and then outputs the inverted potential of the output terminal of the storage module to a signal output terminal. That is, in the entire driving process, the output module performs inversion on the signal output by the storage module; and/or, for a transmission control module in the gate driving circuit, in the first working mode, the transmission control module is controlled to be turned off, and in the second working mode, the transmission control module is controlled to be turned on. That is, in the entire driving process, the on state of the transmission control module is always opposite to the on state of the input module.
An embodiment of the present invention further provides a display panel. The display panel includes the gate driving circuit provided in any embodiment of the present invention and has corresponding beneficial effects. Exemplarily, the display device may be, for example, a display screen, a mobile phone, a watch, or a notebook.
Based on the preceding embodiments, optionally, the display device further includes a first power signal line (not shown) and a second power signal line (not shown) that are configured to transmit a first power signal and a second power signal respectively. First power terminals of the multi-level gate driving circuits 100 are each connected to the first power signal line. Second power terminals of the multi-level gate driving circuits 100 are each connected to the second power signal line.
With continued reference to
Based on the preceding embodiments, optionally, the first clock signal line LCK1 and the second clock signal line LCK2 are provided with multiple signal supply manners, several of which are described hereinafter but do not serve as a limitation of the present invention.
Referring to
In another embodiment, optionally, the display device further includes an inverter, for example, disposed in the non-display region NAA. One clock signal output terminal of the driver chip 2000 is connected to one clock signal line and an input terminal of the inverter. An output terminal of the inverter is connected to the other clock signal line. For example, the driver chip 2000 is connected to the input terminal of the inverter and the first clock signal line LCK1. The output terminal of the inverter is connected to the second clock signal line LCK2. Such an arrangement can reduce the requirements of the display panel 1000 for an external input signal and reduce the requirements for the number of output channels of the driver chip 2000. Only one clock signal output terminal may be provided in the driver chip 2000 for the gate driving circuit 100, and another clock signal is generated through the inverter.
For the structure of the inverter, refer to
It is to be noted that the structure and driving method of the gate driving circuit have been explained in detail in the preceding embodiments. For the content not explained in detail in this embodiment, reference may be made to explanations in the preceding embodiments and is not repeated here.
It is to be understood that various forms of processes shown above may be adopted with steps reordered, added or deleted. For example, the steps described in the present invention may be performed in parallel, sequentially or in different sequences, as long as the desired results of the technical solutions of the present invention can be achieved, and no limitation is imposed herein.
The preceding embodiments do not limit the scope of the present invention. It is to be understood by those skilled in the art that various modifications, combinations, sub-combinations, and substitutions may be performed according to design requirements and other factors. Any modification, equivalent substitution, improvement or the like made within the spirit and principle of the present invention is within the scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311549993.3 | Nov 2023 | CN | national |
