Patent Grant
10032427
The present application is the U.S. national phase entry of PCT/CN2015/085567 with an International filing date of Jul. 30, 2015, which claims the benefit of Chinese Application No. 201510142728.2, filed Mar. 27, 2015, the entire disclosures of which are incorporated herein by reference.
The present invention relates to the field of display technology, and more particularly to a gate driving method of a pixel transistor and a gate drive circuit, as well as a display device including the gate drive circuit.
In liquid crystal display devices, a pixel circuit is arranged for each pixel so as to display the corresponding pixel. Each pixel circuit is provided therein with a pixel transistor and a pixel capacitor. A liquid crystal display device is provided therein with a gate drive circuit for gate driving of the pixel transistors in the pixel circuits, i.e., for controlling the ON/OFF of the pixel transistors. When a pixel transistor is turned on, a data voltage will charge the respective pixel capacitor through the pixel transistor. The charged pixel capacitor can control the output of corresponding optical signals.
Generally speaking, the gate drive circuit is provided with a plurality of output ports with each output port being connected with a gate driving line of a pixel row, and the gate driving line being connected with the gates of the pixel transistors of all the pixel circuits in the pixel row. The gate drive circuit outputs a drive voltage to a connected gate driving line through some output port, so as to control the turn-on and turn-off of the pixel transistors of all the pixel circuits in the corresponding pixel row. When the drive voltage is a high level transistor turn-on voltage VGH, the pixel transistor is turned on, and when the drive voltage is a low level transistor turn-off voltage VGL, the pixel transistor is turned off.
In designing the present invention, the inventor finds that the prior art has at least the following defects:
There exists a resistor and a parasitic capacitor on the gate driving line of each pixel row, which will give rise to delay of the drive voltage transmission. Thus, the turn-on of the pixel transistors far away from the gate drive circuit will be greatly delayed, such that the corresponding pixel capacitor cannot be sufficiently charged, thereby leading to inaccurate display of pixels.
In order to solve or alleviate at least one of the defects or issues in the prior art, the embodiments of the present invention provide a gate driving method of a pixel transistor and a gate drive circuit, as well as a display device including the gate drive circuit.
According to one aspect of the present invention, the gate driving method of the pixel transistor is provided, the method comprising the steps of:
a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to a transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage; and
the gate drive circuit outputting a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time.
Optionally, the first voltage is less than the transistor turn-on voltage.
Optionally, the step of a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to a transistor turn-on time of the pixel row comprises:
the gate drive circuit outputting a preset first voltage to the gate driving line of the pixel row from a preset time period prior to the transistor turn-on time of the pixel row.
Optionally, the preset time period is less than the time difference between the transistor turn-off time of the pixel row and the transistor turn-on time of the pixel row.
Optionally, the method further comprises: the gate drive circuit stopping outputting the transistor turn-on voltage to the gate driving line of the pixel row, but outputting the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
Optionally, the step of a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to the transistor turn-on time of the pixel row comprises:
the gate drive circuit outputting the preset first voltage to the gate driving line of the pixel row under the control of a first control signal, prior to the transistor turn-on time of the pixel row.
Optionally, the step of the gate drive circuit outputting a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time comprises:
the gate drive circuit, under the control of a second control signal, stopping outputting the first voltage to the gate driving line, but outputting the transistor turn-on voltage to the gate driving line, when it reaches the transistor turn-on time.
Optionally, the method further comprises: the gate drive circuit, under the control of the second control signal, stopping outputting the transistor turn-on voltage to the gate driving line, but outputting the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
According to another aspect of the present invention, a gate drive circuit is provided, which comprises:
a precharge module configured to output a preset first voltage to a gate driving line of a pixel row prior to the transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage;
a control module configured to output a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time.
Optionally, the first voltage is less than the transistor turn-on voltage.
Optionally, the precharge module is configured to:
output a preset first voltage to the gate driving line of the pixel row from a preset time period prior to the transistor turn-on time of the pixel row.
Optionally, the preset time period is less than the time difference between the transistor turn-off time of the pixel row and the transistor turn-on time of the pixel row.
Optionally, the control module is also configured to:
stop outputting the transistor turn-on voltage to the gate driving line, but output the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
Optionally, the precharge module is configured to:
output the preset first voltage to the gate driving line of the pixel row under the control of a first control signal, prior to the transistor turn-on time of the pixel row.
Optionally, the control module is configured to:
under the control of a second control signal, stop outputting the first voltage to the gate driving line, but output the transistor turn-on voltage to the gate driving line, when it reaches the transistor turn-on time.
Optionally, the control module is also configured to:
under the control of the second control signal, stop outputting the transistor turn-on voltage to the gate driving line, but output the a transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
According to a further aspect of the present invention, a display device is provided, which comprises any gate drive circuit as stated above.
The technical solutions provided by the embodiments of the present invention can achieve at least one of the following advantageous effects and/or other advantageous effects:
the parasitic capacitor on the gate driving line is charged prior to the transistor turn-on time, such that when the gate drive circuit outputs the transistor turn-on voltage to the gate driving line at the transistor turn-on time, it is possible to reduce the delay in transmitting the transistor turn-on voltage, increase the time for charging the pixel capacitor, and improve the accuracy of pixel display.
To explain the technical solutions in the embodiments of the present invention more clearly, the drawings necessary for describing the embodiments will be briefly introduced. It should be realized that the following drawings are only related to some embodiments of the present invention. Those skilled in the art can obtain other drawings according to these drawings without making an inventive labour.
To make clearer the object, technical solutions and advantages of the present invention, the embodiments of the present invention will be further described in detail with reference to drawings.
A gate driving method of a pixel transistor is provided according to an embodiment of the present invention. As shown in
step 101: a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to the transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage; and
step 102: the gate drive circuit outputting a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time. In a specific implementation, when it reaches the transistor turn-on time of the pixel row, the gate drive circuit stops outputting the first voltage to the gate driving line, but outputs a transistor turn-on voltage to the gate driving line.
It needs to be pointed out that the above method is applicable for any pixel row of the display device. Nevertheless, those skilled in the art can realize that the above method can drive each pixel row of the display device on a row-by-row basis.
By means of the above method, the parasitic capacitor on the gate driving line can be charged prior to the transistor turn-on time. In this way, when the gate drive circuit outputs the transistor turn-on voltage to the gate driving line at the transistor turn-on time, it is possible to reduce the delay in transmitting the transistor turn-on voltage, increase the time for charging the pixel capacitor, and improve the accuracy of pixel display.
A gate driving method of a pixel transistor is provided according to an embodiment of the present invention. The subject that implements the method can be the gate drive circuit in the display device. The gate drive circuit can control the turn-on and turn-off of pixel transistors in a plurality of pixel rows. The gate drive circuit can comprise a plurality of output ports with each output port being respectively connected with a gate driving line of a pixel row.
The processing flow as shown in
step 101: a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to the transistor turn-on time of the pixel row.
Wherein, the gate driving line is the line that connects the output port of the gate drive circuit with the gate of the pixel transistor of each pixel circuit in the corresponding pixel row. An equivalent parasitic capacitor of the gate driving line can be as shown in
In a specific implementation, the transistor turn-on time and the transistor turn-off time can be set for each pixel row. The time period therebetween is the turn-on time period of a corresponding transistor, i.e. the time period during which the data voltage of each pixel in the corresponding pixel row charges the pixel capacitor. The time periods to which the pixel rows each correspond are arranged in a time sequence, i.e., the transistor turn-off time of the first pixel row is followed by the transistor turn-on time of the second pixel row, and the transistor turn-off time of the second pixel row is followed by the transistor turn-on time of the third pixel row, and so on and so forth. As to any pixel row, at any time prior to the transistor turn-on time thereof, the gate drive circuit can output the precharge voltage VGM to the gate driving line of the pixel row through a corresponding output port. Before the output of VGM, what is output by the gate drive circuit to the gate driving line is the transistor turn-off voltage VGL. Since VGM is greater than VGL, VGM starts to charge the parasitic capacitor on the gate driving line when VGM is being output.
The ways to output VGM by the gate drive circuit are of great variety. The gate drive circuit can be added with two channels of input signals, wherein one channel is to input VGM constant signals, and the other is to input corresponding enable signals for triggering the gate drive circuit to output VGM outside, which will be elaborated later. Or it is also possible to not add input signals, but to adjust the original input signals of the transistor turn-on voltage in the gate drive circuit from VGH constant signals to signals that alternate between VGM level and VGH level (the time when VGM jumps to VGH is the transistor turn-on time), and advance the time for inputting the enable signals of the transistor turn-on voltage by a certain time period.
Optionally, the voltage range of the first voltage can be further limited so as to make the first voltage less than the transistor turn-on voltage.
In a specific implementation, the value of VGH ranges from 25V to 35V, that of VGL ranges from −4V to −8V, and the value of VGM can be correspondingly arranged between VGH and VGL, such as 3V. When the gate drive circuit inputs VGM into the gates of the pixel transistors of a pixel row through the gate driving line of the pixel row, the data voltage passing through the pixel transistors is the one of the previous pixel row because it is not the transistor turn-on time of the pixel row. Because the value of VGM is set between VGH and VGL, the pixel transistors of the pixel row at this time enter into a slightly-ON state, such that the pixel capacitor is charged less charges, which may reduce the influence of the data voltage of the previous pixel row on the present pixel row.
Optionally, a reasonable time period for inputting can be set for the first voltage. Correspondingly, the process of the step 101 can be made as follows: the gate drive circuit outputting a preset first voltage to a gate driving line of the pixel row from a preset time period prior to the transistor turn-on time of the pixel row.
Further optionally, the preset time period can be set to be less than the time difference between the transistor turn-off time of the pixel row and the transistor turn-on time of the pixel row, namely less than the turn-on duration of the transistor.
In a specific implementation, a relatively small time period can be selected as the preset time period according to actual demands. For instance, the preset time period can be 10% of the time difference between the transistor turn-off time and the transistor turn-on time, namely 10% of the turn-on duration of the transistor. When the gate drive circuit inputs VGM into the gates of the pixel transistors of the pixel row through the gate driving line of the pixel row, the data voltage passing through the pixel transistors is the one of the previous pixel row because it is not the transistor turn-on time of the pixel row. Since the preset time period is set to be relatively short, the pixel capacitor is charged less charges, which may reduce the influence of the data voltage of the previous pixel row on the present pixel row.
In step 102, the gate drive circuit outputs a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time. In a specific implementation, when it reaches the transistor turn-on time of the pixel row, the gate drive circuit stops outputting the first voltage to the gate driving line, but outputs a transistor turn-on voltage to the gate driving line.
In a specific implementation, when it reaches the transistor turn-on time, the output voltage can jump from VGM to VGH, and at this time, the data voltage changes from the data voltage of the previous pixel row to the data voltage of the pixel row. The pixel transistors of the pixel row enter into a turn-on state, and the current data voltage charges the pixel capacitors of the pixel row.
Optionally, the pixel transistors can be turned off subsequently. Correspondingly, the following step can be made after the step 102: the gate drive circuit stops outputting the transistor turn-on voltage to the gate driving line of the pixel row, but outputs the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
In a specific implementation, when it reaches the transistor turn-off time, the output voltage can jump from VGH to VGL, and at this time, the input of the data voltage of the pixel row comes to an end. The pixel transistors of the pixel row enter into a turn-off state and the charging of the pixel capacitors ceases. Then, each pixel capacitor of the pixel row outputs the voltage and the corresponding pixel content is displayed.
As stated above, in order to achieve the processing of the flow, the gate drive circuit can be added with two channels of input signals, wherein one channel is to input VGM constant signal, and the other is to input corresponding enable signals for triggering the gate drive circuit to output VGM outside. Correspondingly, the step 101 can has a process as follows: prior to the transistor turn-on time of a pixel row, the gate drive circuit outputs the preset first voltage to the gate driving line of the pixel row under the control of a first control signal. Correspondingly, the step 102 can has a process as follows: the gate drive circuit, under the control of a second control signal, stops outputting the first voltage to the gate driving line, but outputs a transistor turn-on voltage to the gate driving line, when it reaches the transistor turn-on time. In addition, the process after the step 102 can be as follows: the gate drive circuit, under the control of the second control signal, stops outputting the transistor turn-on voltage to the gate driving line of the pixel row, but outputs the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
In a specific implementation, the input and output signals of the gate drive circuit is shown in
In the above embodiment, the parasitic capacitor on the gate driving line is charged prior to the transistor turn-on time, such that when the gate drive circuit outputs the transistor turn-on voltage to the gate driving line at the transistor turn-on time, it is possible to reduce the delay in transmitting the transistor turn-on voltage, increase the time for charging the pixel capacitor, and improve the accuracy of pixel display.
A gate drive circuit is provided according to another embodiment of the present invention. The gate drive circuit and the gate driving method of the pixel transistor in the above embodiment are based on the same technical concept, so reference can be made to the contents of the above method as for the operation manners of the modules in the gate drive circuit. As shown in
a precharge module 710 configured to output a preset first voltage to a gate driving line of a pixel row prior to the transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage;
a control module 720 configured to output a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time. In a specific implementation, when it reaches the transistor turn-on time, the control module 720 stops outputting the first voltage to the gate driving line of the pixel row, but outputs a transistor turn-on voltage to the gate driving line.
Optionally, the first voltage is less than the transistor turn-on voltage.
Optionally, the precharge module 710 is configured to:
output a preset first voltage to the gate driving line of the pixel row from a preset time period prior to the transistor turn-on time of the pixel row.
Optionally, the preset time period is less than the time difference between the transistor turn-off time of the pixel row and the transistor turn-on time of the pixel row.
Optionally, the control module 720 is also configured to:
stop outputting the transistor turn-on voltage to the gate driving line of the pixel row, but output the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
Optionally, the precharge module 710 is configured to:
output the preset first voltage to the gate driving line of the pixel row under the control of a first control signal, prior to the transistor turn-on time of the pixel row.
Optionally, the control module 720 is configured to:
under the control of a second control signal, stop outputting the first voltage to the gate driving line of the pixel row, but output the transistor turn-on voltage to the gate driving line, when it reaches the transistor turn-on time.
Optionally, the control module 710 is also configured to:
under the control of the second control signal, stop outputting the transistor turn-on voltage to the gate driving line of the pixel row, but output the transistor turn-off voltage to the gate driving line, when it reaches the transistor turn-off time of the pixel row.
A display device is provided according to a further embodiment of the present invention. The display device comprises any gate drive circuit as stated above for gate driving of the pixel rows of the display device. The gate drive circuit and corresponding gate driving method have been elaborated above and will not be reiterated herein.
It needs to be explained that the above embodiments are illustrated based on the above division of the various functional modules. In actual application, the above functions can be achieved by different functional modules as required. The internal structure of the device can be divided into different functional modules to wholly or partially achieve the functions as stated above. Moreover, the function of one module can be realized by a plurality of modules, and the functions of the plurality of modules can also be integrated into one module.
In the above embodiments of the present invention, the parasitic capacitor on the gate driving line is charged prior to the transistor turn-on time, such that when the gate drive circuit outputs the transistor turn-on voltage to the gate driving line at the transistor turn-on time, it is possible to reduce the delay in transmitting the transistor turn-on voltage, increase the time for charging the pixel capacitor, and improve the accuracy of pixel display.
It is appreciated that the above embodiments are only exemplary for the sake of explaining the principle of the present invention, and the present invention should not be limited thereto. As far as those skilled in the art are concerned, various variations and modifications can be made without departing from the spirit and nature of the present invention and shall be deemed as falling within the protection scope of the present invention. The protection scope of the present invention depends on the protection scope of the appended claims.
The term “and/or” used herein is only used to describe the connecting relations between objects connected thereby, which may be of three types. For instance, “A and/or B” can represent the following three conditions: either A alone, or B alone, or both A and B. In addition, the character “/” used herein often indicates that the former and the latter objects connected thereby is in a “or” relationship.
The words, such as “first”, “second” and “third”, are used in the present application. Such a word is not intended to imply ordering but for the sake of identification, unless in a certain context. For instance, the expressions “the first version” and “the second version” do not necessarily mean that the first version is just the No. 1 version or created prior to the second version, or the first version is required or operated before the second version. In fact, these expressions are used to identify the different versions.
In the claims, any reference numeral in parentheses should not be interpreted as a limitation to the claims. The term “comprise” does not exclude the presence of elements or steps other than those listed in the claims. The words “a” or “an” in front of elements do not exclude the possibility of a plurality of such elements. The present invention can be carried out by means of hardware comprising a plurality of separate elements, or by appropriately programmed software or firmware, or by any combination thereof.
In device or system claims that enumerate several means, one or more of the means can be embodied by one and the same item of hardware. The mere fact that some measure is recited in dependent claims that are different from each other does not indicate that the combination of the measures cannot be used to advantage.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015 1 0142728 | Mar 2015 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2015/085567 | 7/30/2015 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/155169 | 10/6/2016 | WO | A |
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| Number | Date | Country |
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| 101425268 | May 2009 | CN |
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| Entry |
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| Office Action from China Application No. 201510142728.2 dated Sep. 29, 2016. |
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| Number | Date | Country | |
|---|---|---|---|
| 20170039979 A1 | Feb 2017 | US |
