Patent Application
20240290277
This application claims the priority benefit of Republic of Korea Patent Application No. 10-2023-0027318, filed on Feb. 28, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes as if fully set forth herein.
The present disclosure relates to electronic devices with a display, and more specifically, to a gate driving panel circuit, a display panel and a display device.
A display device may include a display panel in which a plurality of data lines and a plurality of gate lines are disposed, a data driving circuit for outputting data signals to the plurality of data lines, a gate driving circuit for outputting gate signals to the plurality of gate lines, and the like.
When gate signals are supplied normally through the plurality of gate lines, images are displayed normally on the display device. In a situation where gate driving is not performed normally, image quality may be degraded.
One or more embodiments of the present disclosure may provide a gate driving panel circuit having a structure suitable for a gate-in-panel (GIP) type, and a display device including the gate driving panel circuit.
One or more embodiments of the present disclosure may provide a gate driving panel circuit suitable for driving gate lines connected to subpixels having a structure capable of allowing sensing to be performed and a display device including the gate driving panel circuit.
One or more embodiments of the present disclosure may provide a display device have a wiring structure for stably supplying various types of signals or power to a gate driving panel circuit disposed in a display panel.
According to aspects of the present disclosure, a display device can be provided that includes a substrate including a display area in which images can be displayed and a non-display area different from the display area, a gate driving panel circuit disposed over the substrate, disposed in a gate driving panel circuit area in the non-display area, and configured to supply a plurality of scan signals through a plurality of scan signal lines, a plurality of clock signal lines disposed in a clock signal line area in the non-display area and delivering a plurality of clock signals to the gate driving panel circuit, at least one gate high voltage line disposed in a first power line area in the non-display area and delivering at least one gate high voltage to the gate driving panel circuit, and at least one gate low voltage line disposed in a second power line area in the non-display area and delivering at least one gate low voltage to the gate driving panel circuit, wherein the first power line area and the second power line area are separated from each other by the gate driving panel circuit area.
According to aspects of the present disclosure, a display panel can be provided that includes: a gate driving panel circuit disposed in a gate driving panel circuit area in a substrate and configured to supply a plurality of scan signals through a plurality of scan signal lines; a plurality of clock signal lines disposed in a clock signal line area in the substrate and delivering a plurality of clock signals to the gate driving panel circuit; at least one gate high voltage line disposed in a first power line area in the substrate and delivering at least one gate high voltage to the gate driving panel circuit; and at least one gate low voltage line disposed in a second power line area in the substrate and delivering at least one gate low voltage to the gate driving panel circuit, wherein the first power line area and the second power line area are separated from each other by the gate driving panel circuit area.
According to aspects of the present disclosure, a gate driving panel circuit can be provided that is disposed in a gate driving panel circuit area in a substrate and configured to supply a plurality of scan signals through a plurality of scan signal lines, the gate driving panel circuit comprising: an output buffer block comprising two or more scan output buffers configured to receive two or more scan clock signals and output two or more scan signals; and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block.
In addition to the aspects above described, other aspects, embodiments and examples of the present disclosure and resulted advantages will be described below, and variations thereof will become apparent to those skilled in the art from the following detailed description.
According to one or more embodiments of the present disclosure, a gate driving panel circuit may be provided that has a structure suitable for a gate-in-panel (GIP) type, and a display device may be provided that includes the gate driving panel circuit.
According to one or more embodiments of the present disclosure, a gate driving panel circuit may be provided that is suitable for driving gate lines connected to subpixels having a structure capable of allowing sensing to be performed, and a display device may be provided that includes the gate driving panel circuit.
Effects according to aspects of the present disclosure are not limited to the above description, more various effects will be apparent in following description.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain principles of the disclosure. In the drawings:
Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, the structures, embodiments, implementations, methods and operations described herein are not limited to the specific example or examples set forth herein and may be changed as is known in the art, unless otherwise specified. Like reference numerals designate like elements throughout the present disclosure, unless otherwise specified. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may thus be different from those used in actual products. Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following example embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art to fully understand the scope of the present disclosure. Further, the protected scope of the present disclosure is defined by claims and their equivalents. In the following description, where the detailed description of the relevant known function or configuration may unnecessarily obscure aspects of the present disclosure, a detailed description of such known function or configuration may be omitted.
The shapes, sizes, ratios, angles, numbers, and the like, which are illustrated in the drawings to describe various example embodiments of the present disclosure, are merely given by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. Where the terms “comprise,” “have,” “include,” “contain,” “constitute,” “make up of,” “formed of,” and the like are used, one or more other elements may be added unless the term, such as “only,” is used. An element described in the singular form is intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise.
Although the terms “first,” “second,” “A,” “B,” “(a),” or “(b),” and the like may be used herein to describe various elements, these elements should not be interpreted to be limited by these terms as they are not used to define a particular order or precedence. These terms are used only to distinguish one element from another; thus, related elements should not be interpreted to be limited by these terms as they are not used to define a particular order or precedence.
Further, the expression of a first element, a second elements “and/or” a third element should be understood as one of the first, second and third elements or as any or all combinations of the first, second and third elements. By way of example, A, B and/or C can refer to only A, only B, or only C; any or some combination of A, B, and C; or all of A, B, and C.
For the expression that an element or layer is “connected,” “coupled,” or “adhered” to another element or layer, the element or layer can not only be directly connected, coupled, or adhered to another element or layer, but also be indirectly connected, coupled, or adhered to another element or layer with one or more intervening elements or layers “disposed” or “interposed” between the elements or layers, unless otherwise specified. Further, the another element may be included in one or more of the two or more elements connected, combined, coupled, or contacted (to) one another.
For the expression that an element or layer “contacts,” “overlaps,” or the like with another element or layer, the element or layer can not only directly contact, overlap, or the like with another element or layer, but also indirectly contact, overlap, or the like with another element or layer with one or more intervening elements or layers “disposed” or “interposed” between the elements or layers, unless otherwise specified.
Where positional relationships are described, for example, where the positional relationship between two parts is described using “on,” “over,” “under,” “above,” “below,” “beside,” “next,” or the like, one or more other parts may be located between the two parts unless a more limiting term, such as “immediate(ly),” “direct(ly),” or “close(ly)” is used. For example, where an element or layer is disposed “on” another element or layer, a third element or layer may be interposed therebetween. Furthermore, the terms “left,” “right,” “top,” “bottom, “downward,” “upward,” “upper,” “lower,” and the like refer to an arbitrary frame of reference.
In describing a temporal relationship, when the temporal order is described as, for example, “after,” “subsequent,” “next,” or “before,” a case which is not continuous may be included unless a more limiting term, such as “just,” “immediate(ly),” or “direct(ly),” is used.
In construing an element, the element is to be construed as including an error or tolerance range even where no explicit description of such an error or tolerance range is provided. Further, the term “may” fully encompasses all the meanings of the term “can.”
The term “at least one” should be understood as including any or all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first element, a second element, and a third element” encompasses the combination of all three listed elements, combinations of any two of the three elements, as well as each individual element, the first element, the second element, and the third element.
The expression of a first element, a second elements “and/or” a third element should be understood as one of the first, second and third elements or as any or all combinations of the first, second and third elements. By way of example, A, B and/or C can refer to only A, only B, or only C; any or some combination of A, B, and C; or all of A, B, and C.
Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, for convenience of description, a scale in which each of elements is illustrated in the accompanying drawings may differ from an actual scale. Thus, the illustrated elements are not limited to the specific scale in which they are illustrated in the drawings.
Referring to
The at least one driving circuit may include a data driving circuit 120, a gate driving circuit 130, and the like, and further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.
The display panel 110 may include a substrate SUB, and signal lines such as a plurality of data lines DL, a plurality of gate lines GL, and the like disposed over the substrate SUB. The plurality of data lines DL and the plurality of gate lines GL may be connected to the plurality of subpixels SP.
The display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA in which an image is not displayed. A plurality of subpixels SP for displaying images may be disposed in the display area DA of the display panel 110. Driving circuits (e.g., 120, 130, and 140) may be electrically connected to, or be mounted in, the non-display area NDA of the display panel 110. Further, a pad portion including one or more pads to which one or more integrated circuits or one or more printed circuits are connected may be disposed in the non-display area NDA.
The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and can supply data signals to the plurality of data lines DL.
The gate driving circuit 130 may be a circuit for driving the plurality of gate lines GL, and can supply gate signals to the plurality of gate lines GL.
The controller 140 can supply a data control signal DCS to the data driving circuit 120 in order to control operation timing of the data driving circuit 120. The controller 140 can supply a gate control signal GCS to the gate driving circuit 130 in order to control operation timing of the gate driving circuit 130.
The controller 140 can start to scan pixels according to respective timings set in each frame, convert image data inputted from external devices or external image providing sources (e.g., host systems) in a data signal form readable by the data driving circuit 120 and then supply image data Data resulting from the converting to the data driving circuit 120, and in line with the scan of at least one pixel (or at least one pixel array) among the pixels, control the loading of the data to the at least one pixel at a time at which the illumination of at least one corresponding light emitting element of the at least one pixel is intended.
The controller 140 can receive, in addition to input image data, several types of timing signals including a vertical synchronous signal VSYNC, a horizontal synchronous signal HSYNC, an input data enable signal DE, a clock signal CLK, and the like from external devices, networks, or systems (e.g., a host system 150).
In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive one or more of the timing signals such as the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, the clock signal CLK, and the like, generate several types of control signals DCS and GCS, and output the generated signals to the data driving circuit 120 and the gate driving circuit 130.
For example, in order to control the gate driving circuit 130, the controller 140 can output several types of gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like.
Further, to control the data driving circuit 120, the controller 140 can output several types of data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable (SOE) signal, and the like.
The controller 140 may be implemented in a separate component from the data driving circuit 120, or integrated with the data driving circuit 120, so that the controller 140 and the data driving circuit 120 can be implemented in a single integrated circuit.
The data driving circuit 120 can drive a plurality of data lines DL by supplying data voltages corresponding to image data Data received from the controller 140 to the plurality of data lines DL. The data driving circuit 120 may also be referred to as a source driving circuit.
The data driving circuit 120 may include, for example, one or more source driver integrated circuits SDIC.
Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, and the like. In one or more embodiments, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.
In one or more embodiments, each source driver integrated circuit SDIC may be connected to the display panel 110 using a tape-automated-bonding (TAB) technique, or connected to a conductive pad such as a bonding pad of the display panel 110 using a chip-on-glass (COG) technique or a chip-on-panel (COP) technique, or connected to the display panel 110 using a chip-on-film (COF) technique.
The gate driving circuit 130 can supply a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller 140. The gate driving circuit 130 can sequentially drive a plurality of gate lines GL by sequentially supplying gate signals of the turn-on level voltage to the plurality of gate lines GL.
In one or more embodiments, the gate driving circuit 130 may be connected to the display panel 110 using the tape-automated-bonding (TAB) technique, or connected to a conductive pad such as a bonding pad of the display panel 110 using the chip-on-glass (COG) technique or the chip-on-panel (COP) technique, or connected to the display panel 110 using the chip-on-film (COF) technique. In one or more embodiments, the gate driving circuit 130 may be disposed in the non-display area NDA of the display panel 110 using the gate-in-panel (GIP) technique. The gate driving circuit 130 may be disposed on a substrate SUB, or connected to the substrate SUB. In an example where the gate driving circuit 130 is implemented with the GIP technique, the gate driving circuit 130 may be disposed in the non-display area NDA of the substrate SUB. The gate driving circuit 130 may be connected to the substrate SUB in examples where the gate driving circuit 130 is implemented with the chip-on-glass (COG) technique, the chip-on-film (COF) technique, or the like.
In an embodiment, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed not to overlap with subpixels SP, or disposed to overlap with one or more, or all, of the subpixels SP.
When a specific gate line is selected and driven by the gate driving circuit 130, the data driving circuit 120 can convert image data Data received from the controller 140 into data voltages in an analog form and supply the data voltages resulting from the converting to a plurality of data lines DL.
The data driving circuit 120 may be located in, and/or electrically connected to, but not limited to, only one side or portion (e.g., an upper edge or a lower edge) of the display panel 110. In one or more embodiments, the data driving circuit 120 may be located in, and/or electrically connected to, but not limited to, two sides or portions (e.g., an upper edge and a lower edge) of the display panel 110 or at least two of four sides or portions (e.g., the upper edge, the lower edge, a left edge, and a right edge) of the display panel 110 according to driving schemes, panel design schemes, or the like.
The gate driving circuit 130 may be located in, and/or electrically connected to, but not limited to, only one side or portion (e.g., a left edge or a right edge) of the display panel 110. In one or more embodiments, the gate driving circuit 130 may be located in, and/or electrically connected to, but not limited to, two sides or portions (e.g., a left edge and a right edge) of the display panel 110 or at least two of four sides or portions (e.g., an upper edge, a lower edge, the left edge, and the right edge) of the display panel 110 according to driving schemes, panel design schemes, or the like.
The controller 140 may be a timing controller used in the typical display technology or a control apparatus/device capable of additionally performing other control functionalities in addition to the typical function of the timing controller. In one or more embodiments, the controller 140 may be one or more other control circuits different from the timing controller, or a circuit or component in the control apparatus/device. The controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, and/or the like.
The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.
The controller 140 can transmit signals to, and receive signals from, the data driving circuit 120 via one or more predetermined interfaces. For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), a serial peripheral interface (SPI), and the like.
The controller 140 may include a storage medium such as one or more registers.
In one or more aspects, the display device 100 may be a display including a backlight unit such as a liquid crystal display device, or may be a self-emissive display such as an organic light emitting diode (OLED) display device, a quantum dot (QD) display device, a micro light emitting diode (M-LED) display device, a light emitting diode (LED) display device based on an inorganic material, or the like.
In an embodiment where the display device 100 is an organic light emitting display device, each subpixel SP may include, as a light emitting element, an organic light emitting diode (OLED), which is a self-emissive element.
In an embodiment where the display device 100 is a quantum dot display device, each subpixel SP may include a light emitting element configured with quantum dots, which are self-emissive semiconductor crystals.
In an embodiment where the display device 100 is an inorganic light emitting display device, each subpixel SP may include, as a light emitting element, an inorganic light emitting diode, which is a self-emissive element and includes an inorganic material. In this embodiment, the inorganic light emitting diode may be referred to as a micro light emitting diode (LED), and the inorganic light emitting display device may be referred to as a micro light emitting diode (LED) display device.
Referring to
For example, the corresponding subpixel circuit SPC of each subpixel SP may include a driving transistor DRT, a scan transistor SCT, a sensing transistor SENT, and a storage capacitor Cst. In this example, as the corresponding subpixel circuit SPC of each subpixel SP is configured with three transistors (3T: DRT, SCT and SENT) and one capacitor (1C: Cst), this structure of subpixel circuit SPC may be referred to as a “3T1C structure”.
Referring to
One of the anode electrode AND and the cathode electrode CAT may be a pixel electrode connected to a transistor such as the driving transistor DRT, and the other may be a common electrode to which a common voltage is applied. The pixel electrode may be an electrode disposed in each subpixel SP, and the common electrode may be an electrode commonly disposed in all or two or more of subpixels SP. For example, the common voltage may be a high voltage EVDD, which is a high level common voltage, or be a low voltage EVSS, which is a low level common voltage. In this example, the high voltage EVDD may be sometimes referred to as a driving voltage, and the low voltage EVSS may be sometimes referred to as a base voltage.
According to the example of
For example, the light emitting element ED may be an organic light emitting diode (OLED), a light emitting diode (LED) based on an inorganic material, a quantum dot light emitting element, or the like.
Referring to
The first node N1 of the driving transistor DRT may be the gate node of the driving transistor DRT, and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT may be the source node or drain node of the driving transistor DRT, be electrically connected to the source node or drain node of the sensing transistor SENT, and be electrically connected to the anode electrode AND of the light emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to a high voltage line DVL for carrying the high voltage EVDD.
Referring to
The scan transistor SCT can be turned on by a scan signal SC having a turn-on level voltage, and thereby, pass a data voltage Vdata carried through the data line DL to the first node N1 of the driving transistor DRT.
In an example where the scan transistor SCT is an n-type transistor, the turn-on level voltage of the scan signal SC may be a high level voltage. In another example where the scan transistor SCT is an p-type transistor, the turn-on level voltage of the scan signal SC may be a low level voltage. Hereinafter, for simplicity, discussions are provided based on the example where the scan transistor SCT is an n-type transistor. Accordingly, in discussions that follow, the turn-on level voltage of a scan signal SC can be a high level voltage.
Referring to
The sensing transistor SENT can be turned on by a sensing signal SE having a turn-on level voltage, and thereby, pass a reference voltage Vref carried through the reference voltage line RVL to the second node N2 of the driving transistor DRT. The sensing signal SE may be referred to as a second scan signal that is different from the scan signal SC.
Further, the sensing transistor SENT can be turned on by a sensing signal SE having the turn-on level voltage, and thereby, pass a voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL.
In an embodiment where the sensing transistor SENT is an n-type transistor, the turn-on level voltage of the sensing signal SE may be a high level voltage. In another example where the sensing transistor SENT is an p-type transistor, the turn-on level voltage of the sensing signal SE may be a low level voltage. Hereinafter, for simplicity, discussions are provided based on the example where the sensing transistor SENT is an n-type transistor. Accordingly, in discussions that follow, the turn-on level voltage of a scan signal SC can be a high level voltage.
For example, the function of the sensing transistor SENT configured to pass the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used when the corresponding subpixel SP is driven to sense one or more characteristic values of the subpixel SP. In this example, the voltage passed to the reference voltage line RVL may be a voltage to determine a characteristic value of the subpixel SP or a voltage where the characteristic value of the subpixel SP is contained.
Herein, the characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting element ED. For example, the characteristic value of the driving transistor DRT may include a threshold voltage and/or mobility of the driving transistor DRT. The characteristic value of the light emitting element ED may include a threshold voltage of the light emitting element ED.
Referring to
Referring to
The storage capacitor Cst may be an external capacitor intentionally designed to be located outside of the driving transistor DRT, other than an internal capacitor, such as a parasitic capacitor (e.g., a Cgs or a Cgd), that may be formed between the gate node and the source node (or the drain node) of the driving transistor DRT.
It should be noted that
The subpixel circuit SPC of the subpixel SP of
The subpixel SP of
As shown in
Referring to
Referring to
As shown in
As shown in
Referring to
Referring to
Referring to
As shown in
Referring to
The additional control circuit ACC may include one or more transistors and/or one or more capacitors.
The additional control circuit ACC may include a fourth node N4 electrically connected to the source node or drain node of the scan transistor SCT, a fifth node N5 electrically connected to the anode electrode AND of the light emitting element ED, a sixth node N6 electrically connected to the source node or drain node of the sensing transistor SENT, and a seventh node N7 electrically connected to a high voltage line DVL.
The additional control circuit ACC can be supplied with an additional voltage, when needed or desired.
Referring to
For example, the additional control circuit ACC may include a light emitting control transistor configured to control a connection between the second node N2 and the fifth node N5. In another example, the additional control circuit ACC may include a light emitting control transistor configured to control a connection between the seven node N7 and the third node N3.
Referring to
The compensation circuit may include a power switch SPRE, a sampling switch SAM, an analog-to-digital converter ADC, a compensator COMP, a memory MEM, and the like. In an embodiment, the compensation circuit may further include a subpixel SP (e.g., the subpixel SP of
The power switch SPRE can control a connection between the reference voltage line RVL and a reference voltage supply node Nref. A reference voltage Vref supplied by a power supply can be applied to the reference voltage supply node Nref, and the reference voltage Vref applied to the reference voltage supply node Nref can be passed to the reference voltage line RVL via the power switch SPRE.
The sampling switch SAM can control a connection between the analog-to-digital converter ADC and the reference voltage line RVL. When the analog-to-digital converter ADC is connected to the reference voltage line RVL by a sampling switch SAM, the analog-to-digital converter ADC can convert a voltage (analog voltage) of the connected reference voltage line RVL into a sensing value in the form of digital value.
As the subpixel SP is driven, a line capacitor Crvl can be formed between the reference voltage line RLV and the ground GND. The voltage of the reference voltage line RVL can correspond to an amount of electric charges stored across the line capacitor Crvl.
The analog-to-digital converter ADC can provide sensing data containing the sensing value to the compensator COMP.
The compensator COMP can determine at least one corresponding characteristic value of at least one circuit element (e.g., the light emitting element ED, the driving transistor DRT, and/or the like) included in the subpixel SP based on the sensing data from the analog-to-digital converter ADC. Thereafter, the compensator COMP can determine a compensation value to reduce or eliminate a difference in characteristic values between circuit elements based on the at least one characteristic value, and store the compensation value in the memory MEM.
For example, the compensation value may be information determined to reduce or eliminate a difference in characteristic values between light emitting elements ED or a difference in characteristic values between driving transistors DRT, and include an offset and/or a gain for modifying data.
The controller 140 can modify image data using the compensation value stored in the memory MEM, and supply the modified image data to the data driving circuit 120.
The data driving circuit 120 can convert the changed image data into a data voltage Vdata in the form of analog voltage by using a digital-to-analog converter DAC, and output the data voltage Vdata. In this manner, the compensation process can be executed.
Referring to
In an embodiment, the compensator COMP may be included in the controller 140.
As described above, the display device 100 can perform the compensation process to reduce a difference in characteristic values between the driving transistors DRT. Further, in order to perform the compensation process, the display device 100 can perform sensing driving to acquire information on a difference in characteristic values between the driving transistors DRT.
In an embodiment, the display device 100 according to aspects of the present disclosure can perform sensing driving in two sensing modes (a first sensing mode and a second sensing mode). Hereinafter, sensing driving in two sensing modes (the first sensing mode and the second sensing mode) will be described with reference to
Referring to
Referring to
Hereinafter, sensing driving in the first sensing mode and sensing driving in the second sensing mode will be described with reference to the compensation circuit of
First, sensing driving in the first sensing mode will be described with reference to
Referring to
Referring to
During the initialization sub-period Tinit, a voltage V1 of the first node N1 of the driving transistor DRT can be initialized to a sensing driving data voltage Vdata_SEN, and a voltage V2 of the second node N2 of the driving transistor DRT can be initialized to a sensing driving reference voltage Vref.
During the initialization sub-period Tinit, the scan transistor SCT and the sensing transistor SENT can be turned on, and the power switch SPRE can be turned on.
Referring to
During the tracking sub-period Track, the power switch SPRE can be turned off or the sensing transistor SENT can be turned off.
Accordingly, during the tracking sub-period Ttrack, while the first node N1 of the driving transistor DRT is in a constant voltage state with the sensing driving data voltage Vdata_SEN, the second node N2 of the driving transistor DRT can be electrically floating. Accordingly, during the tracking sub-period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can vary.
During the tracking sub-period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can increase until the voltage V2 of the second node N2 of the driving transistor DRT contains a threshold voltage Vth of the driving transistor DRT (i.e., until the voltage V2 of the second node N2 of the driving transistor DRT reaches a saturation point at which the threshold voltage Vth of the driving transistor DRT (or a shift ΔVth in the threshold voltage Vth) is contained in the voltage V2 of the second node N2 of the driving transistor DRT).
During the initialization sub-period Tinit, a voltage difference between the first node N1 and the second node N2 of the driving transistor DRT, which has been initialized, can be greater than or equal to the threshold voltage Vth of the driving transistor DRT. Accordingly, when the tracking sub-period Ttrack is initiated, the driving transistor DRT can be turned on and allow current to flow. Thereby, when the tracking sub-period Ttrack is initiated, the voltage V2 of the second node N2 of the driving transistor DRT can increase.
During the tracking sub-period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT cannot continuously increase.
As the latter part of the tracking sub-period Ttrack progresses, an increasing width of the voltage V2 of the second node N2 of the driving transistor DRT can be reduced, and the voltage V2 of the second node N2 of the driving transistor DRT can be eventually saturated.
A saturated voltage V2 of the second node N2 of the driving transistor DRT can correspond to a difference (Vdata_SEN−Vth) between the sensing driving data voltage Vdata_SEN and the threshold voltage Vth or a difference (Vdata_SEN−ΔVth) between the sensing driving data voltage Vdata_SEN and a shift in the threshold voltage ΔVth. The threshold voltage Vth may be a negative threshold voltage (−Vth) or a positive threshold voltage (+Vth).
When the voltage V2 of the second node N2 of the driving transistor DRT is saturated, the sampling sub-period Tsam can be initiated.
Referring to
During the sampling sub-period Tsam of the sensing driving period in the first sensing mode, a voltage of the reference voltage line RVL can be sensed by the analog-to-digital converter ADC. The voltage of the reference voltage line RVL can correspond to the voltage of the second node N2 of the driving transistor DRT, and correspond to a charging voltage of a line capacitor Crvl formed on the reference voltage line RVL.
During the sampling sub-period Tsam, a voltage Vsen sensed by the analog-to-digital converter ADC can be the voltage (Vdata_SEN−Vth) resulting from subtracting the threshold voltage Vth from the sensing driving data voltage Vdata_SEN or the voltage (Vdata_SEN-ΔVth) resulting from subtracting the threshold voltage shift ΔVth from the sensing driving data voltage Vdata_SEN. The Vth may be a positive threshold voltage or a negative threshold voltage.
Referring to
This saturation time Tsat may occupy most of the entire time period of the sensing driving period in the first sensing mode. Thus, in the case of the first sensing mode, it may take quite a long time (saturation time Tsat) for the voltage V2 of the second node N2 of a driving transistor DRT to reach saturation after increasing.
As described above, the sensing driving method for sensing the threshold voltage of a driving transistor DRT (i.e., the first sensing mode) is sometimes referred to as a slow mode since a long saturation time Tsat is taken until the voltage of the second node N2 of the driving transistor DRT contains the threshold voltage of the driving transistor DRT.
Next, sensing driving in the second sensing mode will be described with reference to
Referring to
Referring to
During the initialization sub-period Tinit, the scan transistor SCT and the sensing transistor SENT can be turned on, and the power switch SPRE can be turned on.
During the initialization sub-period Tinit, a voltage V1 of the first node N1 of the driving transistor DRT can be initialized to a sensing driving data voltage Vdata_SEN, and a voltage V2 of the second node N2 of the driving transistor DRT can be initialized to a sensing driving reference voltage Vref.
Referring to
During the tracking sub-period Ttrack, the preset tracking time Δt may be set to a relatively short time. Therefore, it may be difficult for the voltage V2 of the second node N2 of the driving transistor DRT to contain the threshold voltage Vth of the driving transistor DRT for a short tracking time Δt. To address this issue, the voltage V2 of the second node N2 of the driving transistor DRT can be changed enough to determine the mobility of the driving transistor DRT for such a short tracking time Δt.
Accordingly, the second sensing mode may be a sensing driving method for sensing the mobility of a driving transistor DRT.
During the tracking sub-period Ttrack, as the power switch SPRE is turned off or the sensing transistor SENT is turned off, the second node N2 of the driving transistor DRT can be electrically floating.
During the tracking sub-period Ttrack, the scan transistor SCT can be turned off by a scan signal SC of a turn-off level voltage, and the first node N1 of the driving transistor DRT can be also electrically floating.
During the initialization sub-period Tinit, a voltage difference between the first node N1 and the second node N2 of the driving transistor DRT, which has been initialized, can be greater than or equal to the threshold voltage Vth of the driving transistor DRT. Accordingly, when the tracking sub-period Ttrack is initiated, the driving transistor DRT can be turned on and allow current to flow.
The voltage difference between the first node N1 and the second node N2 of the driving transistor DRT may be denoted by Vgs when the first node N1 and the second node N2 of the driving transistor DRT are the gate node and the source node, respectively.
Accordingly, during the tracking sub-period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can increase. In this situation, the voltage V1 of the first node N1 of the driving transistor DRT can also increase.
During the tracking sub-period Ttrack, an increasing rate of the voltage V2 of the second node N2 of the driving transistor DRT can vary depending on the current capability (i.e., mobility) of the driving transistor DRT. As the driving transistor DRT has greater current capability (mobility), the voltage V2 of the second node N2 of the driving transistor DRT can increase more steeply.
After the tracking sub-period Ttrack progresses for the preset tracking time Δt, that is, after the voltage V2 of the second node N2 of the driving transistor DRT increases for the preset tracking time Δt, the sampling sub-period Tsam can proceed.
During the tracking sub-period Ttrack, an increasing rate of the voltage V2 of the second node N2 of the driving transistor DRT can corresponds to an amount of voltage variance ΔV in the second node N2 of the driving transistor DRT during the preset tracking time Δt. The amount of voltage variance ΔV in the second node N2 of the driving transistor DRT can correspond to an amount of voltage variance in the reference voltage line RVL.
Referring to
The analog-to-digital converter ADC can sense a voltage of the reference voltage line RVL. The voltage Vsen sensed by the analog-to-digital converter ADC can be a voltage (Vref+ΔV) increased from the reference voltage Vref by the amount of voltage variance ΔV for the preset tracking time Δt.
The voltage Vsen sensed by the analog-to-digital converter ADC can be the voltage of the reference voltage line RVL, and be the voltage of the second node N2 electrically connected to the reference voltage line RVL through the sensing transistor SENT.
Referring to
As described above, the sensing driving method for sensing the mobility of a driving transistor DRT (i.e., the second sensing mode) is sometimes referred to as a fast mode since this method can be executed by changing the voltage of the second node N2 of the driving transistor DRT for such a short period of time Δt.
Referring to
Referring to
The controller 140 can modify data Data based on the threshold voltage compensation value Φ and mobility compensation value α stored in the memory MEM, and supply the modified data (Data′=α×Data+Φ) to the data driving circuit 120.
The data driving circuit 120 can convert the data (Data′=α×Data+Φ) supplied by the controller 140 into a data voltage Vdata, and supply the converted data voltage Vdata to the corresponding subpixel SP. The data voltage Vdata supplied to the corresponding subpixel SP may be a data voltage Vdata capable of reducing a difference in threshold voltages and a difference in mobilities.
As described above, since a long sensing time is taken for threshold voltage sensing, and a short sensing time is sufficient for mobility sensing, therefore, the threshold voltage sensing can be performed in the first sensing mode corresponding to the slow sensing mode, and the mobility sensing can be performed in the second sensing mode corresponding to the fast sensing mode.
Referring to
Referring to
Referring to
The real-time sensing process may be performed every blank period BLANK between active periods ACT based on a vertical synchronization signal Vsync.
As discussed above, a relatively short period of time may be sufficient for sensing the mobility of a driving transistor DRT, and therefore, mobility sensing may be performed in the second sensing mode, which is the faster sensing mode among the two sensing modes.
Since a relatively short period of time is sufficient for mobility sensing, mobility sensing may be performed using any one of the on-sensing process, the off-sensing process, and the real-time sensing process. For example, mobility sensing, which may be performed in the second sensing mode, may be performed in the real-time sensing process that can reflect a variance in mobility in real time while the display is being driving. Accordingly, mobility sensing may be performed every blank period BLANK while the display is being driven.
As discussed above, threshold voltage sensing of a driving transistor DRT may take a relatively long sensing time including a long saturation time Vsat. Accordingly, threshold voltage sensing may be performed in the first sensing mode corresponding to the slow sensing mode among the two sensing modes.
Since threshold voltage sensing has a relatively long sensing time, threshold voltage sensing is desired to be performed using timing that does not interfere with the user's viewing. Accordingly, threshold voltage sensing of a driving transistor DRT may be performed after a power-off signal is generated by an input event from a user, and the like. For example, the threshold voltage sensing may be performed in a period during which the display device 100 is not driven for display image or a situation in which the user has no intention of viewing. In this manner, threshold voltage sensing may be performed using the off-sensing process.
Referring to
According to the configuration of
In an embodiment, in the configuration of
One or more gate driving panel circuit GPC may be located in the non-display area NDA of the display panel 110. In an embodiment, in the configuration of
The display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for a circuital connection between the plurality of source driver integrated circuits SDIC and other devices or components (e.g., 140, L/S, PMIC, and the like).
At least one circuit film CF on which a corresponding source driver integrated circuit SDIC is mounted may be connected to a corresponding one of the at least one source printed circuit board SPCB. For example, a first side of each of the at least one circuit film CF on which a corresponding source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and a second opposing side thereof may be electrically connected to the source printed circuit board SPCB.
A controller 140 (e.g., the controller 140 discussed above with reference to
The controller 140 can perform an overall control function related to the driving of the display panel 110 and control operations of the plurality of source driver integrated circuits SDIC and the gate driving panel circuit GPC.
The power management integrated circuit PMIC can supply various types of voltages or currents to the plurality of source driver integrated circuits SDIC, the gate driving panel circuit GPC, and the like, or control the various types of voltages or currents to be supplied.
A circuital connection between the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be performed through at least one connection cable CBL. For example, the connection cable CBL may be one of a flexible printed circuit (FPC) and a flexible flat cable (FFC).
In an embodiment, the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into one printed circuit board.
In an embodiment, the display device 100 according to aspects of the present disclosure may further include at least one level shifter L/S for adjusting a voltage level of a signal. For example, the level shifter L/S may be disposed on the control printed circuit board CPCB or the at least one source printed circuit board SPCB.
In an embodiment, in the display device 100 according to aspects of the present disclosure, the level shifter L/S can output signals needed for gate driving to the gate driving panel circuit GPC, which is the gate driving circuit 130 configured using the GIP technique.
For example, the power management integrated circuit PMIC can supply a signal to the level shifter L/S. The level shifter L/S can adjust a voltage level of the signal supplied by the power management integrated circuit PMIC. The signal whose voltage level has been adjusted by the level shifter L/S can be supplied to the gate driving panel circuit GPC.
For example, the level shifter L/S can supply a plurality of clock signals with different phases to the gate driving panel circuit GPC. The gate driving panel circuit GPC can generate a plurality of gate signals (e.g., at least one scan signal SC, at least one sensing signal SE, and the like) based on the plurality of clock signals supplied by the level shifter L/S, and output the generated gate signals to a plurality of gate lines (e.g., at least one scan signal line SCL, at least one sensing signal line SENL, and the like).
Referring to
Referring to
Hereinafter, discussions are provided on an example configuration of the gate driving panel circuit GPC and an example structure of the gate bezel area GBA where the gate driving panel circuit GPC is disposed in the display device 100 according to aspects of the present disclosure.
Referring to
Referring to
The first scan clock signal SCCLK1 and the first sensing clock signal SECLK1 can be output by a level shifter L/S.
The first scan signal SC1 and the first sensing signal SE1 can be applied to a first scan signal line SCL1 and a first sensing signal line SENL1, respectively.
Referring to
The second scan clock signal SCCLK2 and the second sensing clock signal SECLK2 can be output by a level shifter L/S.
The second scan signal SC2 and the second sensing signal SE2 can be applied to a second scan signal line SCL2 adjacent to the first scan signal line SCL1 and a second sensing signal line SENL2 adjacent to the first sensing signal line SENL1, respectively.
Referring to
Referring to
The first scan clock signal SCCLK1, the second scan clock signal SCCLK2, the third scan clock signal SCCLK3, and the fourth scan clock signal SCCLK4 can be output by a level shifter L/S.
The first scan signal SC1 can be applied to a first scan signal line SCL1. The second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4 respectively can be applied to a second scan signal line SCL2, a third scan signal line SCL3, and a fourth scan signal line SCL4, which are adjacent to the first scan signal line SCL1.
Referring to
Referring to
In the example where the first type of gate driving panel circuit GPC is applied, the output buffer block BUF can output at least one scan signal SC and at least one sensing signal SE.
In the example where the first type of gate driving panel circuit GPC is applied, a subpixel SP may have the two-gate driven structure as illustrated in
In the example where the second type of gate driving panel circuit GPC is applied, the output buffer block BUF can output two or more scan signals SC.
In the example where the second type of gate driving panel circuit GPC is applied, a subpixel SP may have the one-gate driven structure as illustrated in
Referring to
The Q node and QB node may have different voltage levels. For example, during a first period, when a voltage of the Q node is a high level voltage, a voltage of the QB node may be a low level voltage. During a second period before or after the first period, when a voltage of the Q node is a low level voltage, a voltage of the QB node may be a high level voltage.
Referring to
Referring to
The input and reset block IR may be a circuit block configured to control charging and discharging of the Q node. The inverter block IVT can be configured to control an electrical value (or level) of the Q node or the QB node such that a voltage level resulting from inverting a voltage level of the Q node becomes a voltage level of the QB node depending on a voltage of the Q node. The stabilization block ST can be configured to stabilize the Q node and the output of the gate driving panel circuit GPC depending on a voltage of the QB node during a period during which an output signal of the gate driving panel circuit GPC has a turn-off level voltage.
Each of the input and reset block IR, the stabilization block ST, and inverter block IVT may include at least one transistor.
The real-time sensing control block RT may be a circuit block configured to control the operation of the output buffer block BUF for real-time sensing driving. The real-time sensing driving may be a sensing driving performed in real time while the display is being driven, and be a sensing driving performed in each blank period BLANK between active periods ACT (see
The real-time sensing control block RT may include at least one transistor.
In the example where the first type of gate driving panel circuit GPC is applied, the real-time sensing control block RT can control voltages of the Q node and the QB node so that the output buffer block BUF can output a scan signal SC and a sensing signal SE to a subpixel SP where real-time sensing driving is performed.
In the example where the second type of gate driving panel circuit GPC is applied, the real-time sensing control block RT can control voltages of the Q node and the QB node so that the output buffer block BUF can output at least one scan signal SC to a subpixel SP where real-time sensing driving is performed.
Referring to
The gate driving panel circuit area GPCA may be an area in which the first type (1st Type) of gate driving panel circuit GPC is disposed. The first type (1st Type) of gate driving panel circuit GPC can output scan signals SC and sensing signals SE to be supplied to subpixels SP having the two-gate driven structure.
In an embodiment, several types of lines for carrying power, voltage, and signals to the gate driving panel circuit GPC may be disposed around the gate driving panel circuit area GPCA. For example, the clock signal line area CLA, the first power line area PLA1, and the second power line area PLA2 may be disposed around the gate driving panel circuit area GPCA of the gate bezel area GBA.
For example, the clock signal line area CLA and the first power line area PLA1 may be located on a first side of the gate driving panel circuit area GPCA, and the second power line area PLA2 may be located on a second opposing side of the gate driving panel circuit area GPCA.
For example, the gate driving panel circuit area GPCA may be located on a first side of the second power line area PLA2, and the display area DA may be located on a second opposing side of the second power line area PLA2.
The clock signal line area CLA may be an area in which clock signal lines are disposed for delivering several types of clock signals to the gate driving panel circuit GPC.
The first power line area PLA1 may be an area in which at least one gate high voltage line is disposed for delivering at least one gate high voltage to the gate driving panel circuit GPC.
In an embodiment, at least one control signal line for delivering at least one control signal to the gate driving panel circuit GPC may be further disposed in the first power line area PLA1. For example, the at least one control signal may include at least one of a start signal, a reset signal, and a line selection signal.
The second power line area PLA2 may be an area in which at least one gate low voltage line is disposed for delivering at least one gate low voltage to the gate driving panel circuit GPC.
Referring to
The carry clock signal line area CRC may be an area in which carry clock signal lines are disposed for delivering carry clock signals to the gate driving panel circuit GPC.
The scan clock signal line area SCC may be an area in which scan clock signal lines are disposed for delivering scan clock signals to the gate driving panel circuit GPC.
The sensing clock signal line area SEC may be an area in which sensing clock signal lines are disposed for delivering sensing clock signals to the gate driving panel circuit GPC.
An order in which the carry clock signal line area CRC, the scan clock signal line area SCC, and the sensing clock signal line area SEC are located may be set in various orders (e.g., CRC-SCC-SEC, SCC-CRC-SEC, SCC-SEC-CRC, SEC-SCC-CRC, or the like).
For example, among the carry clock signal line area CRC, the scan clock signal line area SCC, and the sensing clock signal line area SEC, the scan clock signal line area SCC may be located between the carry clock signal line area CRC and the sensing clock signal line area SEC, and the carry clock signal line area CRC may be located further away from the display area DA or the gate driving panel circuit area GPCA than the sensing clock signal line area SEC.
Referring to
The first gate driving panel circuit GPC #1 may include a first output buffer block BUF #1, a first logic block LOGIC #1, and a first real-time sensing control block RT #1.
The first output buffer block BUF #1 can be configured to output a first scan signal SC1 and a first sensing signal SE1 respectively to a first scan signal line SCL1 and a first sensing signal line SENL1 connected to a first subpixel SP. For example, the first scan signal SC1 may be an n-th scan signal SC(n), and the first sensing signal SE1 may be an n-th sensing signal SE(n).
The first logic block LOGIC #1 can be configured to control operation of the first output buffer block BUF #1 by controlling respective voltages of the Q node and the QB node of the first gate driving panel circuit GPC #1.
The second gate driving panel circuit GPC #2 may include only a second output buffer block BUF #2 and a second logic block LOGIC #2.
The second output buffer block BUF #2 can be configured to output a second scan signal SC2 and a second sensing signal SE2 respectively to a second scan signal line SCL2 and a second sensing signal line SENL2 connected to a second subpixel SP. For example, the second scan signal SC2 may be an (n+1)-th scan signal SC(n+1), and the second sensing signal SE2 may be an (n+1)-th sensing signal SE(n+1).
The second logic block LOGIC #2 can be configured to control operation of the second output buffer block BUF #2 by controlling respective voltages of the Q node and the QB node of the second gate driving panel circuit GPC #2.
The first real-time sensing control block RT #1 may be shared by the first gate driving panel circuit GPC #1 and the second gate driving panel circuit GPC #2. Accordingly, the size of the gate bezel area GBA can be significantly reduced.
The first real-time sensing control block RT #1 can be configured to control operation of the first output buffer block BUF #1 so that the first output buffer block BUF #1 can output a first scan signal SC1 and a first sensing signal SE1 for sensing driving to a corresponding first subpixel SP where real-time sensing driving will be performed by controlling respective voltages of the Q node and QB node of the first gate driving panel circuit GPC #1 during a first real-time sensing driving period (a first blank period).
The first real-time sensing control block RT #1 can be configured to control operation of the second output buffer block BUF #2 so that the second output buffer block BUF #2 can output a second scan signal SC2 and a second sensing signal SE2 for sensing driving to a corresponding second subpixel SP where real-time sensing driving will be performed by controlling respective voltages of the Q node and QB node of the second gate driving panel circuit GPC #2 during a second real-time sensing driving period (a second blank period), which is different from the first real-time sensing driving period (the first blank period).
At least one specific node of the first logic block LOGIC #1 and at least one specific node of the second logic block LOGIC #2 may be electrically connected to each other.
Referring to
Referring to
Accordingly, at least one gate high voltage line disposed in the first power line area PLA1 and at least one gate low voltage line disposed in the second power line area PLA2 may be separated by the gate driving panel circuit GPC disposed in the gate driving panel circuit area GPCA.
According to the configuration of the power-related lines and areas discussed above, since at least one high voltage line and at least one low voltage line do not overlap with each other, one or more high voltages (e.g., GVDD, GVDD2, GVDD_o, and GVDD_e in
In this implementation, the first gate driving panel circuit GPC #1 can be configured to output an odd-numbered n-th scan signal SC(n) and an odd-numbered n-th sensing signal SE(n). The n-th scan signal SC(n) can be supplied to an odd-numbered n-th scan signal line SCL, and the n-th sensing signal SE(n) can be supplied to an odd-numbered n-th sensing signal line SENL. Hereinafter, for convenience of description, the n-th scan signal SC(n) may be also referred to as a first scan signal SC1, and the n-th sensing signal SE(n) may be also referred to as a first sensing signal SE1.
Referring to
Referring to
Referring to
The carry pull-up transistor T6cr can be turned on or turned off depending on a voltage of a Q node, and thereby, control a connection between a carry clock node INcr to which an n-th carry clock signal CRCLK(n) is input and a carry output node OUTcr from which an n-th carry signal C(n) is output. Here, the n-th carry clock signal CRCLK(n) may also be referred to as a first carry clock signal CRCLK1, and the n-th carry signal C(n) may also be referred to as a first carry signal C1.
The gate node of the carry pull-up transistor T6cr may be the Q node or be electrically connected to the Q node. The source node (or drain node) of the carry pull-up transistor T6cr may be the carry output node OUTcr or be electrically connected to the carry output node OUTcr. The drain node (or source node) of the carry pull-up transistor T6cr may be the carry clock node INcr or be electrically connected to the carry clock node INcr.
When the carry pull-up transistor T6cr is turned on, the carry pull-up transistor T6cr can output the first carry signal C1 having a high level voltage using the first carry clock signal CRCLK1.
The carry output buffer CRBUF may further include a carry bootstrapping capacitor Ccr connected between the gate node and the source node (or drain node) of the carry pull-up transistor T6cr.
The carry pull-down transistor T7cr can be turned on or turned off depending on a voltage of a QB node, and thereby, control a connection between a third gate low voltage node LV3 to which a third gate low voltage GVSS2 is input and the carry output node OUTcr from which the n-th carry signal C(n) is output.
The gate node of the carry pull-down transistor T7cr may be the QB node or may be electrically connected to the QB node. The drain node or source node of the carry pull-down transistor T7cr may be the third gate low voltage node LV3 or be electrically connected to the third gate low voltage node LV3, and the source node or drain node of the carry pull-down transistor T7cr may be the carry output node OUTcr or be electrically connected to the carry output node OUTcr.
When the carry pull-down transistor T7cr is turned on, the carry pull-down transistor T7cr can output the first carry signal C1 having a low level voltage using the third gate low voltage GVSS2.
Referring to
Referring to
The scan pull-up transistor T6sc can be turned on or turned off depending on a voltage of the Q node, and thereby, control a connection between a scan clock node INsc to which an n-th scan clock signal SCCLK(n) is input and the scan output node OUTsc from which the n-th scan signal SC(n) is output. Here, the n-th scan clock signal SCCLK(n) may also be referred to as a first scan clock signal SCCLK1, and the n-th scan signal SC(n) may also be referred to as a first scan signal SC1.
The gate node of the scan pull-up transistor T6sc may be the Q node or be electrically connected to the Q node. The source node (or drain node) of the scan pull-up transistor T6sc may be the scan output node OUTsc or be electrically connected to the scan output node OUTsc. The drain node (or source node) of the scan pull-up transistor T6sc may be the scan clock node INsc or be electrically connected to the scan clock node INsc.
When the scan pull-up transistor T6sc is turned on, the scan pull-up transistor T6sc can output the first scan signal SC1 having a turn-on level voltage (e.g., a high level voltage) using the scan clock signal SCCLK to the scan output node OUTsc. The first scan signal SC1 having the turn-on level voltage (e.g., the high level voltage) output from the scan pull-up transistor T6sc can be applied to the first scan signal line SCL1.
The scan output buffer SCBUF may further include a scan bootstrapping capacitor Csc connected between the gate node and the source node (or drain node) of the scan pull-up transistor T6sc.
The scan pull-down transistor T7sc can be turned on or turned off depending on a voltage of the QB node, and thereby, control a connection between a first gate low voltage node LV1 to which a first gate low voltage GVSS0 is input and the scan output node OUTsc from which the n-th scan signal SC(n) is output.
The gate node of the scan pull-down transistor T7sc may be the QB node or may be electrically connected to the QB node. The drain node or source node of the scan pull-down transistor T7sc may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node or drain node of the scan pull-down transistor T7sc may be the scan output node OUTsc or be electrically connected to the scan output node OUTsc.
When the scan pull-down transistor T7sc is turned on, the scan pull-down transistor T7sc can output the first scan signal SC1 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the scan output node OUTsc. The first scan signal SC1 having the turn-off level voltage (e.g., the low level voltage) output from the scan pull-down transistor T7sc can be applied to the first scan signal line SCL1.
Referring to
Referring to
The sensing pull-up transistor T6se can be turned on or turned off depending on a voltage of the Q node, and thereby, control a connection between a sensing clock node INse to which an n-th sensing clock signal SECLK(n) is input and the sensing output node OUTse from which the n-th sensing signal SE(n) is output. Here, the n-th sensing clock signal SECLK(n) may also be referred to as a first sensing clock signal SECLK1, and the n-th sensing signal SE(n) may also be referred to as a first sensing signal SE1.
The gate node of the sensing pull-up transistor T6se may be the Q node or be electrically connected to the Q node. The source node (or drain node) of the sensing pull-up transistor T6se may be the sensing output node OUTse or be electrically connected to the sensing output node OUTse. The drain node (or source node) of the sensing pull-up transistor T6se may be the sensing clock node INse or be electrically connected to the sensing clock node INse.
When the sensing pull-up transistor T6se is turned on, the sensing pull-up transistor T6se can output the first sensing signal SE1 having a turn-on level voltage (e.g., a high level voltage) using the sensing clock signal SECLK to the sensing output node OUTse. The first sensing signal SE1 having the turn-on level voltage (e.g., the high level voltage) output from the sensing pull-up transistor T6se can be applied to the first sensing signal line SENL1.
The sensing output buffer SEBUF may further include a sensing bootstrapping capacitor Cse connected between the gate node and the source node (or drain node) of the sensing pull-up transistor T6se.
The sensing pull-down transistor T7se can be turned on or turned off depending on a voltage of the QB node, and thereby, control a connection between the first gate low voltage node LV1 to which the first gate low voltage GVSS0 is input and the sensing output node OUTse from which the n-th sensing signal SE(n) is output.
The gate node of the sensing pull-down transistor T7se may be the QB node or may be electrically connected to the QB node. The drain node or source node of the sensing pull-down transistor T7se may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node (or drain node) of the sensing pull-down transistor T7se may be the sensing output node OUTse or be electrically connected to the sensing output node OUTse.
When the sensing pull-down transistor T7se is turned on, the sensing pull-down transistor T7se can output the first sensing signal SE1 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the sensing output node OUTse. The first sensing signal SE1 having the turn-off level voltage (e.g., the low level voltage) output from the sensing pull-down transistor T7se can be applied to the first sensing signal line SENL1.
The respective gate nodes of the carry pull-up transistor T6cr, the scan pull-up transistor T6sc, and the sensing pull-up transistor T6se included in the first output buffer block BUF #1 may be electrically connected to each other.
The Q node may be shared by the carry output buffer CRBUF, the scan output buffer SCBUF, and the sensing output buffer SEBUF included in the first output buffer block BUF #1. The Q node may be electrically connected to the gate node of the carry pull-up transistor T6cr, the gate node of the scan pull-up transistor T6sc, and the gate node of the sensing pull-up transistor T6se. This structure may also be referred to as a “Q node sharing structure.”
The respective gate nodes of the carry pull-down transistor T7cr, the scan pull-down transistor T7sc, and the sensing pull-down transistor T7se included in the first output buffer block BUF #1 may be electrically connected to each other.
The QB node may be shared by the carry output buffer CRBUF, the scan output buffer SCBUF, and the sensing output buffer SEBUF included in the first output buffer block BUF #1. The QB node may be electrically connected to the gate node of the carry pull-down transistor T7cr, the gate node of the scan pull-down transistor T7sc, and the gate node of the sensing pull-down transistor T7se.
Referring to
Referring to
Referring to
For example, the Q node charging block of the input and reset block IR may include a first Q node charging transistor T1 and a second Q node charging transistor T1a connected in series between the first gate high voltage node HV1 and the Q node.
The gate node of the first Q node charging transistor T1 and the gate node of the second Q node charging transistor T1a may be electrically connected to each other, and receive the (n−3)-th carry signal C(n−3) together.
The first Q node charging transistor T1 may be connected between the first gate high voltage node HV1 and a Q node charging control node Nqc, and the second Q node charging transistor T1a may be connected between the Q node charging control node Nqc and the Q node.
Referring to
The gate node of the first Q node charge control transistor T11 and the gate node of the second Q node charge control transistor T11′ may be electrically connected to each other, and be connected to the third gate high voltage node HV3 together.
Referring to
The first Q node discharging transistor T3n and the second Q node discharging transistor T3na can be turned on or turned off together by an (n+3)-th carry signal C(n+3), and control a connection between the Q node and the third gate low voltage node LV3.
The first Q node discharging transistor T3n may be connected between the Q node and a holding node (QH node), and the second Q node discharging transistor T3na may be connected between the holding node (QH node) and the third gate low voltage node LV3.
The gate node of the first Q node discharging transistor T3n and the gate node of the second Q node discharging transistor T3na may be electrically connected to each other, and receive the (n+3)-th carry signal C(n+3) together.
Referring to
The third Q node discharging transistor T3nb and the fourth Q node discharging transistor T3nc can be turned on or turned off together by a start signal VST, and control a connection between the Q node and the third gate low voltage node LV3.
The third Q node discharging transistor T3nb may be connected between the Q node and the holding node (QH node), and the fourth Q node discharging transistor T3nc may be connected between the holding node (QH node) and the third gate low voltage node LV3.
Referring to
Referring to
The first stabilization transistor T3 may be connected between the Q node and the holding node (QH node). The first stabilization transistor T3 can be turned on or turned off depending on a voltage of the QB node, and thereby, control a connection between the Q node and the holding node (QH node).
The second stabilization transistor T3a may be connected between the holding node (QH node) and the third gate low voltage node LV3. The second stabilization transistor T3a can be turned on or turned off depending on a voltage of the QB node, and thereby, control a connection between the holding node (QH node) and the third gate low voltage node LV3.
Referring to
Referring to
The QB node charging transistor T4 may be connected between a second gate high voltage node HV2 and the QB node. The QB node charging transistor T4 can be turned on or turned off depending on a voltage of an inverter control node NIVT, and thereby, control a connection between the second gate high voltage node HV2 and the QB node. For example, a second gate high voltage GVDD_o may be applied to the second gate high voltage node HV2.
Referring to
The first inverter control transistor T4q may be connected between the inverter control node NIVT and a second gate low voltage node LV2. The first inverter control transistor T4q can be turned on or turned off depending on a voltage of the Q node, and thereby, control a connection between the inverter control node NIVT and the second gate low voltage node LV2. For example, a second gate low voltage GVSS1 can be applied to the second gate low voltage node LV2.
As the Q node has a low level voltage, the first inverter control transistor T4q can be turned off. In this situation, the inverter control node NIVT may be in a state in which the second gate high voltage GVDD_o supplied by a second inverter control transistor T41 is applied. Accordingly, the QB node charging transistor T4 can be turned on, and thereby, the second gate high voltage GVDD_o can be applied to the QB node (QB node charging).
As the Q node has a high level voltage, the first inverter control transistor T4q can be turned on, and thereby, pass the second gate low voltage GVSS1 to the inverter control node NIVT. Accordingly, the QB node charging transistor T4 can be turned off, thereby preventing the second gate high voltage GVDD_o from being applied to the QB node.
Referring to
The second inverter control transistor T41 may be connected between the second gate high voltage node HV2 and the inverter control node NIVT. The second inverter control transistor T41 can be turned on or turned off depending on the second gate low voltage GVSS1, and thereby, control a connection between the gate high voltage node HV2 and the inverter control node NIVT.
The second inverter control transistor T41 may always remain in a turn-on state, and can pass the second gate high voltage GVDD_o to the inverter control node NIVT.
Referring to
The first QB node discharging transistor T5 can be turned on or turned off depending on an (n−3)-th carry signal C(n−3), and thereby, control a connection between the QB node and the third gate low voltage node LV3. When first QB node discharging transistor T5 is turned on, the third gate low voltage GVSS2 can be applied to the QB node. Accordingly, the QB node can be discharged.
Referring to
The second QB node discharging transistor T5q can be turned on or turned off depending on a voltage of the Q node, and thereby, control a connection between the QB node and the third gate low voltage node LV3. When second QB node discharging transistor T5q is turned on, the third gate low voltage GVSS2 can be applied to the QB node. Accordingly, the QB node can be discharged.
Referring to
A reset signal RST can be input to the gate node of the third QB node discharging transistor T5a. That is, the third QB node discharging transistor T5a can be turned on or turned off depending on a voltage of the reset signal RST.
The gate node of the fourth QB node discharging transistor T5b may be electrically connected to an intermediate node M. That is, the fourth QB node discharging transistor T5b can be turned on or turned off depending on a voltage of the intermediate node M. For example, the intermediate node M may be a node included in the first real-time sensing control block RT #1.
Referring to
Referring to
Referring to
Respective gate nodes of the first holding node control transistor T3q and the second holding node control transistor T3q′ may be connected to the Q node together.
When the Q node has a high level voltage, both the first holding node control transistor T3q and the second holding node control transistor T3q′ can be turned on, and thereby, the first gate high voltage GVDD can be applied to the holding node (QH node). As the holding node (QH node) has the first gate high voltage GVDD, regardless of respective switching of the third Q node discharging transistor T3nb, the first Q node discharging transistor T3n, and the first stabilization transistor T3, the Q node can stably maintain a high level voltage.
Referring to
Referring to
Referring to
The first sensing control transistor Ta and the second sensing control transistor Tb may be connected in series between a previous carry input node Npc and the intermediate node M. For example, an (n−2)-th carry signal C(n−2) may be input to the previous carry input node Npc.
In order that real-time sensing driving is performed for a subpixel SP intended to receive (or to be determined to receive) the first scan signal SC1 and the first sensing signal SE1 output from the first gate driving panel circuit GPC #1, the first gate driving panel circuit GPC #1 is needed to output the first scan signal SC1 and the first sensing signal SE1 as sensing driving gate signals during a real-time sensing driving period. For example, the real-time sensing driving period may be included in a blank period BLANK.
The first real-time sensing control block RT #1 may use a line selection signal LSP so that the first scan signal SC1 and the first sensing signal SE1 can be output as sensing driving gate signals during a real-time sensing driving period.
During the real-time sensing driving period, the line selection signal LSP can be commonly input to respective gate nodes of the first sensing control transistor Ta and the second sensing control transistor Tb. For example, the line selection signal LSP may be a pulse-shaped signal, and can be commonly applied to the gate nodes of the first sensing control transistor Ta and the second sensing control transistors Tb in a period between a start time and an end time of a frame.
The third sensing control transistor Tc can be turned on or turned off depending on a voltage of the intermediate node M, and thereby, control a connection between a connection point Ps and the first gate high voltage node HV1. For example, the connection point Ps may be a point at which the first sensing control transistor Ta and the second sensing control transistor Tb are connected.
The fourth sensing control transistor T1b and the fifth sensing control transistor T1c may be connected in series between the first gate high voltage node HV1 and the Q node.
The gate node of the fourth sensing control transistor T1b may be connected to the intermediate node M. A reset signal RST can be input to the gate node of the fifth sensing control transistor T1c.
During a real-time sensing driving period, the fourth sensing control transistor T1b and the fifth sensing control transistor T1c can be turned on depending on a voltage of the intermediate node M and the reset signal RST, respectively, and thereby, pass the first gate high voltage GVDD to the Q node. Accordingly, the Q node can be charged during the real-time sensing operation period. For example, the real-time sensing driving period may be included in a blank period BLANK.
Referring to
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Referring to
A time period of a respective high level voltage period of each of the scan signals (SC1 to SC16) may be two horizontal times 2HT. The second half of the high level voltage period of a first scan signal SC1 and the first half of the high level voltage period of a second scan signal SC2 may overlap by one horizontal time 1HT. The second half of the high level voltage period of the second scan signal SC2 and the first half of the high level voltage period of the third scan signal SC3 may overlap by one horizontal time 1HT.
Referring to
A time period of a respective high level voltage period of each of the carry signals (C1 to C12) may be two horizontal times 2HT. The second half of the high level voltage period of the first carry signal C1 and the first half of the high level voltage period of the second carry signal C2 may overlap by one horizontal time 1HT. The second half of the high level voltage period of the second carry signal C2 and the first half of the high level voltage period of the third carry signal C3 may overlap by one horizontal time 1HT.
Referring to
Referring to
Carry clock signal lines CL_CRCLK for delivering carry clock signals CRCLK to the gate driving panel circuit GPC may be disposed in the carry clock signal line area CRC.
Scan clock signal lines CL_SCCLK for delivering scan clock signals SCCLK to the gate driving panel circuit GPC may be disposed in the scan clock signal line area SCC.
Sensing clock signal lines CL_SECLK for delivering sensing clock signals SECLK to the gate driving panel circuit GPC may be disposed in the sensing clock signal line area SEC.
Among the carry clock signal line area CRC, the scan clock signal line area SCC, and the sensing clock signal line area SEC, the scan clock signal line area SCC may be located between the carry clock signal line area CRC and the sensing clock signal line area SEC, the carry clock signal line area CRC may be located furthest away from the display area DA, and the sensing clock signal line area SEC may be located closest to the display area DA.
Among the carry clock signal line area CRC, the scan clock signal line area SCC, and the sensing clock signal line area SEC, the carry clock signal line area CRC may be located furthest away from the gate driving panel circuit area GPCA, and the sensing clock signal line area SEC may be located closest to the gate driving panel circuit area GPCA.
Referring to
Referring to
Referring to
The gate high voltage line HVL may have a greater width than the start signal line CSL1, the reset signal line CSL4, and the line selection signal line CSL5.
For example, the first driving sequence control signal line CSL2 and the second driving sequence control signal line CSL3 may be disposed in two specific line areas in the first power line area PLA1. In another example, instead of the first driving sequence control signal line CSL2 and the second driving sequence control signal line CSL3, two gate high voltage lines may be disposed in the two specific line areas in the first power line area PLA1.
Referring to
Referring to
Referring to
For example, the clock signal line area CLA, the first power line area PLA1, and the second power line area PLA2 may be disposed around the gate driving panel circuit area GPCA in the gate bezel area GBA.
For example, the clock signal line area CLA and the first power line area PLA1 may be located on a first side of the gate driving panel circuit area GPCA, and the first power line area PLA1 may be located between the clock signal line area CLA and the gate driving panel circuit area GPCA. The second power line area PLA2 may be located on a second opposing side of the gate driving panel circuit area GPCA. The second power line area PLA2 may be located between the gate driving panel circuit area GPCA and the display area DA. For example, the gate driving panel circuit area GPCA may be located on a first side of the second power line area PLA2, and the display area DA may be located on a second opposing side of the second power line area PLA2.
The clock signal line area CLA may be included in the gate bezel area GBA of the non-display area NDA, and be an area in which a plurality of clock signal lines for delivering a plurality of clock signals to the gate driving panel circuit GPC are disposed.
The first power line area PLA1 may be included in the gate bezel area GBA of the non-display area NDA, and be an area in which at least one gate high voltage line for delivering at least one gate high voltage to the gate driving panel circuit GPC is disposed.
For example, a plurality of gate high voltage lines for delivering a plurality of gate high voltages to the gate driving panel circuit GPC may be disposed in the first power line area PLA1. For example, all of the plurality of gate high voltages may have a same high voltage value. In another example, one or more of the plurality of gate high voltages may have different high voltage values from the remaining gate high voltages. The plurality of gate high voltages may be high voltages having different usages from each other.
In an embodiment, at least one control signal line for delivering at least one control signal to the gate driving panel circuit GPC may be further disposed in the first power line area PLA1. For example, the at least one control signal may include at least one of a start signal VST, a reset signal RST, and a line selection signal LSP.
The second power line area PLA2 may be included in the gate bezel area GBA of the non-display area NDA, and be an area in which at least one gate low voltage line for delivering at least one gate low voltage to the gate driving panel circuit GPC is disposed.
For example, a plurality of gate low voltage lines for delivering a plurality of gate low voltages to the gate driving panel circuit GPC may be disposed in the second power line area PLA2. For example, all of the plurality of gate low voltages may have a same low voltage value. In another example, one or more of the plurality of gate high voltages may have different high voltage values from the remaining gate high voltages. The plurality of gate low voltages may be low voltages having different usages from each other.
Referring to
The scan clock signal line area SCC may be an area in which scan clock signal lines are disposed for delivering scan clock signals to the gate driving panel circuit GPC.
The carry clock signal line area CRC may be an area in which carry clock signal lines are disposed for delivering carry clock signals to the gate driving panel circuit GPC.
In the example where the second type of gate driving panel circuit GPC is applied, the clock signal line area CLA may not include a sensing clock signal line area.
For example, among the scan clock signal line area SCC and the carry clock signal line area CRC, the scan clock signal line area SCC may be located further away from the display area DA or the gate driving panel circuit area GPCA than the carry clock signal line area CRC, and the carry clock signal line area CRC may be located closer to the display area DA or the gate driving panel circuit area GPCA than the scan clock signal line area SCC.
In another example, the carry clock signal line area CRC may be located further away from the display area DA or the gate driving panel circuit area GPCA than the scan clock signal line area SCC. The scan clock signal line area SCC may be located closer to the display area DA or the gate driving panel circuit area GPCA than the carry clock signal line area CRC.
Referring to
The first gate driving panel circuit GPC #1 may include a first output buffer block BUF #1, a first logic block LOGIC #1, and a first real-time sensing control block RT #1.
The first output buffer block BUF #1 can be configured to output two or more scan signals SC to two or more scan signal lines SCL. For example, the first output buffer block BUF #1 can be configured to output four scan signals (SC1, SC2, SC3, and SC4) to four scan signal lines (SCL1, SCL2, SCL3, and SCL4), respectively.
The four scan signals (SC1, SC2, SC3, and SC4) may include a first scan signal SC1 corresponding to an n-th scan signal SC(n), a second scan signal SC2 corresponding to an (n+1)-th scan signal SC(n+1), a third scan signal SC3 corresponding to an (n+2)-th scan signal SC(n+2), and a fourth scan signal SC4 corresponding to an (n+3)-th scan signal SC(n+3).
The first scan signal SC1, the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4 can be applied to the first scan signal line SCL1, the second scan signal line SCL2, the third scan signal line SCL3, and the fourth scan signal line SCL4, respectively.
The first logic block LOGIC #1 can be configured to control operation of the first output buffer block BUF #1 by controlling respective voltages of Q and QB nodes of the first gate driving panel circuit GPC #1.
The first real-time sensing control block RT #1 can be configured to control operation of the first output buffer block BUF #1, so that the first output buffer block BUF #1 can output the first scan signal SC1 for sensing driving to a corresponding first subpixel SP, where real-time sensing driving will be performed by controlling respective voltages of the Q and QB nodes of the first gate driving panel circuit GPC #1 during a first real-time sensing driving period.
Referring to
Accordingly, at least one gate high voltage line disposed in the first power line area PLA1 and at least one gate low voltage line disposed in the second power line area PLA2 may be separated by the gate driving panel circuit GPC disposed in the gate driving panel circuit area GPCA.
According to the configuration of the power-related lines and areas discussed above, since at least one high voltage line and at least one low voltage line do not overlap with each other, one or more high voltages (e.g., GVDD, GVDD2, GVDD_o, and GVDD_e in
Hereinafter, for convenience of description, an n-th scan signal SC(n) may be referred to as a first scan signal SC1, and an (n+1)-th scan signal SC(n+1) may be referred to as a second scan signal SC2, an (n+2)-th scan signal SC(n+2) may be referred to as a third scan signal SC3, and an (n+3)-th scan signal SC(n+3) may be referred to as a fourth scan signal SC4.
Further, for convenience of description, an n-th scan clock signal SCCLK(n) may be referred to as a first scan clock signal SCCLK1, an (n+1)-th scan clock signal SCCLK (n+1) may be described as a second scan clock signal SCCLK2, an (n+2)-th scan clock signal SCCLK (n+2) may be described as a third scan clock signal SCCLK3, and an (n+3)-th scan clock signal SCCLK (n+3) may be referred to as a fourth scan clock signal SCCLK4.
Further, for convenience of description, an n-th carry signal C(n) may be referred to as a first carry signal C1, and an n-th carry clock signal CRCLK(n) may be referred to as a first carry clock signal CRCLK1. Referring to
Except for input carry signals and a configuration of the first output buffer block BUF #1, the first gate driving panel circuit GPC #1 of the second type of gate driving panel circuit GPC illustrated in
Referring to
Referring to
The carry pull-up transistor T6cr can be turned on or turned off depending on a voltage of a Q node, and thereby, control a connection between a carry clock node INcr to which a first carry clock signal CRCLK1 is input and a carry output node OUTcr from which a first carry signal C1 is output.
The gate node of the carry pull-up transistor T6cr may be the Q node or be electrically connected to the Q node. The source node (or drain node) of the carry pull-up transistor T6cr may be the carry output node OUTcr or be electrically connected to the carry output node OUTcr. The drain node (or source node) of the carry pull-up transistor T6cr may be the carry clock node INcr or be electrically connected to the carry clock node INcr.
When the carry pull-up transistor T6cr is turned on, the carry pull-up transistor T6cr can output the first carry signal C1 having a high level voltage using the first carry clock signal CRCLK1.
The carry output buffer CRBUF may further include a carry bootstrapping capacitor Ccr connected between the gate node and the source node (or drain node) of the carry pull-up transistor T6cr.
The carry pull-down transistor T7cr can be turned on or turned off depending on a voltage of a QB node, and thereby, control a connection between a third gate low voltage node LV3 to which a third gate low voltage GVSS2 is input and the carry output node OUTcr from which the first carry signal C1 is output.
The gate node of the carry pull-down transistor T7cr may be the QB node or may be electrically connected to the QB node. The drain node or source node of the carry pull-down transistor T7cr may be the third gate low voltage node LV3 or be electrically connected to the third gate low voltage node LV3, and the source node or drain node of the carry pull-down transistor T7cr may be the carry output node OUTcr or be electrically connected to the carry output node OUTcr. When the carry pull-down transistor T7cr is turned on, the carry pull-down transistor T7cr can output the first carry signal C1 having a low level voltage using the third gate low voltage GVSS2.
Referring to
Referring to
The first scan pull-up transistor T6sc1 can be turned on or turned off depending on a voltage of the Q node, and control a connection between a first scan clock node INsc1 to which a first scan clock signal SCCLK1 is input and the first scan output node OUTsc1 from which the first scan signal SC1 is output.
The gate node of the first scan pull-up transistor T6sc1 may be the Q node or be electrically connected to the Q node. The source node (or drain node) of the first scan pull-up transistor T6sc1 may be the first scan output node OUTsc1 or may be electrically connected to the first scan output node OUTsc1. The drain node (or source node) of the first scan pull-up transistor T6sc1 may be the first scan clock node INsc1 or may be electrically connected to the first scan clock node INsc1.
When the first scan pull-up transistor T6sc1 is turned on, the first scan pull-up transistor T6sc1 can output the first scan signal SC1 having a turn-on level voltage (e.g., a high level voltage) using the first scan clock signal SCCLK1 to the first scan output node OUTsc1.
The first scan output buffer SCBUF1 may further include a first scan bootstrapping capacitor Csc1 connected between the gate node and the source node (or drain node) of the first scan pull-up transistor T6sc1.
The first scan pull-down transistor T7sc1 can be turned on or turned off depending on a voltage of the QB node, and control a connection between a first gate low voltage node LV1 to which a first gate low voltage GVSS0 is input and the first scan output node OUTsc1 from which the first scan signal SC1 is output.
The gate node of the first scan pull-down transistor T7sc1 may be the QB node or may be electrically connected to the QB node. The drain node or source node of the first scan pull-down transistor T7sc1 may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node or drain node of the first scan pull-down transistor T7sc1 may be the first scan output node OUTsc1 or may be electrically connected to the first scan output node OUTsc1.
When the first scan pull-down transistor T7sc1 is turned on, the first scan pull-down transistor T7sc1 can output the first scan signal SC1 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the first scan output node OUTsc1.
Referring to
Referring to
The second scan pull-up transistor T6sc2 can be turned on or turned off depending on a voltage of the Q node, and control a connection between a second scan clock node INsc2 to which a second scan clock signal SCCLK2 is input and the second scan output node OUTsc2 from which the second scan signal SC2 is output.
The gate node of the second scan pull-up transistor T6sc2 may be the Q node or be electrically connected to the Q node. The source node or drain node of the second scan pull-down transistor T6sc2 may be the second scan output node OUTsc2 or may be electrically connected to the second scan output node OUTsc2. The drain node (or source node) of the second scan pull-up transistor T6sc2 may be the second scan clock node INsc2 or may be electrically connected to the second scan clock node INsc2.
When the second scan pull-up transistor T6sc2 is turned on, the second scan pull-up transistor T6sc2 can output the second scan signal SC2 having a turn-on level voltage (e.g., a high level voltage) using the second scan clock signal SCCLK2 to the second scan output node OUTsc2.
The second scan output buffer SCBUF2 may further include a second scan bootstrapping capacitor Csc2 connected between the gate node and the source node (or drain node) of the second scan pull-up transistor T6sc2.
The second scan pull-down transistor T7sc2 can be turned on or turned off depending on a voltage of the QB node, and control a connection between the first gate low voltage node LV1 to which the first gate low voltage GVSS0 is input and the second scan output node OUTsc2 from which the second scan signal SC2 is output.
The gate node of the second scan pull-down transistor T7sc2 may be the QB node or may be electrically connected to the QB node. The drain node or source node of the second scan pull-down transistor T7sc2 may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node or drain node of the second scan pull-down transistor T7sc2 may be the second scan output node OUTsc2 or may be electrically connected to the second scan output node OUTsc2.
When the second scan pull-down transistor T7sc2 is turned on, the second scan pull-down transistor T7sc2 can output the second scan signal SC2 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the second scan output node OUTsc2.
Referring to
Referring to
The third scan pull-up transistor T6sc3 can be turned on or turned off depending on a voltage of the Q node, and control a connection between a third scan clock node INsc3 to which a third scan clock signal SCCLK3 is input and the third scan output node OUTsc3 from which the third scan signal SC3 is output.
The gate node of the third scan pull-up transistor T6sc3 may be the Q node or be electrically connected to the Q node. The source node or drain node of the third scan pull-down transistor T6sc3 may be the third scan output node OUTsc3 or may be electrically connected to the third scan output node OUTsc3. The drain node (or source node) of the third scan pull-up transistor T6sc3 may be the third scan clock node INsc3 or may be electrically connected to the third scan clock node INsc3.
When the third scan pull-up transistor T6sc3 is turned on, the third scan pull-up transistor T6sc3 can output the third scan signal SC3 having a turn-on level voltage (e.g., a high level voltage) using the third scan clock signal SCCLK3 to the third scan output node OUTsc3.
The third scan output buffer SCBUF3 may further include a third scan bootstrapping capacitor Csc3 connected between the gate node and the source node (or drain node) of the third scan pull-up transistor T6sc3.
The third scan pull-down transistor T7sc3 can be turned on or turned off depending on a voltage of the QB node, and control a connection between the first gate low voltage node LV1 to which the first gate low voltage GVSS0 is input and the third scan output node OUTsc3 from which the third scan signal SC3 is output.
The gate node of the third scan pull-down transistor T7sc3 may be the QB node or may be electrically connected to the QB node. The drain node or source node of the third scan pull-down transistor T7sc3 may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node or drain node of the third scan pull-down transistor T7sc3 may be the third scan output node OUTsc3 or may be electrically connected to the third scan output node OUTsc3.
When the third scan pull-down transistor T7sc3 is turned on, the third scan pull-down transistor T7sc3 can output the third scan signal SC3 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the third scan output node OUTsc3.
Referring to
Referring to
The fourth scan pull-up transistor T6sc4 can be turned on or turned off depending on a voltage of the Q node, and control a connection between a fourth scan clock node INsc4 to which a fourth scan clock signal SCCLK4 is input and the fourth scan output node OUTsc4 from which the fourth scan signal SC4 is output.
The gate node of the fourth scan pull-up transistor T6sc4 may be the Q node or be electrically connected to the Q node. The source node or drain node of the fourth scan pull-down transistor T6sc4 may be the fourth scan output node OUTsc4 or may be electrically connected to the fourth scan output node OUTsc4. The drain node (or source node) of the fourth scan pull-up transistor T6sc4 may be the fourth scan clock node INsc4 or may be electrically connected to the fourth scan clock node INsc4.
When the fourth scan pull-up transistor T6sc4 is turned on, the fourth scan pull-up transistor T6sc4 can output the fourth scan signal SC4 having a turn-on level voltage (e.g., a high level voltage) using the fourth scan clock signal SCCLK4 to the fourth scan output node OUTsc4.
The fourth scan output buffer SCBUF4 may further include a fourth scan bootstrapping capacitor Csc4 connected between the gate node and the source node (or drain node) of the fourth scan pull-up transistor T6sc4.
The fourth scan pull-down transistor T7sc4 can be turned on or turned off depending on a voltage of the QB node, and control a connection between the first gate low voltage node LV1 to which the first gate low voltage GVSS0 is input and the fourth scan output node OUTsc4 from which the fourth scan signal SC4 is output.
The gate node of the fourth scan pull-down transistor T7sc4 may be the QB node or may be electrically connected to the QB node. The drain node or source node of the fourth scan pull-down transistor T7sc4 may be the first gate low voltage node LV1 or be electrically connected to the first gate low voltage node LV1. The source node or drain node of the fourth scan pull-down transistor T7sc4 may be the fourth scan output node OUTsc4 or may be electrically connected to the fourth scan output node OUTsc4.
When the fourth scan pull-down transistor T7sc4 is turned on, the fourth scan pull-down transistor T7sc4 can output the fourth scan signal SC4 having a turn-off level voltage (e.g., a low level voltage) using the first gate low voltage GVSS0 to the fourth scan output node OUTsc4.
Respective gate nodes of the carry pull-up transistor T6cr, the first scan pull-up transistor T6sc1, the second scan pull-up transistor T6sc2, the third scan pull-up transistor T6sc3, and the fourth scan pull-up transistor T6sc4, which are included in the first output buffer block BUF #1, may be electrically connected to each other.
For example, the Q node may be shared by the carry output buffer CRBUF, the first scan output buffer SCBUF1, the second scan output buffer SCBUF2, the third scan output buffer SCBUF3, and the fourth scan output buffer SCBUF4, which are included in the first output buffer block BUF #1. The Q node may be electrically connected to respective gate nodes of the carry pull-up transistor T6cr, the first scan pull-up transistor T6sc1, the second scan pull-up transistor T6sc2, the third scan pull-up transistor T6sc3, and the fourth scan pull-up transistor T6sc4, which are included in the first output buffer block BUF #1. This structure may also be referred to as a “Q node sharing structure.”
Respective gate nodes of the carry pull-down transistor T7cr, the first scan pull-down transistor T7sc1, the second scan pull-down transistor T7sc2, the third scan pull-down T7sc3, and the fourth scan pull-down transistor T7sc4, which are included in the first output buffer block BUF #1, may be electrically connected to each other.
For example, the QB node may be shared by the carry output buffer CRBUF, the first scan output buffer SCBUF1, the second scan output buffer SCBUF2, the third scan output buffer SCBUF3, and the fourth scan output buffer SCBUF4, which are included in the first output buffer block BUF #1. The QB node may be electrically connected to respective gate nodes of the carry pull-down transistor T7cr, the first scan pull-down transistor T7sc1, the second scan pull-down transistor T7sc2, the third scan pull-down T7sc3, and the fourth scan pull-down transistor T7sc4, which are included in the first output buffer block BUF #1.
Referring to
Referring to
The first logic block LOGIC #1 illustrated in
As a first difference, in the input and reset block IR of the first logic block LOGIC #1 illustrated in
As a second difference, in the inverter block IVT of the first logic block LOGIC #1 illustrated in
Hereinafter, the circuit configuration of the first logic block LOGIC #1 illustrated in
Referring to
Referring to
For example, the Q node charging block of the input and reset block IR may include the first Q node charging transistor T1 and the second Q node charging transistor T1a connected in series between the first gate high voltage node HV1 and the Q node.
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Respective gate nodes of the first holding node control transistor T3q and the second holding node control transistor T3q′ may be connected to the Q node together.
Referring to
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The high level voltage period of the first scan signal SC1 and the high level voltage period of the second scan signal SC2 may overlap in time. The high level voltage period of the second scan signal SC2 and the high level voltage period of the third scan signal SC3 may overlap in time. The high level voltage period of the third scan signal SC3 and the high level voltage period of the fourth scan signal SC4 may overlap in time.
As described above, a gate driving scheme in which respective high level voltage periods of two scan signals, which are output immediately adjacent to each other in time, overlap in time may be referred to as an “overlap gate driving scheme.”
Referring to
Referring to
A time period of a respective high level voltage period of each of the scan signals (SC1 to SC12) may be two horizontal times 2HT. The second half of the high level voltage period of the first scan signal SC1 and the first half of the high level voltage period of the second scan signal SC2 may overlap by one horizontal time 1HT. The second half of the high level voltage period of the second scan signal SC2 and the first half of the high level voltage period of the third scan signal SC3 may overlap by one horizontal time 1HT.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Scan clock signal lines CL_SCCLK for delivering scan clock signals SCCLK to the gate driving panel circuit GPC may be disposed in the scan clock signal line area SCC.
Carry clock signal lines CL_CRCLK for delivering carry clock signals CRCLK to the gate driving panel circuit GPC may be disposed in the carry clock signal line area CRC.
The scan clock signal line area SCC may be located further away from the display area DA than the carry clock signal line area CRC. The carry clock signal line area CRC may be located closer to the display area DA than the scan clock signal line area SCC.
The scan clock signal line area SCC may be located further away from the gate drive panel circuit area GPCA than the carry clock signal line area CRC. The carry clock signal line area CRC may be located closer to the gate driving panel circuit area GPCA than the scan clock signal line area SCC.
Referring to
Referring to
Referring to
Each of the first gate high voltage line HVL1 and the second gate high voltage line HVL1 may have a greater width than the start signal line CSL1, the reset signal line CSL4, and the line selection signal line CSL5.
The first gate high voltage line HVL1, the second gate high voltage line HVL1, the start signal line CSL1, the reset signal line CSL4, and the line selection signal line CSL5 may be arranged in the first power line area PLA1 in various arrangement orders.
For example, as shown in the example of
Referring to
Referring to
Referring to
Referring to
The locations and shapes of circuit components (T7sc1, T7sc2, T6sc1, T6sc2, and the like) included in each of the two upper scan output buffers and the locations and shapes of circuit components (T7sc3, T7sc4, T6sc3, T6sc4, and the like) included in each of the two lower scan output buffers may be symmetrical to each other about the central area BDA.
Referring to
For example, the first scan output buffer SCBUF1 and the second scan output buffer SCBUF2 may be two upper scan output buffers disposed over the central area BDA, and the third scan output buffer SCBUF3 and the fourth scan output buffer SCBUF4 may be two lower scan output buffers disposed under the central area BDA.
For example, the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4) may have a symmetrical structure about the central area BDA. That is, the locations and shapes of circuit components included in each of the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4) may be symmetrical about the central area BDA.
For example, the two upper scan output buffers (SCBUF1 and SCBUF2) may have a left-right symmetrical structure. The two lower scan output buffers (SCBUF3 and SCBUF4) may have a left-right symmetrical structure.
Referring to
For example, the plurality of clock signal lines CL may include a plurality of scan clock signal lines CL_SCCLK and a plurality of carry clock signal lines CL_CRCLK.
Since each of the plurality of scan clock signal lines CL_SCCLK and the plurality of carry clock signal lines CL_CRCLK is desired to reduce load for gate driving, therefore, these lines may have a multilayer line structure.
The scan clock signal SCCLK may be more sensitive to signal delay or signal waveform changes in terms of driving than the carry clock signal CRCLK. Therefore, in order to reduce the load of the plurality of scan clock signal lines CL_SCCLK, a line width of each of the plurality of scan clock signal lines CL_SCCLK may be designed to be greater than a line width of each of the plurality of carry clock signal lines CL_CRCLK.
Referring to
Referring to
For example, the at least one gate high voltage line HVL may include a first gate high voltage line HVL1 for delivering a first gate high voltage GVDD to the first gate driving panel circuit GPC #1, a second gate high voltage line HVL2 for delivering a second gate high voltage GVDD_o to the first gate driving panel circuit GPC #1, and a third gate high voltage line HVL3 for delivering a third gate high voltage GVDD2 to the first gate driving panel circuit GPC #1.
The first gate high voltage line HVL1 may be a first gate high voltage node HV1 or may be electrically connected to the first gate high voltage node HV1. The second gate high voltage line HVL2 may be a second gate high voltage node HV2 or may be electrically connected to the second gate high voltage node HV2. The third gate high voltage line HVL3 may be a third gate high voltage node HV3 or may be electrically connected to the third gate high voltage node HV3.
The first gate high voltage GVDD, the second gate high voltage GVDD_o, and the third gate high voltage GVDD2 can be supplied to the first logic block LOGIC #1 included in the first gate driving panel circuit GPC #1.
Among the first gate high voltage GVDD, the second gate high voltage GVDD_o, and the third gate high voltage GVDD2, the first gate high voltage GVDD can be supplied to the first real-time sensing control block RT #1 included in the first gate driving panel circuit GPC #1.
Referring to
For example, the at least one gate low voltage line LVL may include a first gate low voltage line LVL1 for delivering a first gate low voltage GVSS0 to the first gate driving panel circuit GPC #1, a second gate low voltage line LVL2 for delivering a second gate low voltage GVSS1 to the first gate driving panel circuit GPC #1, and a third gate low voltage line LVL3 for delivering a third gate low voltage GVSS2 to the first gate driving panel circuit GPC #1.
The first gate low voltage line LVL1 may be a first gate low voltage node LV1 or may be electrically connected to the first gate low voltage node LV1. The second gate low voltage line LVL2 may be a second gate low voltage node LV2 or may be electrically connected to the second gate low voltage node LV2. The third gate low voltage line LVL3 may be a third gate low voltage node LV3 or may be electrically connected to the third gate low voltage node LV3.
Referring to
The first gate low voltage GVSS0 can be applied to drain nodes or source nodes of first to fourth scan pull-down transistors (T7sc1, T7sc2, T7sc3, and T7sc4) respectively included in the first to fourth scan output buffers (SCBUF1, SCBUF2, SCBUF3, and SCBUF4).
To implement this, referring to
Referring to
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The first gate low voltage connection line LVL1_CP may run through the central area BDA located between the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4).
Referring to
The second gate low voltage GVSS1 can be applied to the drain node or source node of a first inverter control transistor T4q included in the first logic block LOGIC #1.
To implement this, for connecting the drain node or source node of the first inverter control transistor T4q included in the first logic block LOGIC #1 to the second gate low voltage line LVL2, a second gate low voltage connection line LVL2_CP may be disposed such that the second gate low voltage connection line LVL2_CP extends in the row direction.
The second gate low voltage connection line LVL2_CP may run through the central area BDA located between the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4).
Referring to
The third gate low potential voltage GVSS2 can be applied to the drain nodes or source nodes of holding transistors (Holding TFT) included in the first logic block LOGIC #1 and connected to the third gate low voltage node LV3. The holding transistors (Holding TFT) may include a second Q node discharging transistor T3na, a fourth Q node discharging transistor T3nc, a second stabilization transistor T3a, a second QB node discharging transistor T5q, a first QB node discharging transistor T5, and a fourth QB node discharging transistor T5b.
Further, the third gate low voltage GVSS2 can be applied to the drain node or source node of a carry pull-down transistor T7cr included in the carry output buffer CRBUF of the first output buffer block BUF #1.
To implement this, for connecting the drain nodes or source nodes of the holding transistors (Holding TFT) included in the first logic block LOGIC #1 and connected to the third gate low voltage node LV3 to the third gate low voltage line LVL3, a third gate low voltage connection line LVL3_CP may be disposed such that the third gate low voltage connection line LVL3_CP extends in the row direction.
The third gate low voltage connection line LVL3_CP may also connect the drain node or source node of the carry pull-down transistor T7cr included in the carry output buffer CRBUF of the first output buffer block BUF #1 to the third gate low voltage line LVL3.
The third gate low voltage connection line LVL3_CP may run through the central area BDA located between the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4).
As described above, since the two upper scan output buffers (SCBUF1 and SCBUF2) and the two lower scan output buffers (SCBUF3 and SCBUF4) included in the first output buffer block BUF #1 has a symmetrical structure about the central area BDA, therefore, the gate low voltages (GVSS0, GVSS1, and GVSS2) can be efficiently delivered (supplied).
Hereinafter, the usage and structure of the first, second, and third gate high voltage lines (HVL1, HVL2, and HVL3) will be discussed, and the usage and structure of the first, second, and third gate low voltage lines (LVL1, LVL2, and LVL3) will be discussed.
The first gate high voltage GVDD carried through the first gate high voltage line HVL1 may be a high voltage used to cause the Q node to charge by being supplied to a Q node charging block of the input and reset blocks IR. For example, the first gate high voltage GVDD carried through the first gate high voltage line HVL1 may be a high voltage used to cause the Q node to charge by being applied to the drain node or source node of a first Q node charging transistor T1.
Further, the first gate high voltage GVDD carried through the first gate high voltage line HVL1 may be a high voltage used to cause the Q node to charge by being supplied to the real-time sensing control block RT #1 during a real-time sensing driving period.
The second gate high voltage GVDD_o carried through the second gate high voltage line HVL2 may be a high voltage used to cause the QB node to charge by being supplied to the inverter block IVT.
The third gate high voltage GVDD2 carried through the third gate high voltage line HVL3 can be applied to the drain node (or source node) and the gate node of a first Q node charging control transistor T11, and be applied to a Q node charging control node Nqc through the first Q node charging control transistor T11. The first Q node charging control transistor T11 can serve to compensate for a negative threshold voltage of the first Q node charging transistor T1.
The first gate low voltage GVSS0 carried through the first gate low voltage line LVL1 can be supplied to the first to fourth scan output buffers (SCBUF1 to SCBUF4) of the first output buffer block BUF #1. Thereby, the first gate low voltage GVSS0 can cause voltage levels of first to fourth scan signals (SC1 to SC4) to have a turn-off voltage level, and in turn, turn off driving for the first to fourth scan signal lines (SCL1 to SCL4).
The second gate low voltage GVSS1 carried through the second gate low voltage line LVL2 may be a low voltage applied to the drain node or source node of the first inverter control transistor T4q included in the inverter block IVT.
The second gate low voltage GVSS1 may be configured as a separate low voltage separate from the third gate low voltage GVSS2.
The third gate low voltage GVSS2 carried through the third gate low voltage line LVL3 may be a low voltage used to cause the Q node to discharge (or turn off) and the QB node to discharge (or turn off) by being supplied to the first logic block LOGIC #1.
The third gate low voltage GVSS2 carried through the third gate low voltage line LVL3 may be a power supply voltage supplied to the largest number of transistors.
Each of the first gate high voltage line HVL1, the second gate high voltage line HVL2, the first gate low voltage line LVL1, the second gate low voltage line LVL2, and the third gate low voltage line LVL3 may be desired to have a smaller line resistance and thereby have a multilayer structure because the first gate high voltage GVDD, the second gate high voltage GVDD_o, the first gate low voltage GVSS0, the second gate low voltage GVSS1, and the third gate low voltage GVSS2 directly affect the output of the first gate driving panel circuit GPC #1.
The first Q node charging control transistor T11 connected to the third gate high voltage line HVL3 may not require a relatively high voltage. Further, one or more lines may intersect, and overlap with, the third gate high voltage line HVL3. Considering these issues, the third gate high voltage line HVL3 may have a single-layer line structure.
The structure in the gate bezel area GBA described with reference to
Hereinafter, the multilayer line structure of the plurality of clock signal lines CL will be described with reference to
Referring to
Referring to
The first metal clock signal line MCL1 may be disposed in a first metal layer, which is a metal layer between a substrate SUB and an insulating layer INS on the substrate SUB.
The second metal clock signal line MCL2 may be disposed in a second metal layer, which is a metal layer between the insulating layer INS and a protective layer PAS on the insulating layer INS.
For example, the insulating layer INS may include a buffer layer and a gate insulating layer.
The second metal clock signal line MCL2 may be connected to the first metal clock signal line MCL1 through a contact hole in the insulating layer INS.
For example, a light shield may be located under an active layer (channel) of a driving transistor DRT disposed in the display area DA and may overlap with the channel of the driving transistor DRT. The insulating layer (e.g., the buffer layer) may be disposed between the channel of the driving transistor DRT and the light shield. The light shield may be formed from a first metal (e.g., a light shield metal). That is, the first metal layer may be a metal layer in which the light shield is disposed.
One of two or more capacitor electrodes constituting a storage capacitor Cst formed in the display area DA may be formed from the first metal (the light shield metal). That is, the first metal layer may be a metal layer in which one of two or more capacitor electrodes constituting the storage capacitor Cst is disposed.
In another example, the source and drain electrode of the transistor may be formed from a first metal (e.g., a source-drain metal). That is, the first metal layer may be a metal layer in which the source and drain electrodes of the transistor are disposed.
For example, a scan signal line SCL and a sensing signal line SENL may be formed from a second metal (e.g., a gate metal). That is, the second metal layer may be a metal layer in which the scan signal line SCL and the sensing signal line SENL are disposed. The second metal layer may be a metal layer in which the other one or another one of two or more capacitor electrodes constituting the storage capacitor Cst formed in the display area DA is disposed.
At least one multilayer power line MPL having a multilayer line structure may be disposed in the gate bezel area GBA.
The multilayer power line MPL may include a first metal power line MVL1 and a second metal power line MVL2. The first metal power line MVL1 and the second metal power line MVL2 may be located in different layers and may be electrically connected to each other.
The first metal power line MVL1 may be disposed in a first metal layer between a substrate SUB and an insulating layer INS on the substrate SUB. The second metal power line MVL2 may be disposed in a second metal layer between the insulating layer INS and a protective layer PAS on the insulating layer INS. For example, the insulating layer INS may include a buffer layer and a gate insulating layer.
The second metal power line MVL2 may be connected to the first metal power line MVL1 through a contact hole in the insulating layer INS.
For example, the first metal layer may be a metal layer in which a light shield located under the channel of a driving transistor DRT formed in the display area DA is disposed. The first metal layer may be a metal layer in which one of two or more capacitor electrodes constituting a storage capacitor Cst formed in the display area DA is disposed.
In another example, the first metal layer may be a metal layer constituting the source and drain electrode of the transistor.
For example, the second metal layer may be a metal layer in which a scan signal line SCL and a sensing signal line SENL are disposed. The second metal layer may be a metal layer in which the other one or another one of two or more capacitor electrodes constituting the storage capacitor Cst formed in the display area DA is disposed.
For example, the multilayer power line MPL having the multilayer line structure may include the first gate high voltage line HVL1, the second gate high voltage line HVL2, the first gate low voltage line LVL1, the second gate low voltage line LVL2, and the third gate low voltage line LVL3.
At least one single-layer power line SPL having a single-layer line structure may be disposed in the gate bezel area GBA.
The single-layer power line SPL may be disposed in a first metal layer between a substrate SUB and an insulating layer INS on the substrate SUB. For example, the insulating layer INS may include a buffer layer and a gate insulating layer.
For example, the first metal layer may be a metal layer in which a light shield located under the channel of a driving transistor DRT formed in the display area DA is disposed. The first metal layer may be a metal layer in which one of two or more capacitor electrodes constituting a storage capacitor Cst formed in the display area DA is disposed.
In another example, the first metal layer may be a metal layer constituting the source and drain electrode of the transistor.
For example, the single-layer power line SPL having the single-layer line structure may include the third gate high voltage line HVL3.
Referring to
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For example, the at least one trench TRC may be formed in at least one of a first area between the gate driving panel circuit area GPCA and the second power line area PLA2 and a second area between the second power line area PLA2 and the display area DA.
For example, a first trench TRC may be located in the first area between the gate driving panel circuit area GPCA and the second power line area PLA2. That is, the overcoat layer OC may be disposed in each of the gate driving panel circuit area GPCA and the second power line area PLA2, and an area (i.e., the first area) between the gate driving panel circuit area GPCA and the second power line area PLA2, in which the overcoat layer is not disposed, may correspond to the first trench TRC.
For example, a second trench TRC may additionally located in the second area between the second power line area PLA2 and the display area DA. That is, the overcoat layer OC may be disposed in each of the second power line area PLA2 and the display area DA, and an area (i.e., the second area) between the second power line area PLA2 and the display area DA, in which the overcoat layer is not disposed, may correspond to the second trench TRC.
As the display panel 110 has the above-described trench structure, the penetration of moisture H20 into an emission layer EL can be prevented.
Referring to
In the gate bezel area GBA, an insulating layer INS may be disposed such that the insulating layer INS covers the light shield LS.
In the second power line area PLA2 of the gate bezel area GBA, a gate material layer GATE may be disposed on the insulating layer INS and overlap with the light shield LS.
In a gate driving panel circuit area GPCA of the gate bezel area GBA, an overcoat layer OC may be disposed on the insulating layer INS.
In the second power line area PLA2 of the gate bezel area GBA, the overcoat layer OC may be disposed such that the overcoat layer OC covers the gate material layer GATE on the insulating layer INS.
In the gate driving panel circuit area GPCA and the second power line area PLA2 of the gate bezel area GBA, a bank BNK may be disposed on the overcoat layer OC.
In the gate bezel area GBA, a trench TRC may be formed in an area between the gate driving panel circuit area GPCA and the second power line area PLA2, in which the overcoat layer OC and the bank BNK are not present (or removed).
In the gate bezel area GBA, an additional trench TRC may be formed in an area between the second power line area PLA2 and the display area DA, in which the overcoat layer OC and the bank BNK are not present (or removed).
Meanwhile, in the display area DA, an emission layer EL may be disposed under a cathode electrode CAT, and a subpixel section SPU may be located under the emission layer EL. The subpixel section SPU may include an anode electrode AE, transistors (DRT, SCT, SENT, and the like), and a storage capacitor Cst. The emission layer EL may extend to the gate bezel area GBA of the non-display area NDA.
For example, the emission layer EL may extend from the display area DA to the non-display area NDA and extend to an upper portion of the bank BNK in the second power line area PLA2 via the trench TRC.
In the display area DA, the cathode electrode CAT may be disposed on the emission layer EL. The cathode electrode CAT may extend to the gate bezel area GBA of the non-display area NDA. Accordingly, the cathode electrode CAT may extend from the display area DA to all or a portion of the gate driving panel circuit area GPCA.
The cathode electrode CAT may be disposed in an area in which the trench TRC between the gate driving panel circuit area GPCA and the second power line area PLA2 is present, and disposed in an area in which the trench TRC between the second power line area PLA2 and the display area DA is present.
An encapsulation layer ENCAP may be disposed on the cathode electrode CAT. The encapsulation layer ENCAP may extend from the display area DA to a portion of the non-display area NDA.
The encapsulation layer ENCAP may include a first encapsulation layer ENCAP1 on the cathode electrode CAT and a second encapsulation layer ENCAP2 on the first encapsulation layer ENCAP1. For example, the first encapsulation layer ENCAP1 may include an adhesive and/or a moisture absorbent having an encapsulation function. The first encapsulation layer ENCAP1 may include an organic material. The second encapsulation layer ENCAP2 may include a metal or an inorganic material.
Referring to
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The dummy gate driving panel circuit (Dummy GPC) may have basically the same structure as the first or second type of gate driving panel circuit GPC. However, the dummy gate driving panel circuit (Dummy GPC) may not be connected to a gate line GL actually used to drive the display. For example, such a gate line GL may be a scan signal line SCL or a sensing signal line SENL.
The cross-sectional view of
Referring to
The display area DA and the non-display area NDA may be defined on the substrate SUB.
The gate driving panel circuit GPC may be disposed on the substrate SUB, disposed in a gate driving panel circuit area GPCA included in the gate bezel area GBA of the non-display area NDA of the substrate SUB, and configured to output a corresponding gate signal to each of a plurality of gate lines GL disposed in the display area DA.
For example, when the first type of gate driving panel circuit GPC is applied, the plurality of gate lines may include a plurality of scan signal lines SCL and a plurality of sensing signal lines SENL. In another example, when the second type of gate driving panel circuit GPC is applied, the plurality of gate lines may include a plurality of scan signal lines SCL.
The plurality of clock signal lines CL may be disposed on the substrate SUB, and disposed in a clock signal line area CLA located on a first side of the gate driving panel circuit area GPCA in the non-display area NDA of the substrate SUB. Each of the plurality of clock signal lines CL can deliver a corresponding clock signal to the gate driving panel circuit GPC.
For example, the clock signal line area CLA may be located further away from the display area DA than the gate driving panel circuit area GPCA. For example, the clock signal line area CLA may be located in a further outer edge of the substrate SUB than the gate driving panel circuit area GPCA.
For example, when the first type of gate driving panel circuit GPC is applied, the plurality of clock signal lines CL may include a plurality of carry clock signal lines CL_CRCLK, a plurality of scan clock signal lines CL_SCCLK, and a plurality of sensing clock signal lines CL_SECLK. In another example, when the second type of gate driving panel circuit GPC is applied, the plurality of clock signal lines CL may include a plurality of scan clock signal lines CL_SCCLK and a plurality of carry clock signal lines CL_CRCLK.
The overcoat layer OC may be disposed on the plurality of clock signal lines CL.
The overcoat layer OC may be disposed on the gate driving panel circuit GPC.
The cathode electrode CAT may be disposed in the display area DA and extend to the non-display area NDA.
The cathode electrode CAT may extend to the gate bezel area GBA of the non-display area NDA. For example, the cathode electrode CAT may extend to all or at least a portion of the gate driving panel circuit GPC such that the cathode electrode CAT is located on (or covers) all or at least a portion of the gate driving panel circuit GPC. According to this configuration, the cathode electrode CAT may overlap with all or at least a portion of the gate driving panel circuit GPC.
The cathode electrode CAT may extend to the gate bezel area GBA in the non-display area NDA. For example, the cathode electrode CAT may extend to all, or one or more, of the plurality of clock signal lines CL such that the cathode electrode CAT is located on (or covers) all, or one or more, of the plurality of clock signal lines CL. According to this configuration, the cathode electrode CAT may overlap with all, or one or more, of the plurality of clock signal lines CL.
A first power line area PLA1 may be disposed between the clock signal line area CLA and the gate driving panel circuit area GPCA, and a second power line area PLA2 may be disposed between the gate driving panel circuit area GPCA and the display area DA. It should be noted that, in
Referring to
A subpixel section SPU may be located under the emission layer EL. The subpixel section SPU may include an anode electrode AE, transistors (DRT, SCT, SENT, and the like), and a storage capacitor Cst.
Referring to
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The encapsulation layer ENCAP may include a first encapsulation layer ENCAP1 and a second encapsulation layer ENCAP2. For example, the first encapsulation layer ENCAP1 may include an adhesive and/or a moisture absorbent having an encapsulation function. The first encapsulation layer ENCAP1 may include an organic material. The second encapsulation layer ENCAP2 may include a metal or an inorganic material. The second encapsulation layer ENCAP2 may be disposed such that the second encapsulation layer ENCAP2 covers the cathode electrode CAT, the capping layer CPL, and the first encapsulation layer ENCAP1.
The encapsulation layer ENCAP may overlap with the plurality of clock signal lines CL and the gate driving panel circuit GPC.
Each of the emission layer EL, the cathode electrode CAT, and the capping layer CPL may have a slightly different size or edge position from each other depending on process errors during the manufacturing process of the display panel 110. For example, the cathode electrode CAT may not overlap with all of the plurality of clock signal lines CL disposed in the clock signal line area CLA. Depending on the process errors, a portion of the cathode electrode CAT may overlap with all or one or more of the plurality of clock signal lines CL disposed in the clock signal line area CLA.
Referring to
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A location at which the electrostatic discharge component ESD is disposed is not limited thereto. For example, one or more additional electrostatic discharge components ESD may be disposed in one or more other locations of the display device 100, in addition to the outer corner area shown in
Referring to
For example, the bank BNK may be disposed on the entire top surface, or over all, of the electrostatic discharge component ESD. The cathode electrode CAT may be disposed on the top surface of, or over, a portion of the electrostatic discharge component ESD.
Referring to
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The embodiments of the touch display device 100 according to aspects of the present disclosure described above can be briefly discussed as follows.
According to the embodiments described herein, a display device (e.g., the display device 100 of
In the display device according to the embodiments of the present disclosure, the first power line area and the second power line area may be separated by the gate driving panel circuit area.
The clock signal line area and the first power line area may be located on a first side of the gate driving panel circuit area. The first power line area may be located between the clock signal line area and the gate driving panel circuit area.
The second power line area may be located on a second opposing side of the gate driving panel circuit area. The second power line area may be located between the gate driving panel circuit area and the display area.
The clock signal line area may include a carry clock signal line area and a scan clock signal line area.
The plurality of clock signal lines may include a plurality of carry clock signal lines disposed in the carry clock signal line area and a plurality of scan clock signal lines disposed in the scan clock signal line area.
The scan clock signal line area may be located further away from the gate driving panel circuit area than the carry clock signal line area.
A line width of each of the plurality of scan clock signal lines may be greater than that of each of the plurality of carry clock signal lines.
The display device may further include at least one control signal line disposed in the first power line area and delivering at least one control signal to the gate driving panel circuit.
The gate driving panel circuit may include an output buffer block containing two or more scan output buffers configured to receive two or more scan clock signals and output two or more scan signals, and a logic block configured for control respective voltages of a Q node and a QB node electrically connected to the output buffer block.
The output buffer block may include a first scan output buffer configured to output a first scan signal to a first scan signal line connected to a first subpixel, and a second scan output buffer configured to output a second scan signal to a second scan signal line connected to a second subpixel.
The gate driving panel circuit may further include a real-time sensing control block configured to control the first scan output buffer so that the first scan signal can be output at a preset timing by the first scan output buffer during a first blank period.
During the first blank period, after the first scan signal having a turn-on level voltage is supplied to the first subpixel, a voltage of a reference voltage line connected to the first subpixel may increase.
An increasing rate of the voltage of the reference voltage line may vary depending on at least one characteristic value (e.g., mobility) of a driving transistor included in the first subpixel.
For example, the increasing rate of the voltage of the reference voltage line may be proportional to the mobility of the driving transistor included in the first subpixel.
Among the output buffer block, the logic block, and the real-time sensing control block, the real-time sensing control block may be located furthest away from the display area.
At least one carry signal line may be further disposed between the real-time sensing control block and the logic block. The carry signal line may be a signal line for delivering a carry signal.
The display panel of the display device may further include a central area for separating the first scan output buffer and the second scan output buffer, at least one first gate low voltage connection line for connecting a first gate low voltage line disposed in the second power line area to the first scan output buffer and the second scan output buffer, at least one second gate low voltage connection line for connecting a second gate low voltage line disposed in the second power line area to the logic block, and at least one third gate low voltage connection line for connecting a third gate low voltage line disposed in the second power line area to the logic block.
The first gate low voltage connection line, the second gate low voltage connection line, and the third gate low voltage connection line may run through the central area.
Among a plurality of subpixels disposed in the display panel, a first subpixel may include a light emitting element, a driving transistor for driving the light emitting element, a first transistor configured to control a connection between a data line and a first node of the driving transistor, a second transistor configured to control a connection between the reference voltage line and a second node of the driving transistor, and a storage capacitor between the first node and the second node.
In the first subpixel, the gate node of the first transistor and the gate node of the second transistor may be electrically connected to the first scan signal line.
A plurality of gate high voltage lines may be disposed in the first power line area, and a plurality of gate low voltage lines may be disposed in the second power line area.
All or one or more of the plurality of clock signal lines may be multi-layer lines. At least one of the plurality of gate high voltage lines may be a single-layer line and the remaining gate high voltage lines may be multi-layer lines. The plurality of gate low voltage lines may be multi-layer lines.
The display panel of the display device further includes an overcoat layer disposed in the non-display area and disposed on the gate driving panel circuit.
The overcoat layer may include at least one trench formed in at least one of a first area between the gate driving panel circuit area and the second power line area and a second area between the second power line area and the display area.
The display panel of the display device may further include a bank extending from the display area to the non-display area, an emission layer extending from the display area to the non-display area, a cathode electrode extending from the display area to the non-display area and located on the emission layer, and an electrostatic discharge component disposed in an outer corner area of the non-display area.
The electrostatic discharge component may not overlap with the emission layer, a portion of the electrostatic discharge component may overlap with the cathode electrode, and the electrostatic discharge component may overlap with the bank.
The plurality of clock signal lines may be disposed along one or more outer corners of the substrate, all or one or more of the plurality of clock signal lines do not overlap with the electrostatic discharge component, and all or one or more of the plurality of clock signal lines may overlap with the cathode electrode.
According to the embodiments described herein, a display panel can be provided, comprising: a gate driving panel circuit disposed in a gate driving panel circuit area in a substrate and configured to supply a plurality of scan signals through a plurality of scan signal lines; a plurality of clock signal lines disposed in a clock signal line area in the substrate and delivering a plurality of clock signals to the gate driving panel circuit; at least one gate high voltage line disposed in a first power line area in the substrate and delivering at least one gate high voltage to the gate driving panel circuit; and at least one gate low voltage line disposed in a second power line area in the substrate and delivering at least one gate low voltage to the gate driving panel circuit.
The first power line area and the second power line area may be separated by the gate driving panel circuit area.
According to the embodiments described herein, a gate driving panel circuit can be provided that is disposed in a gate driving panel circuit area in a substrate and configured to supply a plurality of scan signals through a plurality of scan signal lines, the gate driving panel circuit comprising: an output buffer block comprising two or more scan output buffers configured to receive two or more scan clock signals and output two or more scan signals; and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block.
The output buffer block may comprise: a first scan output buffer configured to output a first scan signal to a first scan signal line connected to a first subpixel; and a second scan output buffer configured to output a second scan signal to a second scan signal line connected to a second subpixel.
The gate driving panel circuit may further comprise a real-time sensing control block configured to control the first scan output buffer so that the first scan signal is output at a preset timing by the first scan output buffer during a first blank period.
According to the embodiments described herein, a gate driving panel circuit may be provided that has a structure suitable for a gate-in-panel (GIP) type, and a display device may be provided that includes the gate driving panel circuit.
According to the embodiments described herein, a gate driving panel circuit may be provided that is suitable for driving gate lines connected to subpixels having a structure capable of allowing sensing to be performed, and a display device may be provided that includes the gate driving panel circuit.
According to the embodiments described herein, a display device may be provided that has a wiring structure for stably supplying various types of signals or power to a gate driving panel circuit disposed in a display panel.
According to the embodiments described herein, since a display panel and a display device are designed to include a gate driving panel circuit disposed on a substrate of the display panel and formed during the manufacturing process of the display panel or the display device, advantage of enabling process optimization of the display panel and the display device can be provided.
The embodiments of the present disclosure described above have been described for illustrative purposes; those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed herein including the accompanying claims. Although the exemplary embodiments have been described for illustrative purposes, a person skilled in the art will appreciate that various modifications and applications are possible without departing from the essential characteristics of the present disclosure. For example, the specific components of the exemplary embodiments may be variously modified.
In the description herein, the term “exemplary embodiment” refers to an example embodiment, and does not mean that the example embodiment is preferred or the best embodiment.
The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various embodiments to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0027318 | Feb 2023 | KR | national |
