Patent Application
20250029561
The present application relates to the field of display technologies, and more particularly to a gate driving module and a display panel.
An Organic Light Emitting Diode (OLED) display panel is widely used because of its feature such as flexibility.
A gate driving circuit in the OLED display panel generally outputs valid pulses stage by stage to sequentially turn on multiple rows of sub-pixels, and a refresh rate of an entire display area of the display panel is the same. Therefore, it is impossible to drive different areas with different refresh rates, resulting in limited use scenarios.
The present application provides a gate driving module and a display panel to implement driving of the different areas with the different refresh rates.
The present application provides a gate driving module, including a frequency division control line and a plurality of cascaded gate driving circuits, where the frequency division control line is configured to transmit a frequency division control signal to the plurality of cascaded gate driving circuits, and each of the gate driving circuits includes:
The present application provides a gate driving module and a display panel. By disposing the frequency division control unit electrically connected between the gate control unit and the output unit and for controlling the signal from one of the first node and the second node according to the frequency division control signal to control the output unit to output the current-stage gate control signal, the plurality of gate control signals respectively generated by the plurality of gate driving circuits are controlled when the gate driving module is applied to the display panel to further control light emitting conditions of a plurality of rows of sub-pixels, so that the plurality of rows of sub-pixels are controlled in different frames to be in different light emitting conditions, resulting in different number of frames in a plurality of frames in which sub-pixels in different areas emit light or do not emit light. That is, driving of the display panel in a frequency division manner can be implemented.
In order to more clearly illustrate the technical solutions in embodiments of the present application, the accompanying drawings depicted in the description of the embodiments will be briefly described below. It will be apparent that the accompanying drawings in the following description are merely some embodiments of the present application, and other drawings may be obtained from these drawings without creative effort by those skilled in the art.
Technical solutions in embodiments of the present application will be clearly and completely described below in conjunction with drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.
In the description of the present application, the term “first”, “second”, or the like are for illustrative purposes only and are not to be construed as indicating or imposing a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature that limited by “first”, “second” may expressly or implicitly include at least one of the features. A source and a drain of the transistor are not distinguished herein, and they can be interchanged. In addition, it should be noted that the drawings provide a structure which is relatively close to the present application and omits some details which are not very relevant to the application, so as to simplify the drawings and make the application point clear, rather than indicating that the apparatus in practice is the same as that in the drawings and is not intended to be a limitation of the apparatus in practice.
Referring to “embodiments” in this specification means that specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase “embodiments” appearing at various respective locations in the specification does not necessarily refer to a same embodiment, or is an independent or alternative embodiment that is mutually exclusive from another embodiment. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described in this specification may be combined with other embodiments.
The present application provides a gate driving circuit, including but not limited to the following embodiments and a combination of the following embodiments.
In an embodiment, as shown in
Specifically, an example in which n (where n≥2) gate driving circuits 101 are connected in cascade in
It can be understood in the present embodiment that the frequency division control unit 13 is electrically connected between the gate control unit 11 and the output unit 12, and can control the signal from one of the first node P and the second node Q according to the frequency division control signal FD. That is, a signal transmitted to the output unit 12 can be controlled on the basis of the signal from another one of the first node P and the second node Q electrically connected to the output unit 12 being unchanged, thereby controlling a specific case of the gate control signal output from the output unit 12. As such, when the gate driving module 10 is applied to the display panel, light emitting conditions of a plurality of rows of sub-pixels Pi can be further controlled by controlling a plurality of gate control signals Scan respectively generated by a plurality of gate driving circuits 101, so that the plurality of rows of sub-pixels Pi are further controlled in different frames to be in different light emitting conditions, resulting in different number of frames in a plurality of frames in which sub-pixels Pi in different areas emit light or do not emit light. That is, driving of the display panel in a frequency division manner can be implemented by a same gate driving module 10.
In particular, the frequency division control unit 13 is electrically connected between the gate control unit 11 and the output unit 12 in the present application, and specific structures of the frequency division control unit 13, the gate control unit 11, and the output unit 12 are not limited herein. Regardless of the specific combination of the frequency division control unit 13, the gate control unit 11, and the output unit 12, it is possible to disable the gate control signal outputted from the current stage (that is, a next-stage stage transmission signal) if the signal for controlling one of the first node P and the second node Q from the gate driving circuit of the current stage is disabled (i.e., there is no valid pulse), and therefore the gate control signals of all subsequent stages starting from the next-stage are disabled, so that the influence of the frequency division control signal on the existence of “switching pulse” of the gate control signals from the current stage to the last stage is not considered when the frequency division control signal is transitioned in the current stage (seeing, for example, the gate control signals NScan(3) to NScan(6) in an Frame 2, the gate control signals NScan(5) to NScan(6) in an Frame 3, and NScan(3) to NScan(6) in an Frame 4 in a subsequent
In summary, in the present application, the above-mentioned problem of “switching pulse” does not exist. Therefore, the pulse width of the valid pulse output by the gate control signal may not be limited, and may be set to be large to sufficiently turn on the respective one of the sub-pixels.
An example in which only 8 stages of gate driving circuits are arranged continuously and every two stages of gate driving circuits correspond to the same refresh rate, and 4 frames are shown is taken in
In one embodiment, as shown in
Further, the gate control unit 11 may further include a thirteenth transistor T8 electrically connected to the first node P, where a source of the thirteenth transistor T8 is loaded with a first voltage VGH, a gate of the thirteenth transistor T8 is electrically connected to a node D, and a drain of the thirteenth transistor T8 is electrically connected to the first node.
In one embodiment, as shown in
Specifically, the first node P may control an ON condition of the first output transistor T10 to control whether the first voltage VGH can be transmitted to the signal output terminal OUT, and the second node Q may control an ON condition of the second output transistor T9 to control whether the second voltage VGL can be transmitted to the signal output terminal OUT. Further, as can be seen from the above discussion in the present application that a specific case of the gate control signal output from the signal output terminal OUT is controlled by setting the control transistor T17 connected between the third node R and the first node P to control whether the first node P or the second node Q can receive the signal from the third node R to control the ON condition of the first output transistor T10 and the ON condition of the second output transistor T9.
For example, when the first output transistor T10 is turned on and the second output transistor T9 is turned off, the gate control signal output from the signal output terminal OUT may be equal to the first voltage VGH. For another example, when the first output transistor T10 is turned off and the second output transistor T9 is turned on, the gate control signal output from the signal output terminal OUT may be equal to the second voltage VGL. For yet other example, when both the first output transistor T10 and the second output transistor T9 are turned off, the gate control signal output from the signal output terminal OUT may be equal to a previous voltage. For other example, when both the first output transistor T10 and the second output transistor T9 are turned on again, the gate control signal output from the signal output terminal OUT may be between the first voltage VGH and the second voltage VGL.
In one embodiment, the gate driving circuit 101 is electrically connected to one or more pixel driving circuits 202, the signal output terminal OUT is electrically connected to a gate of a pixel transistor in each of the pixel driving circuits 202, and the first voltage VGH is greater than the second voltage VGL. As shown in
The configuration of the pixel driving circuit 202 is not limited in the present embodiment, and it can be considered that the pixel transistor in the pixel driving circuit 202 can be controlled by the gate control signal output from the signal output terminal OUT of the gate driving circuit 101 to control a light emitting brightness of a light emitting device 201. Specifically, in the present embodiment in which the first voltage VGH is greater than the second voltage VGL, when the pixel transistor is the N-type transistor, the drain of the control transistor T17 is electrically connected to the first node P, so that the ON condition of the first output transistor T10 can be controlled to control whether a larger first voltage VGH (which is a valid voltage of the N-type transistor) can be transmitted to the gate of the N-type pixel transistor, thereby controlling whether the respective light emitting device 201 emits light; and when the pixel transistor is the P-type transistor, the drain of the control transistor T17 is electrically connected to the second node Q, so that the ON condition of the second output transistor T9 can be controlled to control whether a smaller second voltage VGL (which is a valid voltage of the P-type transistor) can be transmitted to the gate of the P-type pixel transistor, thereby controlling whether the corresponding light emitting device 201 emits light.
As can be seen from the above discussion that, if a valid voltage required to turn on the N-type or P-type pixel transistor has the same duration, it can be considered that, among the NScan signal and the PScan signal respectively output by the NScan circuit and the PScan circuit, a voltage value of the valid pulse of the NScan signal (such as but not limited to being equal to the first voltage VGH) is greater than that of the valid pulse of the PScan signal (such as but not limited to being equal to the second voltage VGL), and the valid pulses of the NScan and PScan signals can have the same pulse width.
Further, since the gate control unit 11 can receive the gate control signal generated by the upper stage of gate driving circuit 101, it can be seen from a stage transmission function of the gate control signal that a first start signal STV1 and a second start signal STV2 respectively loaded to the first stage of NScan circuit and the first stage of PScan circuit can be also obtained by translating the first stage of NScan signal (1) and the first stage of PScan signal (1) by equal distances in a negative direction of a time axis, that is, the voltage values of the valid pulses of the NScan and PScan signals can be equal to the first voltage VGH and the second voltage VGL, respectively. The first start signal STV1, the second start signal STV2, the NScan signal, and the PScan signal may all be periodic signals.
In one embodiment, as shown in
It should be noted that, for ease of description in the present application, an example in which the second output transistor T9 is located below the first output transistor T10 (i.e., the second node Q is located below the first node P) is taken only in the schematic diagram for illustration. In practice, a connection relationship among a plurality of electronic devices is protected by the present application and is not limited to a positional relationship. The gate control signal generated by the upper stage of gate driving circuit 101 is loaded on the basis of the input unit 114. As shown in
In one embodiment, as shown in
an operation of a signal in a portion of states is illustrated by taking an example in which the transistors in the gate driving circuit 101 are all P-type transistors in the present application. At the time of power-on, a control signal transmitted via the CL may control the fourth transistor T13 to be turned on to transmit the first voltage VGH to the second node Q. At the time of later outputting low voltages in both the first clock signal and the (i−1)-th stage of gate control signal NScan(i−1), the gate control signal NScan(i−1) controls both the seventh transistor T5 and the second output transistor T9 to be turned on, the second voltage VGL is transmitted to the signal output terminal OUT via the second output transistor T9, and the first clock signal controls the first transistor T4 to be turned on, and the second voltage VGL and the first clock signal both control the second transistor T6 to be turned on, and in this case, the high voltage in the second clock signal controls the third transistor T7 to be turned off. At the time of later outputting the high voltage in the first clock signal, the second transistor T6, the input transistor T3, and the first transistor T4 are turned off, and in this case, it may be considered that the second output transistor T9 maintains to be turned on, the low voltage in the second clock signal controls the third transistor T7 to be turned on, the third node R is not loaded with a voltage, and the signal output terminal OUT still outputs the second voltage VGL.
It should be noted that the present application does not limit the type of each of the transistors in the gate driving circuit 101. For example, each of the transistors may be a P-type transistor. Alternatively, a portion of the transistors may be an N-type transistor and the remaining of the transistors may be a P-type transistor. The signal may be correspondingly set according to the type of the transistors, and reference may be specifically made to the operation of “an example in which the transistors in the gate driving circuit 101 are all P-type transistors”
Further, the first node control unit 111 may further include an eighth transistor T11 and a second capacitor C2. The second node control unit 112 may further include a ninth transistor T12. The output unit 12 may further include a third capacitor C3 electrically connected between the gate and the source of the first output transistor T10. A gate of the eighth transistor T11 and a gate of the ninth transistor T12 may both be loaded with a second voltage VGL to maintain the eighth transistor T11 and the ninth transistor T12 to be turned on, a source and a drain of the eighth transistor T11 are electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, respectively, the second capacitor C2 is electrically connected between the gate and the drain of the second transistor T6, and the source and the drain of the ninth transistor T12 are electrically connected to the drain of the input transistor T3 and the second node Q, respectively.
Since the first capacitor C1, the second capacitor C2, and the third capacitor C3 maintain the voltage of the corresponding node and function as a coupling effect, the eighth transistor T11 and the ninth transistor T12 can be ensured to be turned on only when source voltages of both the eighth transistor T11 and the ninth transistor T12 are sufficiently low, so as to maintain the drains of the eighth transistor T11 and the ninth transistor T12 to have lower voltages respectively and facilitate turning on of both the first output transistor T10 and the second output transistor T9.
In one embodiment, as shown in
It should be understood that the second node control unit 112 in the embodiment may be further provided with the above-mentioned tenth transistor T14 and eleventh transistor T16. The second node Q is not directly electrically connected to the first capacitor C1 by the eleventh transistor T16 connected between the second node Q and the gate of the sixth transistor T2 while the tenth transistor T14 may be configured to control the voltage of the gate of the sixth transistor T2, so as to protect the second node Q from coupling of the first capacitor C1, and thus the second node Q may be maintained at a lower voltage.
It should be noted that, as can be seen from comparison of
Further, the gate driving circuit 101 in the present application may also be, but not limited to, an emission (EM) circuit, and the EM circuit and the NScan circuit differ in that the first start signal STV1 is replaced with a third start signal STV3, and it can be understood that the third start signal STV3 may be obtained by translating the first start signal STV1 by a distance in a negative direction or a positive direction of the time axis, and a waveform of the first start signal STV1 may not overlap that of the third start signal STV3. Similarly, the third start signal STV3 may also be a periodic signal.
The present application provides a display panel, including but not limited to following embodiments and a combination of the following embodiments.
In one embodiment, as shown in
An example in which the display panel 100 includes six gate driving modules 10 (GOA1, GOA2, two GOA3, GOA4, and GOA5, which are electrically connected to the corresponding sub-pixels Pi by the first scanning line EML1, the second scanning line NSL1, the third scanning line PSL, the fourth scanning line NSL2, and the fifth scanning line EML2, respectively) is taken in
It should be noted that a connection relationship among the plurality of gate driving circuits 101 in the same gate module and a connection relationship between each of the plurality of gate driving circuits 101 and each of the plurality of sub-pixels Pi are only illustrated in
Specifically, as shown in
The pixel driving circuit 202 may further include a reset transistor M4 and a compensation transistor M3, where a gate of the reset transistor M4 (e.g., the N-type transistor) may be electrically connected to the scanning line NSL1 to load the NScan1 signal, and the reset transistor M4 is configured to enable a reset signal VI1 to be transmitted to a gate of the driving transistor M1 for reset, a gate of the compensation transistor M3 (e.g., the N-type transistor) can be electrically connected to the fourth scanning line NSL2 to load the NScan2 signal, and a source and a drain of the compensation transistor M3 are electrically connected to a drain and a gate of the driving transistor M1 respectively.
The pixel driving circuit 202 may further include an initial transistor M7, where a gate of the initial transistor M7 (e.g., the P-type transistor) is electrically connected to the fifth scanning line EML2 to load the EM2 signal, a drain of the initial transistor M7 is electrically connected to one terminal of the light emitting device 201 (the other terminal of the light emitting device 201 may be loaded with the low voltage signal VSS), and the initial transistor M7 is configured to enable an initialization signal VI2 to be transmitted to one terminal of the light emitting device 201 for initialization.
The pixel driving circuit 202 further includes a reset transistor M8, where a gate of the reset transistor M8 (e.g., the P-type transistor) may be electrically connected to the fifth scanning line EML2 to load the EM2 signal, a drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1, and the reset transistor M8 is configured to enable a reset signal VI3 to be transmitted to the source of the driving transistor M1 to reset a potential of the driving transistor M1.
The pixel driving circuit 202 may further include a first light emitting control transistor M5 and a second light emitting control transistor M6, where a source of the first light emitting control transistor M5 is loaded with a first high voltage VDD, a drain of the first light emitting control transistor M5 is electrically connected to the source of the driving transistor M1, a source and a drain of the second light emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one terminal of the light emitting device 201, respectively, and the gates of both the first light emitting control transistor M5 and the second light emitting control transistor M6 (for example, both P-type transistors) are electrically connected to the first scanning line EML1 to load the EM1 signal, and both configured to control the light emitting timing of the light emitting device 201 according to the EM1 signal.
The pixel driving circuit 202 further includes a storage capacitor Cst connected in series between the source of the first light emitting control transistor M5 and the gate of the driving transistor M1.
The pixel driving circuit 202 further includes a boosting capacitor Cboost connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.
Based on the above discussion, as shown in
In the first reset phase tim1, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EM2 signal, and the compensation transistor M3 is turned on according to the corresponding NScan2 signal, so that an anode of the light emitting device 201 is reset in accordance with the initialization signal VI2, and an input terminal, an output terminal, a control terminal source (i.e., the source, the drain, and the gate) of the driving transistor M1 are reset according to the reset signal VI3.
In the second reset phase tim2, the reset transistor M4 is turned on according to the corresponding NScan1 signal, and the compensation transistor M3 is turned on according to the corresponding NScan2 signal, so that the gate and the drain of the driving transistor M1 are reset according to the initialization signal VI2.
In the data writing phase tim3, the data transistor M2 is turned on according to the corresponding PScan signal, and the compensation transistor M3 is turned on according to the corresponding NScan2 signal, so that the gate of the driving transistor M1 can write a data signal Vdata.
In the light emitting phase tim4, the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on according to the EM1 signal, so that the driving transistor M1 generates a driving current to drive the corresponding light emitting device 201 to emit light.
Further, the third reset phase tin may be included between the light emitting phase tim4 and the data writing phase tim3, where the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EM2 signal, so that the anode of the light emitting device 201 is reset according to the initialization signal VI2, and the source and drain of the drive transistor M1 are reset according to the reset signal VI3.
As can be seen from the above discussion that, since the normal light emission of each row of sub-pixels Pi is to be realized in the writing frame WF, each of the GOA1 to the GOA5 needs to output a corresponding valid pulse at a corresponding time period in the writing frame WF to control the corresponding transistor in the pixel driving circuit 202 to be turned on so as to realize a corresponding function of the pixel driving circuit 202. It can also be considered that, if at least one of the GOA1 to the GOA5 cannot output a corresponding valid pulse at a corresponding time period in the writing frame WF, the corresponding row of sub-pixels Pi cannot emit light. As shown in
Therefore, based on the pixel driving circuit 202 shown in
It should be noted in the present application that the gate control signal output from the signal output terminal OUT of the current stage of gate driving circuit 101 is loaded not only to the corresponding row of sub-pixels Pi of the current stage, but also to the lower stage of gate driving circuit 101. Therefore, if the third node R in the current stage of gate driving circuit 101 is not electrically connected to the first node P (for
In one embodiment, as shown in
As can be seen from the above discussion, the present application controls whether the output gate control signal has the valid pulse or not by disposing the frequency division control unit 13 electrically connected between the gate control unit 11 and the output unit 12 in the pixel driving circuit 202 for controlling the signal from one of the first node P and the second node Q according to the frequency division control signal, that is, by controlling whether one of the first node P and the second node Q is electrically connected to the gate control unit 11 (to obtain a signal from the third node R).
Further, among a plurality of continuous frames, it can be controlled in at least one of the preceding frames that all stages of gate control signals have valid pulses, and it can be controlled in at least one of the following frames that at least one of the preceding stages of gate control signals (corresponding to a plurality of first sub-pixels Pi1) have the valid pulses and the gate control signals from the subsequent stage to the last stage (corresponding to a plurality of second sub-pixels Pi2) do not have the valid pulses. That is, the plurality of first sub-pixels Pi1 emit light in more frames in the successive frames than the plurality of second sub-pixels Pi2, so that the first display area has a larger refresh rate than the second display area. Therefore, the display panel can realize a differential setting of refresh rates in different areas on the basis of setting one gate driving module 10, taking into account the cost and the frequency division function of the display panel.
Therefore, it can be seen from the above discussion that, in at least one frame (e.g., “at least one of the following frames” described above), the frequency division control signal is configured to control the gate control signal output by the first gate driving circuit 1011 to include a valid pulse to control that the corresponding light emitting device 201 emits light and configured to control the gate control signal output by the second gate driving circuit 1012 to be unable to include the valid pulse to control that the corresponding light emitting device 201 does not emit light.
Specifically, taking the NScan circuit shown in
In a first operation phase t1, the first clock signal XCK is set to be low, the second clock signal CK is set to be high, and the stage transmission signal NScan(i−1) is set to be low. The third transistor T7 is at an off state according to the second clock signal CK. All of the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the stage transmission signal NScan(i−1), which is set to be low, is transmitted to the node D, the second node Q, and the node F, so that all of the seventh transistor T5, the thirteenth transistor T8, the second output transistor T9, the sixth transistor T2, and the eleventh transistor T16 are turned on according to the NScan(i−1). The second voltage VGL is transmitted to the node C and the node B, the second clock signal CK, which is set to be high, is transmitted to the node E, and the first voltage VGH is transmitted to the node P (node R), so that both the second transistor T6 and the fifth transistor T1 are turned on according to the second voltage VGL. The second clock signal CK, which is set to be high, is transmitted to the node A, so that the second capacitor C2 is charged to a voltage difference between potentials of the node A and the node B. The first voltage VGH is transmitted to the node E (the potential of the node E may be between the first voltage VGH and the high potential of the second clock signal CK), so that the first capacitor C1 is charged to a voltage difference between potentials of the node E and the node F. The first capacitor C1 is charged so that the potential of the node F is pulled up due to a coupling effect. Since the first output transistor T10 is turned off and the second output transistor T9 is turned on, the gate control signal NScan(i) is a low voltage.
In a second operation phase t2, the first clock signal XCK is set to be high, the second clock signal CK is set to be low, and the stage transmission signal NScan(i−1) is set to be low. The first transistor T4, the input transistor T3, and the tenth transistor T14 are at the off state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node F are maintained at previous voltages. The sixth transistor T2 is maintained to be at an on state, and the second clock signal CK, which is set to be low, is transmitted to the node E, and the potential of the node F is further pulled down by a falling coupling of the second clock signal CK to the first capacitor C1, so that the eleventh transistor T16 is maintained at the on state, and the potential of the node F is transmitted to the node D, but the potential of the node D is also pulled up by an increasing coupling of the first clock signal XCK transmitted via the first clock signal line CKL1 in the circuit layout. The eleventh transistor T16 is turned off, the potential of the second node Q can be prevented from changing with the potential of the node D due to the action of the ninth transistor T12, and the second output transistor T9 is maintained at the on state. The seventh transistor T5 is still maintained at the on state, and the first clock signal XCK, which is set to be high, is transmitted to both the node C and the node B, so that the fifth transistor T1 and the second transistor T6 are turned off. The thirteenth transistor T8 is turned on according to the potential of the node D, and the first voltage VGH is transmitted to the first node P (node R) so that the first output transistor T10 is turned off, while the third transistor T7 is turned on by the second clock signal CK that is set to be low. The first voltage VGH is further transmitted to the node A to charge the second capacitor C2 to a voltage difference between potentials of the node A and the node B. Since the first output transistor T10 is turned off and the second output transistor T9 is turned on, the gate control signal NScan(i) is the low voltage.
In a third operation phase t3, the first clock signal XCK is set to be low, the second clock signal CK is set to be high, and the stage transmission signal NScan(i−1) is set to be high. The third transistor T7 is at the off state according to the second clock signal CK. All of the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the stage transmission signal NScan(i−1), which is set to be high, is transmitted to the node D, the second node Q, the node F, and the gate of the seventh transistor T5, and the second voltage VGL is transmitted to both the node C and the node B. The second output transistor T9 is turned off, and the seventh transistor T5 is turned off according to the stage transmission signal NScan(i−1) that is set to be high. Both the fifth transistor T1 and the second transistor T6 are turned on according to the second voltage VGL, and the first voltage VGH is transmitted to the node E to charge the first capacitor C1 to a voltage difference between potentials of both the node E and the node F. The second clock signal CK is transmitted to the node A to charge the second capacitor C2 to a voltage difference equal to both the node A and the node B; The thirteenth transistor T8 is turned off according to the signal NScan(i−1) that is set to be high, and the first node P (node R) is maintained at a previous (high) voltage by the C3, so that the first output transistor T10 is turned off. Since the first output transistor T10 is turned off and the second output transistor T9 is turned off, that is, the signal output terminal OUT is suspended, the gate control signal NScan(i) is maintained to be the low voltage.
In a fourth operation phase t4, the first clock signal XCK is set to be high, the second clock signal CK is set to be low, and the stage transmission signal NScan(i−1) is set to be high. All of the input transistor T3, the first transistor T4, and the tenth transistor T14 are at the off state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node C are maintained at previous voltages. The seventh transistor T5 is turned off according to a previous high voltage, the second output transistor T9 is turned off according to a previous high voltage at the second node Q, the thirteenth transistor T8 is turned off according to a high voltage at the node D, both the fifth transistor T1 and the second transistor T6 are turned on according to a previous low voltage at the node C, and the sixth transistor T2 is turned off according to a previous high voltage at the node F. The first voltage VGH is transmitted to the node E via the fifth transistor T1, that is, the potential of the node E is substantially unchanged, and the potential of the node F may be substantially unchanged in combination with a coupling effect of the first capacitor C1. The second clock signal CK, which is set to be low, is transmitted to the node A via the second transistor T6, and the potential of the node B is reduced in combination with the coupling effect of the second capacitor C2. The third transistor T7 is turned on according to the second clock signal line CK, and the low voltage at the node A is transmitted to the node P (node R) via the third transistor T7, thereby turning on the first output transistor T10. Since the first output transistor T10 is turned on and the second output transistor T9 is turned off, the gate control signal NScan(i) is the high voltage.
In a fifth operation phase t5, the first clock signal XCK is set to be low, the second clock signal CK is set to be high, and the stage transmission signal NScan(i−1) is set to be low. The third transistor T7 is at the off state according to the second clock signal line CK. All of the first transistor T4, the input transistor T3, and the tenth transistor T14 are turned on according to the first clock signal XCK, and the stage transmission signal NScan(i−1), which is set to be low, is transmitted via the input transistor T3 to the node D, the second node Q, and the gate of the seventh transistor T5. The second output transistor T9 is turned on according to the low voltage at the second node Q, and the sixth transistor T2 is turned on according to a voltage at the node F so that the second clock signal line CK that is set to be high is transmitted to the node E to charge the first capacitor C1 to a voltage difference between potentials of both the node E and the node F. The seventh transistor T5 is turned on so that the first clock signal XCK that is set to be low is transmitted to both the node C and the node B, and the fifth transistor T1 is turned on according to the first clock signal XCK that is set to be low and the second voltage VGL. The first voltage VGH is transmitted via the fifth transistor T1 to the node E (the potential of the node E may be between the first voltage VGH and the high potential of the second clock signal CK), and the potential of the node E is almost unchanged based on the fact that the first voltage VGH and the high potential of the second clock signal CK are equal, and thus the potential of the node F is almost unchanged, and the eleventh transistor T16 is turned off, so that it is possible to avoid that the first capacitor C1 influences a descending speed of the potential of the second node Q. The second transistor T6 is turned on according to the low voltage at the node B so that the second clock signal CK that is set to be high is transmitted to the node A to charge the second capacitor C2 to a voltage difference between potentials of both the node A and the node B. The thirteenth transistor T8 is turned on according to the low voltage at the node D so that the first voltage VGH is transmitted to the first node P (node R), thereby turning off the first output transistor T10. Since the first output transistor T10 is turned off and the second output transistor T9 is turned on, the gate control signal NScan(i) is a low voltage.
In a sixth operation stage t6, the stage transmission signal NScan(i−1) is set to be low, and the first clock signal XCK and the second clock signal CK are alternately set to be low and set to be high, so that the potential of the node F is driven to be coupled downward. Each time the potential of the node F is coupled downward, the voltage at the node F is gradually reduced to be close to −16V, and the potential of the second node Q is gradually reduced to be close to −20V. In the first several periods after the seventh transistor T5 is turned on in the fifth stage, the potential of the node F is coupled downward, and the potential of the second node Q is greatly affected by the potential of the node F. In a later stage in which the eleventh transistor T16 is turned off, the potential of the second node Q is stabilized against being affected by the potential of the node F.
It should be noted that the gate driving circuit 101 provided in the present application may be, but not limited to, a 16T3C structure or a 13T3C structure (where the 16T3C is only illustrated in
As can be seen from the above discussion, in comparison with
Specifically, in the first operation phase t1, the transistor T8 is turned on, and the first voltage VGH is transmitted to the first node P so that the transistor T10 is turned off. In the second operation phase t2, the transistor T8 is turned on, and the first voltage VGH is transmitted to the first node P so that the transistor T10 is turned off. In the third operation phase t3, the transistor T8 is turned off and the first node P is maintained at the first voltage VGH so that the transistor T10 is turned off. In the fourth operation phase t4, the transistor T8 is turned off and the first node P is maintained at the first voltage VGH, so that the transistor T10 is turned off. In the fifth operation phase t5, the transistor T8 is turned on, and the first voltage VGH is transmitted to the first node P so that the transistor T10 is turned off. In the sixth operation phase t6, the transistor T8 is turned on, and the first voltage VGH is transmitted to the first node P so that the transistor T10 is turned off. Therefore, it can be considered that the transistor t10 is turned off at each of the stages, and the gate control signal is related to the on state of the transistor T9, which is shown as follows.
In the first operation phase t1, the transistor T9 is turned on, so that the gate control signal NScan(i) is the low voltage.
In the second operation phase t2, the transistor T9 is turned on, so that the gate control signal NScan(i) is the low voltage.
In the third operation phase t3, the transistor T9 is turned off, i.e., the signal output terminal OUT is suspended, so that the gate control signal NScan(i) is maintained at the low voltage.
In the fourth operation phase t4, the transistor T9 is turned off, i.e., the signal output terminal OUT is suspended, so that the gate control signal NScan(i) is maintained at the low voltage.
In the fifth operation phase t5, the transistor T9 is turned on, so that the gate control signal NScan(i) is the low voltage.
In the sixth operation phase t6, the transistor T9 is turned on, so that the gate control signal NScan(i) is the low voltage.
In summary, in a period in which the control transistor T17 is turned off (i.e., the control signal is at its higher voltage), the gate control signals NScan(i) are all low voltages. In a period in which the control transistor T17 is turned on (i.e., the control signal is at its lower voltage), the gate control signal may have a valid pulse pl (e.g., a high voltage pulse) in corresponding periods (e.g., the fourth operation phase t4 to the sixth operation phase t6 in
Specifically, as shown in
Further, as shown in
The frequency division control signal is the low voltage in the Frame 1 to enable the six control transistors T17 corresponding to the first stage to the sixth stage of gate driving circuits 101 to be turned on, so that the NScan(1) to NScan(6) have the valid pulse pl in the Frame 1.
The frequency division control signal is the low voltage before tf1 in the Frame 1 to enable the two control transistors T17 corresponding to the first stage to the second stage of gate driving circuits 101 to be turned on, so that the NScan(1) to NScan(2) have the valid pulse pl in the Frame 2. Then, the frequency division control signal is the high voltage after the tf1 to enable the four control transistors T17 corresponding to the third stage to the sixth stage of gate driving circuits 101 to be turned off, so that the NScan(3) to NScan(6) have no valid pulse pl in the Frame 2.
The frequency division control signal is the low voltage before tf2 in the Frame 3 to enable the four control transistors T17 corresponding to the first stage to the fourth stage of gate driving circuits 101 to be turned on, so that the NScan(1) to NScan(4) have the valid pulse pl in the Frame 3. Then, the frequency division control signal is the high voltage after the tf2 to enable the two control transistors T17 corresponding to the fifth stage to the sixth stage of gate driving circuits 101 to be turned off, so that the NScan(5) to NScan(6) have no valid pulse pl in the Frame 3.
The frequency division control signal is the low voltage before tf3 in the Frame 4 to enable the two control transistors T17 corresponding to the first stage to the second stage of gate driving circuits 101 to be turned on, so that the NScan(1) to NScan(2) have the valid pulse pl in the Frame 4. Then, the frequency division control signal is the high voltage after the tf3 to enable the fourth control transistors T17 corresponding to the third stage to the sixth stage of gate driving circuits 101 to be turned off, so that the NScan(3) to NScan(6) have no valid pulse pl in the Frame 4.
In summary, as discussed above with respect to
An example in which the display panel is only divided into three areas, each of the areas is correspondingly applied with two stages of gate control signals, and the refresh rates of the three areas may be a, (½)*a, (¼)*a, respectively is taken for ease of explanation herein. It should be understood by a person skilled in the art that the number of areas divided in the display panel and the number of rows of sub-pixels contained in each of the areas may be varied, and the respective refresh rates may be also adjusted. Only a difference degree of the refresh rates in the plurality of areas and a requirement for setting the number of frames are illustrated herein. If the refresh rate of each latter of the three areas is ⅓ of the refresh rate of its former, nine frames need to be illustrated, so that the refresh times of the three areas are presented in a three times relationship, that is, the three areas are refreshed nine times, three times, and one time, respectively, in the nine frames.
Further, based on m areas, m refresh rates can be expressed as a/(j1), a/(j2), up to a/(jm), where j1 to jm are all positive integers. The m refresh rates are all positive integers, and then the number of frames should be set to the least common multiple of the m numbers from j1 to jm.
Further, a plurality of gate driving circuits 101 are electrically connected to the same clock signal line (it may be considered that all odd stages of gate driving circuits 101 and the first clock signal lines CKL1 or the second clock signal lines CKL2 are connected in the same manner, and all even stages of gate driving circuits 101 and the first clock signal lines CKL1 or the second clock signal lines CKL2 are connected in the same manner, but a connection manner among the odd stages of gate driving circuits 101 and the first clock signal lines CKL1 or the second clock signal lines CKL2 is opposite to that among even stages of gate driving circuits 101 and the first clock signal lines CKL1 or the second clock signal lines CKL2) to load the same clock signal (the first clock signal lines CKL1 and the second clock signal lines CKL 2 are configured to transmit the first clock signal and the second clock signal, respectively). In at least one frame, the frequency division control signal controls each of the i-th stage of gate driving circuit 101 to (i+k)-th stage of gate driving circuit 101 cascaded sequentially, the third node R is disconnected from the first node P or the second node Q corresponding to the third node R (for example, a period in which the frequency division control signal is an invalid high potential in the Frame 2, the Frame 3, and the Frame 4 in
It should be understood that the (i+1)-th stage of gate driving circuit 101 to the (i+k)-th stage of gate driving circuit 101 herein may be understood as a plurality of cascaded second gate driving circuits 1012. An example of one stage of gate driving circuit 101 is taken and may have several configurations as follows.
In case 1, the voltage of the first clock signal is equal to the first voltage VGH (regardless of the setting of the second clock signal), the first clock signal controls the transistors T3, T14, and T4 to be turned off, the second node Q and the node D are maintained at the original (low) voltage, the transistor T8 are turned on at all times to transmit the first voltage VGH to the first node P to turn off the transistor T10, and the transistor T9 is turned on at all times to transmit the VGL to the signal output terminal OUT.
In case 2, the voltage of the first clock signal is equal to the second voltage VGL (regardless of the setting of the second clock signal), the first clock signal controls the transistors T3, T14, and T4 to be turned on, and since the stage transmission signal is always at the low voltage and transmitted to the second node Q and the node D, the transistor T8 is turned on at all times to transmit the first voltage VGH to the first node P to turn off the transistor T10, and T9 is turned on at all time to transmit the VGL to the signal output terminal OUT.
In case 3, the voltage of the second clock signal is equal to the first voltage VGH (regardless of the setting of the first clock signal), the transistor T7 is turned on, regardless of the setting of the first clock signal. That is, the first clock signal is a constant first voltage VGH or a constant second voltage VGL. Alternatively, the voltage of the first clock signal is alternately equal to the first voltage VGH or the second voltage VGL, i.e., the voltage of the first clock signal is equal to the first voltage VGH or the second voltage VGL for any of the periods, which may cause the transistor T10 to be turned off and the transistor T9 to be turned on at all times to transmit the VGL to the signal output terminal OUT in combination with the above discussion.
In summary, since the end of the valid pulse of the gate control signal output from the (i−1)-th stage of gate driving circuit ends, the valid pulse of the (i−1)-th stage of gate control signal has been output normally, and for each of the (i+1)-th stage of gate driving circuit 101 to the (i+k)-th stage of gate driving circuit 101, since the frequency division control signal controls one of the first nodes P to be disconnected from the third node R corresponding to the first node P and various stage transmission signals are low voltages, the output of the gate control signal is not affected even if at least one of the first clock signal and the second clock signal is set as a constant voltage signal. That is, the first stage gate control signal to the (i−1)-th stage gate control signal can output respective valid pulses respectively, and the (i+1)-th stage of gate control signal to the (i+k)-th stage of gate control signal can still output a constant low voltage signal. Since at least one of the first clock signal and the second clock signal is a constant voltage signal, power consumption of the gate driving module 10 can be effectively reduced.
Further, in order to design the clock control signal and minimize power consumption, the clock signals (the first clock signal and the second clock signal) corresponding to each of the i-th stage of gate driving circuit 101 to the (i+k)-th stage of gate driving circuit 101 cascaded sequentially may be set as constant voltage signals. Specifically, reference may be made to
The present application provides the gate driving module and the display panel. By disposing the frequency division control unit electrically connected between the gate control unit and the output unit and for controlling the signal from one of the first node and the second node according to the frequency division control signal to control the output unit to output the current-stage gate control signal, the plurality of gate control signals respectively generated by the plurality of gate driving circuits are controlled when the gate driving module is applied to the display panel to further control light emitting conditions of a plurality of rows of sub-pixels, so that the plurality of rows of sub-pixels are controlled in different frames to be in different light emitting conditions, resulting in different number of frames in a plurality of frames in which sub-pixels in different areas emit light or do not emit light. That is driving of the display panel in a frequency division manner can be implemented by the same gate driving module. That is, driving of the display panel in a frequency division manner can be implemented.
A specific example is used herein to describe a principle and an implementation of the present application. The description of the foregoing embodiments is merely used to help understand a method and a core idea of the present application. In addition, a person skilled in the art may make changes in a specific implementation manner and an application scope according to an idea of the present application. In conclusion, content of this specification should not be construed as a limitation on the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 20310669777.6 | Jun 2023 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/108321 | 7/20/2023 | WO |
