Patent Application
20250040124
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0098900 filed on Jul. 28, 2023, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
Example embodiments of the present disclosure relate to a gate structure and a semiconductor including the same.
As the integration degree of DRAM devices gradually increases, the volume of a gate structure included in the DRAM device may decrease, and the distance between neighboring gate structures may decrease. Accordingly, resistance of the gate structure may increase and interference between the neighboring gate structures may increase.
Example embodiments provide a gate structure having improved characteristics.
Example embodiments provide a semiconductor device having improved characteristics.
According to example embodiments, there is provided a gate structure. The gate structure may include a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.
According to example embodiments, there is provided a gate structure. The gate structure may include a gate electrode on a substrate, the gate electrode including a first conductive pattern and a second conductive pattern sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure contacting a sidewall of the second conductive pattern and an edge of an upper surface of the first conductive pattern, the spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate; a gate insulation pattern on a lower surface and a sidewall of the first conductive pattern and an outer sidewall of the spacer structure; and a gate mask contacting an upper surface of the second conductive pattern and an upper surface of the spacer structure, wherein the upper surface of the spacer structure is substantially coplanar with the upper surface of the second conductive pattern, and wherein the first spacer includes a high dielectric material or silicon nitride, and the second spacer includes lanthanum oxide (LaO), magnesium oxide (MgO) or strontium oxide (SrO).
According to example embodiments, there is provided a semiconductor device. The semiconductor device may include an active pattern on a substrate; an isolation pattern on a sidewall of the active pattern; a gate structure extending in a first direction substantially parallel to an upper surface of the substrate in upper portions of the active pattern and the isolation pattern; a bit line structure on a central portion of the active pattern, the bit line structure extending in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; a contact plug structure on each of opposite end portions of the active pattern; and a capacitor structure on the contact plug structure. The gate structure may include a gate electrode extending in the first direction, the gate electrode including a lower portion and an upper portion sequentially stacked in a third direction substantially perpendicular to the upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in the second direction on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.
In a semiconductor device according to example embodiments, a gate structure may include a spacer structure disposed between a gate electrode and a gate insulation pattern, and the spacer structure may be configured to induce a dipole at an interface with the gate insulation pattern to decrease flat band voltage (Vmb) of the gate structure. Accordingly, the gate structure may have improved refresh time characteristics, and Gate Induced Drain Leakage (GIDL) may also be reduced or prevented.
In addition, the gate electrode may contain a metal or a metal nitride instead of polysilicon doped with impurities, and thus, the gate electrode may have generally low resistance. Accordingly, the gate structure may be formed to have a relatively small diameter, and thus, interference or risk of electrical short between neighboring gate structures may be reduced.
The above and other aspects and features of the semiconductor devices and the methods of manufacturing the same in accordance with example embodiments will become readily understood from detail description that follows with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various directions, materials, layers, regions, pads, electrodes, patterns, structure and/or processes, these various materials, layers, regions, pads, electrodes, patterns, structure and/or processes should not be limited by these terms. These terms are only used to distinguish one direction, material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Thus, “first”, “second” and/or “third” may be used selectively or interchangeably for each direction, material, layer, region, electrode, pad, pattern, structure or process respectively.
Hereinafter, two directions among horizontal directions that are substantially parallel to an upper surface of a substrate 10 or a substrate 100, which may be substantially orthogonal to each other, may be referred as first and second directions D1 and D2, respectively, and a direction among the horizontal directions, which may have an acute angle with respect to each of the first and second directions D1 and D2, may be referred to as a third direction D3. Additionally, a direction substantially perpendicular to the upper surface of the substrate 10 or the substrate 100 may be referred to as a vertical direction.
Referring to
The substrate 10 may include silicon, germanium, silicon-germanium, and/or a III-V group compound semiconductor, such as GaP, GaAs, or GaSb. In example embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
The gate insulation pattern 15 may be disposed on a bottom and a sidewall of the first recess 5, and the gate electrode 70 and gate mask 80 may be sequentially stacked in the vertical direction on the gate insulation pattern 15 within the first recess 5.
The gate insulation pattern 15 may include, for example, an oxide, such as silicon oxide
The gate electrode may include a first conductive pattern 20 and a second conductive pattern 60 sequentially stacked in the vertical direction.
Each of the first and second conductive patterns 20 and 60 may include, for example, a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc., or a metal, such as tungsten (W), aluminum (Al), molybdenum (Mo), etc.
In one example embodiment, the first and second conductive patterns 20 and 60 may include substantially the same metal nitride or metal, and thus may be merged with each other to be integrally or monolithically formed. In another example embodiment, the first and second conductive patterns 20 and 60 may include different metal nitrides or metals from each other to be distinguished from each other, e.g., a boundary may be formed therebetween.
In some example embodiments, the first conductive pattern 20 or the second conductive pattern 60 may include a metal, for example, tungsten (W), aluminum (Al), molybdenum (Mo), etc. In this case, the gate electrode 70 may further include a barrier pattern at least partially covering a sidewall and/or a bottom of the metal. The barrier pattern may include a metal nitride, for example, titanium nitride, tantalum nitride, tungsten nitride, etc.
In example embodiments, an area of an upper surface of the first conductive pattern 20 may be greater than an area of a lower surface of the second conductive pattern 60.
The spacer structure 50 may be disposed between the gate insulation pattern 15 and the second conductive pattern 60, and may include a second spacer 45 and a first spacer 35 sequentially stacked in the second direction D2 on a sidewall of the second conductive pattern 60.
In example embodiments, the first spacer 35 may contact an inner sidewall of the gate insulation pattern 15 and an edge of the upper surface the first conductive pattern 20. A cross-section in the second direction D2 of the first spacer 35 may have a shape of an “L”. The second spacer 45 may contact an inner sidewall of the first spacer 35.
In example embodiments, the first spacer 35 may include a high dielectric material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, etc., or silicon nitride, and the second spacer 45 may include a material that induces a dipole, for example, lanthanum oxide, magnesium oxide, strontium oxide, etc.
The first and second spacers 35 and 45 may together be configured to induce a dipole at an interface of the first spacer 35 and the gate insulation pattern 15 to decrease a flat band voltage (Vfb) of the gate structure 90.
The gate mask 80 may include an insulating nitride, for example, silicon nitride.
If the gate electrode is composed of a first conductive pattern including a metal nitride and/or a metal, and a second conductive pattern including polysilicon doped with impurities that has a lower work function than that of the first conductive pattern, resistance of the second conductive pattern may be high, and thus, overall resistance of the gate electrode may be relatively high.
However, in the semiconductor device according to example embodiments, the gate electrode 70 may include the first and second conductive patterns 20 and 60, each of which includes a metal nitride and/or a metal, and thus, overall resistance of the gate electrode 70 may be relatively low. However, if the gate electrode 70 includes only a metal nitride and/or a metal and not include polysilicon doped with impurities having a low work function, refresh time may be deteriorated.
However, the gate structure 90 according to example embodiments may further include the spacer structure 50 disposed between the gate insulation pattern 15 and the gate electrode 70. The spacer structure 50 may lower the flat band voltage (Vfb) of the gate structure 90 by inducing a dipole at the interface with the gate insulation pattern 15. Accordingly, deterioration of the refresh time of the gate structure 90 may be reduced or prevented, and Gate Induced Drain Leakage (GIDL) may also be reduced or prevented.
In addition, the gate structure 90 may have a low resistance even if the gate structure 90 has a small diameter. Accordingly, the distance between the neighboring gate structures 90 may be sufficient, and thus, interference or electrical shorts therebetween may be reduced.
Referring to
A first conductive layer may be formed on the gate insulation pattern 15 and the substrate 10 to at least partially fill the first recess 5. An upper portion of the first conductive layer may be removed by, for example, performing an etch-back process to form a first conductive pattern 20 in a lower portion of the first recess 5. An upper surface of the first conductive pattern 20 may be lower than an upper surface of the substrate 10.
In example embodiments, the first conductive layer may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, and/or a physical vapor deposition (PVD) process.
Referring to
In example embodiments, each of the first and second spacer layers 30 and 40 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, and/or a physical vapor deposition (PVD) process.
Referring to
The first and second spacers 35 and 45 may together form a spacer structure 50. The first and second spacers 35 and 45 may be configured to induce a dipole at an interface of the first spacer 35 and the gate insulation pattern 15.
Referring again to
A gate mask layer may be formed on the second conductive pattern 60, the spacer structure 50, the gate insulation pattern 15 and the substrate 10 to at least partially fill a remaining portion of the first recess 5, and a planarization process may be performed on the gate mask layer until the upper surface of the substrate 10 is exposed to form a gate mask 80.
Accordingly, a gate structure 90 including the gate insulation pattern 15, the spacer structure 50 including the first and second spacers 35 and 45, the gate electrode 70 including the first and second conductive patterns 20 and 60, and a gate mask 80 may be formed.
The planarization process may include, for example, a chemical mechanical polishing (CMP) process and/or an etch-back process.
This semiconductor device may be an application of the gate structure 90 illustrated with reference to
Referring to
The semiconductor device may further include an isolation pattern 110, a spacer structure 465, a sixth spacer 490, a second capping pattern 485, first and second insulation pattern structures 235 and 590, fourth and fifth insulation patterns 410 and 420, and a metal silicide pattern 500.
The active pattern 105 may extend in the third direction D3, and a plurality of active patterns 105 may be spaced apart from each other in the first and second directions D1 and D2. A sidewall of the active pattern 105 may be at least partially covered by the isolation pattern 110. The active pattern 105 may include substantially the same material as the substrate 100, and the isolation pattern 110 may include an oxide, e.g., silicon oxide.
Referring to
In example embodiments, the gate structure 90 may extend in the first direction D1, and a plurality of gate structures 90 may be spaced apart from each other in the second direction D2.
Referring to
In example embodiments, an area of a bottom of the first opening 240 may be greater than an area of the upper surface of the active pattern 105. Thus, the first opening 240 may also at least partially expose an upper surface of a portion of the isolation pattern 110 adjacent to the active pattern 105. Additionally, the first opening 240 may extend through upper portions of the active pattern 105 and the portion of the isolation pattern 110 adjacent thereto, and thus the bottom of the first opening 240 may be lower than an upper surface of each of opposite edge portions in the third direction D3 of the active pattern 105 as shown in
The bit line structure 395 may include a third conductive pattern 255, a first barrier pattern 265, a fourth conductive pattern 275, a first mask 285, a first etch stop pattern 365 and a first capping pattern 385 sequentially stacked in the vertical direction on the first opening 240 or the first insulation pattern structure 235. The third conductive pattern 255, the first barrier pattern 265 and the fourth conductive pattern 275 may collectively form a conductive structure, and the first mask 285, the first etch stop pattern 365 and the first capping pattern 385 may collectively form an insulation structure.
The third conductive pattern 255 may include, e.g., doped polysilicon, the first barrier pattern 265 may include a metal nitride, e.g., titanium nitride, or a metal silicon nitride, e.g., titanium silicon nitride, the fourth conductive pattern 275 may include a metal, e.g., tungsten, and each of the first mask 285, the first etch stop pattern 365 and the first capping pattern 385 may include an insulating nitride, e.g., silicon nitride.
In example embodiments, the bit line structure 395 may extend in the second direction D2 on the substrate 100, and a plurality of bit line structures 395 may be spaced apart from each other in the first direction D1.
The fourth and fifth insulation patterns 410 and 420 may be formed in the first opening 240, and may contact a lower sidewall of the bit line structure 395. The fourth insulation pattern 410 may include an oxide, e.g., silicon oxide, and the fifth insulation pattern 420 may include an insulating nitride, e.g., silicon nitride.
The first insulation pattern structure 235 may be formed on the active pattern 105 and the isolation pattern 110 under the bit line structure 395, and may include first, second and third insulation patterns 205, 215 and 225 sequentially stacked in the vertical direction. The first and third insulation patterns 205 and 225 may include an oxide, e.g., silicon oxide, and the second insulation pattern 215 may include an insulating nitride, e.g., silicon nitride.
The contact plug structure may include a lower contact plug 475, a metal silicide pattern 500 and an upper contact plug 555 sequentially stacked in the vertical direction on the active pattern 105 and the isolation pattern 110.
The lower contact plug 475 may contact the upper surface of each of opposite edge portions in the third direction D3 of the active pattern 105. In example embodiments, a plurality of lower contact plugs 475 may be spaced apart from each other in the second direction D2, and a second capping pattern 485 may be formed between neighboring ones of the lower contact plugs 475 in the second direction D2. The second capping pattern 485 may include an insulating nitride, e.g., silicon nitride.
The lower contact plug 475 may include, e.g., doped polysilicon, the metal silicide pattern 500 may include, e.g., titanium silicide, cobalt silicide, nickel silicide, etc.
The upper contact plug 555 may include a second metal pattern 545 and a second barrier pattern 535 at least partially covering a lower surface of the second metal pattern 545. The second metal pattern 545 may include a metal, e.g., tungsten, and the second barrier pattern 535 may include a metal nitride, e.g., titanium nitride.
In example embodiments, a plurality of upper contact plugs 555 may be spaced apart from each other in the first and second directions D1 and D2, and may be arranged in a honeycomb pattern or a lattice pattern in a plan view. Each of the upper contact plugs 555 may have a shape of, e.g., a circle, an ellipse, or a polygon in a plan view.
The spacer structure 465 may include a third spacer 400 at least partially covering sidewalls of the bit line structure 395 and the third insulation pattern 225, an air spacer 435 on a lower outer sidewall of the third spacer 400, and a fifth spacer 450 on an outer sidewall of the air spacer 435, a sidewall of the first insulation pattern structure 235, and upper surfaces of the fourth and fifth insulation patterns 410 and 420.
Each of the third and fifth spacers 400 and 450 may include an insulating nitride, e.g., silicon nitride, and the air spacer 435 may include air.
The sixth spacer 490 may be formed on an outer sidewall of a portion of the third spacer 400 on an upper sidewall of the bit line structure 395, and may at least partially cover an upper end of the air spacer 435 and an upper surface of the fifth spacer 450. The sixth spacer 490 may include an insulating nitride, e.g., silicon nitride.
Referring to
The sixth and seventh insulation patterns 570 and 580 may include an insulating nitride, e.g., silicon nitride.
The second etch stop pattern 600 may be formed on the sixth and seventh insulation patterns 570 and 580, the upper contact plug 555 and the second capping pattern 485. The second etch stop pattern 600 may include, for example, an insulating nitride, e.g., silicon boronitride, silicon nitride, etc.
The capacitor 640 may include a lower electrode 610, a dielectric layer 620 and an upper electrode 630 that are sequentially stacked, and the lower electrode 610 may extend through the second etch stop pattern 600 to contact an upper surface of the upper contact plug 555. Each of the lower electrode 610 and the upper electrode 630 may include, e.g., a metal, a metal nitride, a metal silicide, polysilicon doped with impurities, etc., and the dielectric layer 620 may include a metal oxide, for example, hafnium oxide, zirconium oxide, etc.
This semiconductor device may be an application of the method of manufacturing the gate structure 90 illustrated with reference to
Referring to
As the isolation pattern 110 is formed on the substrate 100, an active pattern 105 of which a sidewall is at least partially covered by the isolation pattern 110 may be defined.
The active pattern 105 and the isolation pattern 110 on the substrate 100 may be partially etched to form a third recess extending in the first direction D1, and a gate structure 90 may be formed in the third recess. In example embodiments, the gate structure 90 may extend in the first direction D1, and a plurality of gate structures may be spaced apart from each other in the second direction D2.
Referring to
The insulating layer structure 230 may be patterned, and the active pattern 105, the isolation pattern 110, and the gate mask 80 included in the gate structure 90 may be partially etched using the patterned insulating layer structure 230 as an etching mask to form a first opening 240. In example embodiments, the insulating layer structure 230 may have a circular shape or an elliptical shape in a plan view, and a plurality of insulating layer structures 230 may be spaced apart from each other in the first and second direction D1 and D2. Each of the insulating layer structures 230 may overlap edge portions of ones of the active patterns 105 neighboring in the third direction D3, which may face each other, in a vertical direction substantially orthogonal to the upper surface of the substrate 100.
Referring to
Referring to
In example embodiments, the first capping pattern 385 may extend in the second direction D2, and a plurality of first capping patterns 385 may be spaced apart from each other in the first direction D1.
By the etching process, a third conductive pattern 255, a first barrier pattern 265, a fourth conductive pattern 275, a first mask 285, a first etch stop pattern 365 and the first capping pattern 385 may be formed on the first opening 240, and a third insulation pattern 225, the third conductive pattern 255, the first barrier pattern 265, the fourth conductive pattern 275, the first mask 285, the first etch stop pattern 365 and the first capping pattern 385 may be sequentially stacked on the second insulating layer 210 of the insulating layer structure 230 at an outside of the first opening 240.
Hereinafter, the third conductive pattern 255, the first barrier pattern 265, the fourth conductive pattern 275, the first mask 285, the first etch stop pattern 365 and the first capping pattern 385 sequentially stacked may be referred to as a bit line structure 395. The third conductive pattern 255, the first barrier pattern 265 and the fourth conductive pattern 275 may form a conductive structure, and the first mask 285, the first etch stop pattern 365 and the first capping pattern 385 may form an insulation structure. In example embodiments, the bit line structure 395 may extend in the second direction D2, and a plurality of bit line structures 395 may be spaced apart from each other in the first direction D1.
Referring to
The third spacer layer may also at least partially cover a sidewall of the third insulation pattern 225 under the bit line structure 395 on the second insulating layer 210, and the fifth insulating layer may at least partially fill a remaining portion of the first opening 240.
The fourth and fifth insulating layers may be etched by an etching process. In example embodiments, the etching process may be a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as an etchant, and portions of the fourth and fifth insulating layers except for portions thereof in the first opening 240 may be removed. Accordingly, most portion of a surface of the third spacer layer, that is, all portions of the surface of the third spacer layer except for a portion of the surface thereof in the first opening 240 may be at least partially exposed, and the fourth and fifth insulating layers remaining in the first opening 240 may form fourth and fifth insulation patterns 410 and 420, respectively.
A fourth spacer layer may be formed on the exposed surface of the fourth spacer layer and the fourth and fifth insulation patterns 410 and 420 in the first opening 240. The fourth spacer layer may be anisotropically etched to form a fourth spacer 430 at least partially covering a sidewall of the bit line structure 395 on the surface of the third spacer layer and on the fourth and fifth insulation patterns 410 and 420.
A dry etching process may be performed using the first capping pattern 385 and the fourth spacer 430 as an etching mask to form a second opening 440 at least partially exposing an upper surface of the active pattern 105, and upper surfaces of the isolation pattern 110 the gate mask 80 may also be at least partially exposed by the second opening 440.
By the dry etching process, portions of the third spacer layer on upper surfaces of the first capping pattern 385 and the second insulating layer 210 may be removed, and thus a third spacer 400 may be formed on the sidewall of the bit line structure 395. By the dry etching process, the first and second insulating layers 200 and 210 may be partially removed to remain as first and second insulation patterns 205 and 215, respectively, under the bit line structure 395. The first to third insulation patterns 205, 215 and 225 sequentially stacked under the bit line structure 395 may collectively form a first insulation pattern structure.
Referring to
The third to fifth spacers 400, 430 and 450 sequentially stacked on the sidewall of the bit line structure 395 in the horizontal direction may be referred to as a preliminary spacer structure 460.
A first sacrificial layer may be formed to at least partially fill the second opening 440 on the substrate 100 to a sufficient height, and an upper portion of the first sacrificial layer may be planarized until the upper surface of the first capping pattern 385 is exposed to form a first sacrificial pattern 480 in the second opening 440.
In example embodiments, the first sacrificial pattern 480 may extend in the second direction D2, and a plurality of first sacrificial patterns 480 may be spaced apart from each other in the first direction D1 by the bit line structures 395. The first sacrificial pattern 480 may include, for example, an oxide such as silicon oxide.
Referring to
In example embodiments, each of the third openings may overlap a region between the gate structures 90 in the vertical direction. By the etching process, a fourth opening exposing upper surfaces of the active pattern 105 and the isolation pattern 110 may be formed between the bit line structures 395 on the substrate 100.
The second mask may be removed, a lower contact plug layer may be formed to at least partially fill the fourth opening to a sufficient height, and an upper portion of the lower contact plug layer may be planarized until the upper surface of the first capping pattern 385 and upper surfaces of the first sacrificial pattern 480 and the preliminary spacer structure 460 are at least partially exposed. Thus, the lower contact plug layer may be transformed into a plurality of lower contact plugs 475 spaced apart from each other in the second direction D2 between the bit line structures 395. Additionally, the first sacrificial pattern 480 extending in the second direction D2 between the bit line structures 395 may be divided into a plurality of pieces in the second direction D2 by the lower contact plugs 475.
The first sacrificial pattern 480 may be removed to form a fifth opening, and a second capping pattern 485 may be formed to at least partially fill the fifth opening. In example embodiments, the second capping pattern 485 may overlap the gate structure 90 in the vertical direction.
Referring to
An upper portion of the lower contact plug 475 may be additionally removed. Thus, an upper surface of the lower contact plug 475 may be lower than upper surfaces of the fourth and fifth spacers 430 and 450 in the vertical direction.
A sixth spacer layer may be formed on the bit line structure 395, the preliminary spacer structure 460, the second capping pattern 485 and the lower contact plug 475, and may be anisotropically etched to form a sixth spacer 490 at least partially covering an upper portion of the preliminary spacer structure 460 on the sidewall of the bit line structure 395, and the upper surface of the lower contact plug 475 may be at least partially exposed by the etching process.
A metal silicide pattern 500 may be formed on the exposed upper surface of the lower contact plug 475. In example embodiments, the metal silicide pattern 500 may be formed by forming a first metal layer on the first and second capping patterns 385 and 485, the sixth spacer 490 and the lower contact plug 475, performing a heat treatment thereon, and removing an unreacted portion of the first metal layer.
Referring to
A planarization process may be performed on an upper portion of the second metal layer 540. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and/or an etch-back process.
Referring to
The sixth opening 560 may be formed by partially removing the first and second capping patterns 385 and 485, the preliminary spacer structure 460 and the sixth spacer 490, as well as the second metal layer 540 and the second barrier layer 530.
The upper contact plug 555 may include a second metal pattern 545 and a second barrier pattern 535 at least partially covering a lower surface of the second metal pattern 545. In example embodiments, the upper contact plug 555 may have a shape of a circle, an ellipse, or a rounded polygon in a plan view, and the upper contact plugs 555 may be arranged, for example, in a honeycomb pattern in the first and second direction D1 and D2, in a plan view.
The lower contact plug 475, the metal silicide pattern 500 and the upper contact plug 555 sequentially stacked on the substrate 100 may collectively form a contact plug structure.
Referring to
Each of the sixth and seventh insulation patterns 570 and 580 may form a second insulation pattern structure 590.
A top end of the air gap may be at least partially covered by the sixth insulation pattern 570, and thus an air spacer 435 may be formed. The third spacer 400, the air spacer 435 and the fifth spacer 450 may collectively form a spacer structure 465.
Referring again to
The mold layer may be removed, and a dielectric layer 620 and an upper electrode 630 may be formed on the lower electrode 610 and the second etch stop pattern 600. Accordingly, the capacitor 640 including the lower electrode 610, the dielectric layer and the upper electrode 630 may be formed, and the manufacturing of the semiconductor device may be completed.
While embodiments of the inventive concept have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0098900 | Jul 2023 | KR | national |
