Patent Application
20130155733
1. Field
The present disclosure relates generally to power converters and, more specifically, the present disclosure relates to detecting fault conditions in a power converter using a fault-protection latch-reset.
2. Related Art
Power converters are used in many electrical devices to transform an alternating current (ac) power supply into a direct current (dc) power supply. Generally, these converters include a controller that switches a power switch between an ON state and an OFF state to control the amount of power transmitted to the output of the converter.
Some power converter controllers may include fault-protection circuitry that detect and respond to fault conditions of the controller and/or power supply (e.g., over voltage condition, low voltage condition, and the like). In some instances, the fault protection circuitry may cause the controller to shut down the power converter. In this scenario the power converter may use an input monitoring circuit to indicate resetting of the controller when input to the power converter has been removed (e.g., due to the converter being unplugged from a wall outlet). Specifically, when the ac input is removed the input monitoring circuit may provide a reset signal to reset the controller back to its initial conditions such that when the power converter is again connected to the ac input, the controller may presume operation.
Conventional input monitoring circuits generally include resistive elements (e.g., 2M-ohm resistors) connected to the AC input of the power converter that continuously dissipate power. While these circuits are effective at detecting fault conditions, the resistive elements cause the power converter to consume relatively large amounts of power at no-load conditions. For example, some conventional input monitoring circuits consume power during normal operation. While the amount of power consumed may be small relative to the amount of power delivered to an attached load, it may be a relatively large portion of power to consume during no-load conditions.
Additionally, specifications for newer electronic devices require that power converters consume less power during no-load conditions. For example, some laptop specifications require that the total no-load consumption of an adapter be less than 30 mW. However, conventional input monitoring circuits may consume 30 mW or more alone, leaving no room for power consumption by the rest of the power converter.
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
In the various embodiments, an ac input may be monitored by an input monitoring circuit that uses the ac input to charge a line detection capacitor. The input monitoring circuit may be configured such that the voltage at one end of the line detection capacitor drops below a line detection threshold voltage when the ac input is removed for longer than an allowable period of time or when the voltage of the ac input falls below an acceptable value. The drop in voltage at the end of the capacitor may cause an electrically coupled transistor to turn on, thereby causing a reset-signal to be generated.
To illustrate,
Power converter system 100 further includes power converter 103 coupled to the output of AC Bridge 101. Power converter 103 may be configured to receive a rectified voltage and output dc output voltage VOUT. Power converter 103 may include many types of power converter topologies such as, but not limited to, flyback, forward, buck, and boost topologies. In addition, power converter 103 may further include a power switch (not shown) that switches to control the transfer of energy through a magnetic energy transfer element (not shown). In one example, power converter 103 may include a coupled inductor (not shown) electrically coupled to a power switch, such as, but not limited to, a metal oxide semiconductor field effect transistor (MOSFET). The power switch may be used to control the amount of current conducted through the coupled inductor, and thus, the amount of power transferred to the output winding (not shown) of the coupled inductor, by switching between an ON state (allowing current to be conducted through the switch) and an OFF state (preventing current from being conducted through the switch). Power converter 103 may further include capacitors, such as an input-smoothing capacitor (not shown), an output-smoothing capacitor (not shown), clamp circuitry (not shown), feedback circuitry (not shown), or other circuit elements that one skilled in the art would know how to arrange for a particular application.
Power converter system 100 further includes controller 107 for controlling the output voltage VOUT at output terminals 111 by selectively scheduling the switching events of power converter 103. In one example, power converter system 100 may regulate an output current and/or a combination of output voltage VOUT and output current IOUT. Specifically, controller 107 may be configured to initiate a switching event by sending a drive signal 115 to the base or control terminal of the power switch in power converter 103. Controller 107 may adjust characteristics of the switching events (e.g., frequency, duration, etc.) to control the amount of power delivered to the output of power converter system 100. Additionally, in response to a fault condition at the input of power converter system 100 (e.g., as indicated by a reset signal 117), controller 107 may be configured to shut down or enter a protection-mode in which the controller inhibits switching of the power switch, except when periodically attempting to restart the system.
As shown, controller 107 may receive a feedback signal 116 representative of information relating to the output of power converter system 100. For example, controller 107 may receive feedback signal 116 in order to regulate output voltage VOUT at output terminals 111. In one example, controller 107 may be implemented as an integrated circuit. In another example, controller 107 and the power switch in power converter 103 may form part of an integrated control circuit that is manufactured as either a hybrid or monolithic integrated circuit.
Power converter system 100 further includes AC-latch-reset 105 for detecting fault conditions (e.g., removal of the AC input or low voltage condition) at the input of power converter system 100 and generating a reset signal 117 in response to detecting a fault condition.
In some embodiments, power converter system 100 may further include a fault shutdown latch (not shown). This latch may be triggered during a system fault-condition, such as an over-voltage condition at the output, an under voltage condition at the output, or the like. Once a system fault-condition is detected, controller 107 may trigger the shutdown latch to prevent further switching of the power switch. In these embodiments, AC-latch-reset 105 may be used to reset the fault shutdown latch and thus restore normal device operation. For example, to reset the fault shutdown latch, the AC-latch-reset 105 may generate reset signal 117 in response to detecting a reset condition (e.g., removal of the ac input). Reset signal 117 may be received by controller 107, causing controller 107 to enter a normal operation mode in which it resets the fault shutdown latch, thereby allowing normal switching of the power switch. Various embodiments of AC-latch-reset 105 will be described in greater detail below with respect to
In some examples, reset signal URESET may be the same signal as reset signal 117 shown in
AC-latch-reset 105 of
AC-latch-reset 105 may further include a high impedance circuit 205 coupled to the input terminals 201 of AC-latch-reset 105. In some embodiments, high impedance circuit 205 may include resistor R1, diode D2, and resistor R2. In this configuration, line detection capacitor C2 is charged through resistor R1 and diode D2 during at least a portion of each of the positive half-cycles of input voltage VAC. Additionally, line detection capacitor C2 can be continuously discharged through resistor R2 during both the positive and negative half-cycles of input voltage VAC. However, the rate of charge of capacitor C2 through resistor R1 and diode D2 during at least a portion of each of the positive half-cycles of input voltage VAC may be greater than the rate of discharge of capacitor C2 through resistor R2, resulting in a net increase in charge on capacitor C2.
AC-latch-reset 105 may further include diode D3 coupled across line detection capacitor C2. Diode D3 can be included to limit the voltage VC2 across line detection capacitor C2 to a maximum value equal to the turn-on voltage of diode D3 (e.g., 0.7 V). Specifically, as the voltage VC2 across line detection capacitor C2 increases to the turn-on voltage of diode D3, diode D3 begins to conduct current from node N3 into voltage source VDD, thereby preventing the voltage VC2 across line detection capacitor C2 from rising above a maximum value (the turn-on voltage of diode D3). By limiting the voltage VC2 across line detection capacitor C2, diode D3 also limits the voltage at node N3 to a maximum value approximately equal to the voltage of voltage source VDD plus the turn-on voltage of diode D3 (e.g., about 0.7 V).
It can be desirable to limit the voltage VC2 across line detection capacitor C2 and the voltage at node N3 to provide a stable reference voltage from which capacitor C2 can be discharged. The stable reference voltage creates a constant, or at least substantially constant, discharge time between the maximum voltage of VC2 and a voltage level allowing the voltage at node N3 to drop below a threshold voltage that causes transistor Q2 to conduct. As a result, AC-latch-reset 105 may consistently generate reset signal URESET in response to removal of input voltage VAC for longer than an allowable period of time or if the voltage of the ac input falls below an acceptable value.
As shown, AC-latch-reset 105 may further include PNP transistor Q2 to generate reset signal URESET. Specifically, transistor Q2 is shown coupled to voltage source VDD and resistor R4. The state of transistor Q2 (e.g., ON/OFF), which is determined at least in part on the voltage at node N3, dictates the amount of current allowed to pass through resistor R4, and thus, the voltage of reset signal URESET.
AC-latch-reset 105 may be configured such that when input VAC is applied to AC-latch-reset 105, the voltage at node N3 is large enough such that the voltage difference between the base and emitter of transistor Q2 may be below the turn-on threshold voltage of PNP transistor Q2, thus preventing current from being conducted through the transistor Q2 and resistor R4. As a result, the voltage of reset signal URESET remains at or near the reference voltage of output return 220.
Additionally, AC-latch-reset 105 may be further configured such that when input voltage VAC is disconnected from AC-latch-reset 105 or when input voltage VAC falls below an input voltage threshold, the voltage at node N3 drops below a line detection threshold voltage, causing the voltage difference between the base and emitter of transistor Q2 to rise above the turn-on threshold voltage of transistor Q2, allowing current to conduct through transistor Q2 and resistor R4. As a result, the voltage of reset signal URESET rises to a voltage that is a function of the current passing through transistor Q2 and the resistance of resistor R4. Since transistor Q2 is inactive during normal operation and only active for a brief time during a fault condition, when the voltage at node N3 drops below a certain line detection threshold, power consumption of transistor Q2 is reduced.
In some embodiments, the base to emitter breakdown voltage of transistor Q2 can be 5V or less. In these embodiments, to prevent transistor Q2 from failing, the voltage at node N3 can be clamped to a voltage that is less than the voltage of VDD plus the base to emitter breakdown voltage of transistor Q2. For example, as shown in
AC-latch-reset 105 may further include a base resistor (not shown) coupled to the base of transistor Q2. In one example, the base resistor may form a resistor divider with resistor R2 and may set a minimum voltage across capacitor C2.
Given the description above, it should be apparent that many variations of values for each component may be used to provide the desired performance for any given application. However, in one example embodiment, the components may have approximately the following values: R1=10 MΩ R2=10 MΩ, R4=100 kΩ, VDD=5.8 V, C2=22 nF, β of Q2=20, and the breakdown voltage of D2 and D3=75 V. In some examples, this particular configuration allows the circuit to detect the presence of an ac input having a voltage of 40 VAC or greater while consuming a relatively small amount of power.
The operation of AC-latch-reset 105 will now be described with simultaneous reference to the schematic of AC-latch-reset 105 shown in
Referring now to input current IAC shown in
Referring now to voltage VN3 at node N3 shown in
Referring back to
The operation of the embodiments of AC-latch-reset 105 shown in
Referring now to voltage VN3 at node N3 shown in
Referring back to
Referring now to
At block 703, a line detection capacitor may be charged through the high impedance circuit. This may occur while the diode of the high-impedance circuit is conducting. In some embodiments, the line detection capacitor may be similar to capacitor C2, and may be charged through capacitor C1 and diode D2 of high impedance circuit 205 while diode D2 is conducting. In other embodiments, the line detection capacitor may be similar to capacitor C2, and may be charged through resistor R1 and diode D2 of high impedance circuit 205 while diode D2 is conducting.
At block 705, the voltage across the line detection capacitor may decrease as the line detection capacitor is discharged through the resistor of the high-impedance circuit. This may occur while the diode of the high-impedance circuit is not conducting. For example, line detection capacitor C2 may be discharged through resistor R2 of high impedance circuit 205 while no current is conducting through diode D2.
At block 707 the voltage at one end of line detection capacitor may be monitored. For example, transistor Q2 may be used to monitor the voltage at node N3 coupled to line detection capacitor C2. At block 709, it may be determined whether or not the voltage at one end of line detection capacitor has fallen below a threshold voltage. If the voltage is not below the threshold voltage, the process returns to block 701. However, if the voltage is below the threshold voltage, the process moves to block 711. For example, transistor Q2 may be used to facilitate monitoring of the voltage at node N3 coupled to line detection capacitor C2 to determine whether or not the at node N3 has fallen below a line detection threshold voltage. In the examples shown in FIGS. 2, 4, and 5, the line detection threshold voltage may be equal to or less than the voltage of voltage source VDD minus the emitter-base voltage of transistor Q2.
At block 711, a reset signal may be generated. For example, if the voltage VN3 at node N3 falls below the line detection threshold voltage, transistor Q2 may turn on, driving the voltage of reset signal URESET to a non-zero voltage representing a high signal.
While the blocks of process 700 have been presented in a particular sequence, it should be appreciated that they may be performed in any order and that one or more blocks may be performed at the same time. For instance, a transistor (e.g., transistor Q2) may be used to facilitate the monitoring of the voltage at one end of line detection capacitor C2 as the input voltage VAC causes the capacitor to be repeatedly charged and discharged. In one example, if the ac input is removed, the transistor may monitor the voltage at one end of line detection capacitor C2 as the capacitor is discharged. Upon reaching the turn-on threshold voltage, transistor Q2 may turn on, causing reset signal URESET to be generated.
The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.
These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.
