Patent Application
20130243113
1. Field
The present disclosure relates to frequency generation in electronic devices.
2. Background
Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over wireless networks. Many such wireless telephones incorporate additional devices to provide enhanced functionality for end users. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can execute software applications, such as a web browser application that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
In an electronic device, such as a wireless telephone, a local oscillator (LO) frequency may be used to perform signal processing operations (e.g., at a transceiver of the wireless telephone). The LO frequency may depend on the frequency of a wireless channel that is in use. A phase-locked loop (PLL) may be used to generate the LO frequency. As high frequency channels become more common, higher LO frequencies may be needed to perform operations at the wireless telephone. However, it may be difficult to design a PLL to keep up with increasing LO frequency requirements due to process/voltage/temperature (PVT) variations experienced by the PLL. To illustrate, a high frequency PLL may not meet tuning, noise, or power consumption requirements. In addition, routing of high LO frequency signals to various components of the wireless telephone may consume an unacceptably high amount of battery power.
Systems and methods of generating a LO frequency by upconversion (e.g., multiplication) of a sub-harmonic frequency are disclosed. For example, the described techniques may be applied in multiple-input multiple-output (MIMO) devices that utilize a LO frequency of approximately 60 gigahertz (GHz). To illustrate, the MIMO devices may be compatible with an Institute of Electrical and Electronics Engineers (IEEE) 802.11ad protocol, in which four wireless channels exist between 57 GHz and 66 GHz. The described techniques may also be used with other standards that support MIMO, as well as standards without MIMO.
To generate a high frequency (e.g., 60 GHz) LO signal, the described techniques may first generate a lower frequency sub-harmonic of the desired LO signal. For example, a 15 GHz or 20 GHz sub-harmonic of the desired 60 GHz signal may be generated using a PLL. At a routing endpoint (e.g., front-end mixer blocks of a MIMO device), the sub-harmonic signal may be multiplied to generate the LO signal. Generating and routing the sub-harmonic signal instead of the LO signal may relax PLL design requirements and use less power at the PLL. Moreover, routing the sub-harmonic signal instead of the LO signal to the routing endpoints may use less power at an electronic device. Use of sub-harmonic signals may also provide increased immunity to frequency pulling effects, electromagnetic and substrate coupling (e.g., to sensitive blocks, such as a low noise amplifier (LNA)), and PVT variations in phase or amplitude experienced by in-phase/quadrature-phase (I/Q) signals in a MIMO device.
Unlike superheterodyne architectures that attempt to generate a 60 GHz signal using a conversion to an intermediate frequency (e.g., 48 GHz), the disclosed system and method may use a single homodyne (also referred to as zero-IF) conversion to generate frequencies at or near all four wireless channel frequencies of 802.11ad over potential PVT variations. In some implementations, the LO frequency generation and routing techniques disclosed herein may be used in conjunction with a superheterodyne architecture. For example, a 12 GHz sub-harmonic signal may be generated and routed in a 48 GHz superheterodyne system.
In a particular embodiment, an apparatus for generating a LO signal includes a PLL configured to output a signal having a frequency that is a sub-harmonic of a LO frequency. The apparatus also includes a mixer blocking having a frequency upconverter configured to upconvert the signal to generate a LO signal having the LO frequency.
In another particular embodiment, an apparatus for generating a LO signal includes a MIMO device including a PLL configured to output a signal having a frequency that is a sub-harmonic of a LO frequency. The MIMO device also includes a plurality of mixer blocks, where each mixer block is associated with a particular input and a particular output of the MIMO device. Each mixer block includes a frequency upconverter configured to upconvert the signal to generate a LO signal having the LO frequency. The MIMO device further includes a plurality of sub-harmonic transmission paths, where each sub-harmonic transmission path is configured to route the signal to a mixer block of the plurality of mixer blocks.
In another particular embodiment, a method for generating a LO signal includes generating, at a PLL of an electronic device, a signal having a frequency that is a sub-harmonic of a LO frequency of the electronic device. The method also includes upconverting the signal at a mixer block to generate a LO signal having the LO frequency.
In another particular embodiment, a method for generating a LO signal includes generating, at a PLL of a MIMO device, a signal having a frequency that is a sub-harmonic of a LO frequency of the MIMO device. The method also includes routing the signal to each of a plurality of mixer blocks of the MIMO device via a corresponding one of a plurality of sub-harmonic transmission paths of the MIMO device. The method further includes upconverting the signal at each of the plurality of mixer blocks to generate a LO signal having the LO frequency at each of the plurality of mixer blocks.
One particular advantage provided by at least one of the disclosed embodiments is an ability to generate a sub-harmonic frequency signal at a PLL and route the sub-harmonic frequency signal to endpoints such as front-end mixer blocks of a MIMO device, which locally upconvert the sub-harmonic frequency signal to generate a LO frequency signal. Generating and routing the sub-harmonic frequency signal instead of the LO frequency signal may simplify design and conserve power at the MIMO device.
Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.
The PLL 110 may include a phase frequency detector (PFD) 111 that receives a reference signal 101 having a reference frequency. In a particular embodiment, the reference signal 101 is provided by a system clock. The PFD 111 may also receive a feedback signal 105 from the prescaler 104. The PFD 111 may be configured to detect if and by how much the feedback signal 105 deviates from the reference signal 101. For example, the reference signal 101 may have a frequency of 100 megahertz (MHz) and the PFD 111 may determine if and by how much the feedback signal 105 is less than or greater than 100 MHz. It should be noted that the description of 100 MHz as a reference frequency is for illustration only. In alternate embodiments, other reference frequencies may be used.
The PLL 110 may also include a charge pump 112 and a filter 113 (e.g., a low pass filter) connected between the PFD 111 and an oscillator 114. In the embodiment of
The oscillator 114 may output the sub-harmonic signal 102 to the divider 103 coupled to the prescaler 104. The combination of the divider 103 and the prescaler 104 may frequency downconvert the sub-harmonic signal 102 to generate the feedback signal 105. For example, a 15 GHz sub-harmonic signal may be downconverted to an approximately 100 MHz feedback signal, and any deviation from 100 MHz may be detected by the PFD 111, as described above.
The oscillator 114 may also output the sub-harmonic signal 102 to the frequency upconverter 120. In a particular embodiment, when the sub-harmonic signal 102 is a 1/n sub-harmonic of the LO frequency, the frequency upconverter 120 may frequency upconvert the sub-harmonic signal by a factor of n. For example, the frequency upconverter 120 may upconvert a 15 GHz sub-harmonic signal by a factor of four to generate a LO signal having an LO frequency of 60 GHz. In a particular embodiment, the frequency upconverter 120 may include at least one signal multiplier (e.g., doubler) to perform the upconversion, as further described with reference to
During operation, the PLL 110 may generate and maintain (via phase and frequency locking) the sub-harmonic signal 102 at a frequency that is a sub-harmonic of a LO frequency. The sub-harmonic signal 102 may be routed to the frequency upconverter 120, which may upconvert the sub-harmonic signal 102 to generate a LO signal 121.
In a particular embodiment, the PLL 110 and the frequency upconverter 120 may be integrated into a radio frequency (RF) beamforming device. It should be noted that RF beamforming is described for illustration only. Methods of beamforming may include, but are not limited to, RF beamforming, baseband beamforming, digital beamforming, and LO beamforming. One or a combination of beamforming methods may be used in conjunction with the described signal generation techniques. As shown in
It will be appreciated that by operating the PLL 110 at a lower sub-harmonic frequency rather than at a higher LO frequency, the system 100 of
Further, the system 100 of
It should be noted that although
Each mixer block of the MIMO device 200 may be coupled to a PLL 201 via a corresponding sub-harmonic transmission path of a plurality of sub-harmonic transmission paths. For example, the mixer block 250 may be coupled to the PLL 201 via a first sub-harmonic transmission path 202. In an illustrative embodiment, the PLL 201 may include the PLL 110 of
The mixer block 250 may include a frequency upconverter, which is illustrated in
The differential signals may also be output to one or more second mixers 208 that are coupled to a second phase rotator 209. A power amplifier (PA) 210 may also be coupled to the second mixers 208, as shown. The LNA 207 and the PA 210 may be associated with a particular input and a particular output of the MIMO device 200. For example, the LNA 207 and the PA 210 may be connected to a particular RF front end/antenna of the MIMO device 200.
During operation, the PLL 201 may generate a sub-harmonic signal. The sub-harmonic signal may be routed to each of a plurality of mixer blocks (e.g., the mixer block 250 and the additional mixer blocks 230, 240, and 260) via one of a plurality of sub-harmonic transmission paths (e.g., the first sub-harmonic transmission path 202 and one or more second sub-harmonic transmission paths 220). The sub-harmonic signal may be frequency upconverted at each of the mixer blocks, and the resulting LO frequency signal may be used to generate I/Q signals that are provided to other components of the mixer blocks, as shown.
In a particular embodiment, the MIMO device 200 may be integrated into a wireless device. For example, when the LO frequency is 60 GHz, the wireless device may be a millimeter wavelength (mmWave) device operable to communicate in accordance with an IEEE 802.11ad protocol, which includes four wireless channels having frequencies between 57 GHz and 66 GHz.
As shown in
The system 300 includes a first doubler 310, a balun 320, and a second doubler 330. The first doubler 310 may be configured to receive a first input signals 301 and a second input signal 302 (e.g., differential signals) having a frequency (e.g., 15 GHz) that is one-fourth a LO frequency (e.g., 60 GHz). The first doubler 310 may generate a single-ended signal 303 having a second frequency (e.g., 30 GHz) that is approximately one-half the LO frequency. The balun 320 may generate a first differential signal 304 and a second differential signal 305 from the single-ended signal 303, as shown. The differential signals 304, 305 may be output to the second doubler 330, which may generate a LO signal 306 (e.g., a 60 GHz signal) from the differential signals 304, 305.
When the system 300 of
A particular embodiment of a circuit-level implementation of the first doubler 310, the balun 320, and the second doubler 330 is illustrated in
The balun 320 may include a second inductor 420 and a third inductor 421 that are connected to the voltage supply (Vdd) and to a second variable capacitor 422. The balun 320 may also include a fifth NFET 427 and a sixth NFET 428 that are cross-coupled, as shown. A gate of the fifth NFET 427 may be connected to a fourth resistor 425 and to a third capacitor 430. A gate of the sixth NFET 428 may be connected to a fifth resistor 426 and to a fourth capacitor 429. The fourth resistor 425 and the fifth resistor 426 may be connected to a third bias voltage (e.g., a voltage generated on-chip). The single-ended signal 303 may be received at a fifth capacitor 432 that is connected to a sixth resistor 433 and to a seventh NFET 434. A seventh resistor 436 may be connected to a sixth capacitor 431 and to an eighth NFET 435, as shown. The sixth resistor 433 and the seventh resistor 436 may be connected to a fourth bias voltage (e.g., a voltage generated on-chip). A third pad 423 of the balun 320 may produce the first differential signal 304 of
The second doubler 330 may include a fifth pad 440 that receives the first differential signal 304 as input and a sixth pad 447 that receives the second differential signal 305 as input. The fifth pad 440 may be connected to a seventh capacitor 441 that is connected to an eighth resistor 442 and to a ninth NFET 443. The sixth pad 447 may be connected to an eighth capacitor 446 that is connected to a ninth resistor 445 and to a tenth NFET 444. The eighth resistor 442 and the ninth resistor 445 may be connected to a fifth bias voltage (e.g., a voltage generated on-chip). The second doubler 330 may also include a fourth inductor 448, a fifth inductor 449, and a sixth inductor 450 connected between the voltage supply (Vdd) and a third variable capacitor 451, as shown. The fifth inductor 449 may also be connected to a gate of an eleventh NFET 453 that is also connected to a seventh pad 452. The seventh pad 452 may produce the LO signal 306 of
The method 500 may include generating, at a PLL of an electronic device, a signal having a frequency that is a sub-harmonic of a LO frequency of the electronic device, at 502. For example, in
The method 500 may also include routing the signal over a first distance from the PLL to a mixer block, at 504. For example, in
The method 500 may further include upconverting the signal at the mixer block to generate an LO signal having the LO frequency, at 506. For example, in
The method 500 may include routing the LO signal generated at the mixer block over a second distance that is less than the first distance, at 508. For example, referring to
The method 600 may include generating, at a PLL of a MIMO device, a signal having a frequency that is a sub-harmonic of a LO frequency of the MIMO device, at 602. For example, in
The method 600 may also include routing the signal to each of a plurality of mixer blocks of the MIMO device via a plurality of sub-harmonic transmission paths of the MIMO device, at 604. A length of each sub-harmonic transmission path may be substantially longer than a distance between a frequency upconverter and an I/Q signal generation unit of the mixer block coupled to the sub-harmonic transmission path. For example, in
The method 600 may further include upconverting the signal at the frequency upconverter of each of the mixer blocks to generate a LO signal having the LO frequency at each of the mixer blocks, at 606. For example, in
The method 600 may include generating I/Q signals at each mixer block based on the LO signal at each mixer block, at 608, and performing one or more wireless signal processing operations at each mixer block based on the generated I/Q signals, at 610. For example, in
The memory 732 may be a non-transitory tangible computer-readable and/or processor-readable storage device that stores instructions 760. The instructions 760 (and other instructions associated with other components of the device 700, such as firmware associated with a controller) may be executable (e.g., by the processor 710 or other component of the device 700) to initiate, control, or perform the methods described with reference to
The transceiver 750 may include a PLL 791 that is connected to a plurality of front-end mixer blocks, such as illustrative mixer blocks 792, 793, 794, and 795. In an illustrative embodiment, the PLL 791 may be the PLL 110 of
In a particular embodiment, the processor 710, the display controller 726, the memory 732, the CODEC 734, the wireless controller 740, and the transceiver 750 are included in a system-in-package or system-on-chip device 722. In a particular embodiment, an input device 730 and the power supply 744 are coupled to the system-on-chip device 722. Moreover, in a particular embodiment, as illustrated in
In conjunction with the described embodiments, an apparatus is disclosed that may include means for outputting a signal having a frequency that is a sub-harmonic of a LO frequency. For example, the means for outputting may include the PLL 110 of
The apparatus may further include means for routing the signal to each of the plurality of mixer blocks. For example, the means for routing may include the sub-harmonic transmission path 202 of
Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal (e.g., a mobile phone or a PDA). In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.
The previous description of the disclosed embodiments is provided to enable a person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments disclosed herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
The present application claims priority from commonly owned U.S. Provisional Patent Application No. 61/612,031 filed on Mar. 16, 2012, the contents of which are expressly incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61612031 | Mar 2012 | US |
