Patent Grant
10984739
The present invention relates to the field of display technologies, and in particular to a ghost relieving circuit for a display panel, a display panel and a ghost relieving method for a display panel.
With the development of display technology, liquid crystal display (LCD) has gradually replaced the cathode ray tube (CRT) display device due to its advantages of lightness, thinness and low radiation. Liquid crystal displays are widely used in information terminals such as computers, smart phones, mobile phones, car navigation devices, and electronic books, and become the most common display devices.
On the one hand, there is only one gamma chip on the liquid crystal display panel currently used. Please refer to
On the other hand, the liquid crystal molecules in the liquid crystal display panel are fixed at a certain voltage for a long time, which causes the ions around the liquid crystal molecules to move toward the glass direction, and even some ions may adhere to the alignment film. When the voltage is applied, the electric field generated by the ions cancels a part, which causes the liquid crystal deflection characteristics to change. Therefore, at intervals, the voltage must be restored to the original state to prevent ions from adhering to the alignment film. Generally, the electric field applied to the liquid crystal molecules is directional. In different time periods, an electric field in the opposite direction is applied to the liquid crystal molecules, which is called “polarity inversion”. That is, the voltage applied to the liquid crystal molecules is a symmetric positive voltage and a negative voltage. In practical applications, the pixel voltage is divided into a positive-polarity and a negative-polarity, and the pixel voltage is a data voltage minus a feedthrough voltage, wherein the feedthrough voltage is a voltage drop caused by the gate voltage coupling the pixel electrode. The gate voltage and the data voltage have different voltage drops in different areas of the liquid crystal display panel, so the positive and negative pixel voltages cannot be completely symmetrical in all areas by the compensation of a single Vcom. Therefore, when the liquid crystal panel is loaded with the same image for a long time, charged ions in the liquid crystal are adsorbed on both ends of the liquid crystal above and below the glass to generate a built-in electric field. When the screen is switched, the ions cannot be released immediately, so that the liquid crystal molecules are not immediately deflected to the corresponding angle, causing the current picture to retain the information of the previous picture, called ghost. Therefore, how to improve the ghost problem of the liquid crystal display panel has become an urgent problem to be solved.
In order to solve the defects and deficiencies of the prior art, embodiments of the present invention provide a ghost relieving circuit for a display panel, a display panel, and a ghost relieving method for a display panel.
In a first aspect, a ghost relieving circuit for a display panel according to an embodiment of the present invention includes: a digital-to-analog converter, a first switching circuit, a second switching circuit, and a gamma chip; wherein the gamma chip is connected to the digital-to-analog converter and configured to provide a plurality of reference voltages to the digital-to-analog converter, the digital-to-analog converter is individually connected to the first switching circuit and the second switching circuit, the first switching circuit is connected to receive a first working voltage and a positive-polarity reference voltage and has an positive-polarity data voltage output end, the second switching circuit is connected to receive a second working voltage and a negative-polarity reference voltage and has a negative-polarity data voltage output end, and the positive-polarity reference voltage is less than the negative-polarity reference voltage.
In an embodiment of the present invention, the first switching circuit includes a first switching transistor and a second switching transistor. The positive output end of the digital-to-analog converter is connected to the control end of the first switching transistor and the control end of the second switching transistor; the first end of the first switching transistor is connected to receive the first working voltage, a node formed by connecting the second end of the first switching transistor and the first end of the second switching transistor in series is used as the positive-polarity data voltage output end, and the second end of the second switching transistor is connected to receive the positive-polarity reference voltage.
In an embodiment of the present invention, the first switching transistor is a P-type transistor, and the second switching transistor is an N-type transistor.
In an embodiment of the present invention, the second switching circuit includes a third switching transistor and a fourth switching transistor. The negative output end of the digital-to-analog converter is connected to the control end of the third switching transistor and the control end of the fourth switching transistor; the first end of the third switching transistor is connected to receive the negative-polarity reference voltage, a node formed by connecting the second end of the third switching transistor and the first end of the fourth switching transistor in series is used as the negative-polarity data voltage output end, and the second end of the fourth switching transistor is connected to receive the second working voltage.
In an embodiment of the present invention, the third switching transistor is a P-type transistor, and the fourth switching transistor is an N-type transistor.
In an embodiment of the present invention, the plurality of reference voltages include a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage in an order from the largest to the smallest as per voltage values thereof; the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage are corresponding to a highest gray scale of positive polarity, a lowest gray scale of negative polarity, a lowest gray scale of positive polarity, and a highest gray scale of negative polarity respectively; the first working voltage is greater than the first reference voltage, the positive-polarity reference voltage is less than the third reference voltage and greater than the second working voltage, the negative-polarity reference voltage is greater than the second reference voltage and less than the first working voltage, the second working voltage is less than the fourth reference voltage. The voltage range from the positive-polarity reference voltage to the first working voltage and the voltage range from the negative-polarity reference voltage to the second working voltage have an overlapped range.
In an embodiment of the present invention, the ghost relieving circuit is applied to a source driver of the display panel, positive gray scale ranges corresponding to different areas of the display panel respectively are different, and negative gray scale ranges corresponding to the different areas respectively are different.
Compared with the prior art, the first aspect of the present invention has the following beneficial effects: the ghost relieving circuit can keep the common voltage Vcom unchanged. By adjusting the positive-polarity reference voltage and the negative-polarity reference voltage, the voltage range of the positive-polarity reference voltage to the first working voltage and the voltage range of the negative-polarity reference voltage to the second working voltage have an overlapped range. The pixel voltage of the entire display panel can be symmetrical with respect to the common voltage Vcom, thereby reducing the ghost of the display panel. Moreover, the output buffer formed by the first switching transistor and the second switching transistor of the ghost relieving circuit provided by the present invention only needs to be close to the highest and lowest differential pressure of the half width, thereby effectively improving the driving force and reducing the cost, and ensuring the state of the display content of the display panel.
In a second aspect, the present invention provides a display panel including a timing controller, configured to form a scan line control timing, a first data line control timing, and a second data line control timing, wherein the first data line control timing and the second data line control timing are formed respectively according to a first gray scale and a second gray scale formed from an original image gray scale; a gate driver, connected to the timing controller and configured to receive the scan line control timing and thereby generate a scan line voltage signal; a source driver, connected to the timing controller and configured to receive the first data line control timing and the second data line control timing and thereby generate a first data line voltage signal and a second data line voltage signal respectively; and a pixel matrix, connected to the gate driver and the source driver and configured to perform displaying of an image according to the scan line voltage signal, the first data line voltage signal, and the second data line voltage signal.
In an embodiment of the present invention, the timing controller includes a sub-pixel lookup table, the sub-pixel lookup table is configured to form the first gray scale and the second gray scale according to the original image gray scale.
In an embodiment of the present invention, the sub-pixel lookup table includes original image gray scales of sub-pixels at predetermined positions, first gray scales corresponding to the original image gray scales, and second gray scales corresponding to the original image gray scales.
In an embodiment of the present invention, the timing controller is further configured to determine whether a sub-pixel to be displayed corresponding to the original image gray scale is the sub-pixel at the predetermined position; if yes, search the sub-pixel lookup table according to the original image gray scale corresponding to the sub-pixel to be displayed to thereby determine the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed; if not, calculate the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed by using an interpolation algorithm according to the sub-pixel lookup table.
In an embodiment of the present invention, the timing controller is further configured to perform frame rate control on a sub-pixel of the pixel matrix; the frame rate control specifically includes adjusting a ratio of occurrence time of different gray scales for the sub-pixel in a time period of a plurality of image frames.
In an embodiment of the present invention, the timing controller is further configured to perform dithering on a plurality of sub-pixels of the pixel matrix; the dithering specifically includes adjusting a ratio of positional arrangement of different gray scales for ones of the plurality of sub-pixels in a same image frame.
In an embodiment of the present invention, the source driver includes a digital-to-analog converter, a first switching circuit, a second switching circuit, and a gamma chip. The gamma chip is connected to the digital-to-analog converter and configured to provide a plurality of reference voltages to the digital-to-analog converter. The digital-to-analog converter is connected to the first switching circuit and the second switching circuit individually. The first switching circuit is connected to receive a first working voltage and a positive-polarity reference voltage and has a positive-polarity data voltage output end. The second switching circuit is connected to receive a second working voltage and a negative-polarity reference voltage and has a negative-polarity data voltage output end, and the positive-polarity reference voltage is less than the negative-polarity reference voltage; the digital-to-analog converter is configured to receive the first data line control timing and the second data line control timing, the positive-polarity data voltage output end is configured to generate the first data line voltage signal, the negative-polarity data voltage output end is configured to generate the second data line voltage signal.
In an embodiment of the present invention, the plurality of reference voltages include a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage in an order from the largest to the smallest as per voltage values thereof; the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are corresponding to a highest gray scale of positive polarity, a lowest gray scale of negative polarity, a lowest gray scale of positive polarity, and a highest gray scale of negative polarity respectively. The first working voltage is greater than the first reference voltage, the positive-polarity reference voltage is less than the third reference voltage and greater than the second working voltage, the negative-polarity reference voltage is greater than the second reference voltage and less than the first working voltage, and the second working voltage is less than the fourth reference voltage. A voltage range from the positive-polarity reference voltage to the first working voltage and a voltage range from the negative-polarity reference voltage to the second working voltage have an overlapped range.
In an embodiment of the present invention, the gate driver is a COF type driving module or a GOA type driving module.
Compared with the prior art, the second aspect of the present invention has the following beneficial effects: the display panel adjusts the input voltage across the sub-pixel by keeping the Vcom voltage constant. Compared with the original method of adjusting the Vcom voltage, it is possible to more accurately control the symmetry of the positive and negative-polarity pixel voltages in the entire display panel area, and effectively reduce the ghost of the display panel.
In a third aspect, an embodiment of the present invention provides a ghost relieving method, which is applied to a display panel including a pixel matrix. The method includes acquiring input gray scales; acquiring first gray scales and second gray scales according to the input gray scales; acquiring corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales; and outputting the first voltages and the second voltages to a pixel matrix.
In an embodiment of the present invention, the step of acquiring first gray scales and second gray scales according to the input gray scales includes: establishing a lookup table for sub-pixels at predetermined positions; determining whether a sub-pixel to be displayed corresponding to one of the input gray scales is the sub-pixel at the predetermined position; if yes, searching the lookup table according to the input gray scale of the sub-pixel to be displayed, and determining the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed; if not, calculating the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed by using an interpolation algorithm according to the lookup table.
In an embodiment of the present invention, the step of establishing a lookup table for sub-pixels at predetermined positions includes: selecting the sub-pixels at the predetermined positions; determining input gray scales, first gray scales and second gray scales, corresponding to the sub-pixels at the predetermined positions; and storing the input gray scales, the first gray scales, and the second gray scales and thereby forming the lookup table.
In an embodiment of the present invention, before the step of acquiring corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales, further includes performing frame rate control according to the first gray scales and the second gray scales.
In an embodiment of the present invention, before the step of acquiring corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales, further including performing dithering according to the first gray scales and the second gray scales.
In a fourth aspect, an embodiment of the present invention provides a ghost relieving apparatus including a signal input module configured to acquire an input gray scale; a gray scale processing module, configured to acquire a first gray scale and a second gray scale according to the input gray scale; a voltage conversion module, configured to acquire a corresponding first voltage and a second voltage according to the first gray scale and the second gray scale respectively; and a signal output module, configured to output the first voltage and the second voltage to the pixel matrix.
In an embodiment of the present invention, the gray scale processing module includes: a lookup table establishing unit, configured to establish a lookup table for sub-pixels at predetermined positions; a sub-pixel determining unit, configured to determine whether a current sub-pixel of the liquid crystal display device to be displayed corresponding to one of the input gray scale is a selected number of the sub-pixels at the predetermined position; if yes, the lookup table is searched according to the input gray scale of the sub-pixel to be displayed, and the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed corresponding to the input gray scale is determined; if not, the first gray scale and the second gray scale corresponding to the input gray scale of the sub-pixel to be displayed are calculated by using an interpolation algorithm according to the lookup table.
In an embodiment of the present invention, the lookup table establishing unit is configured to select a plurality of sub-pixels at the predetermined position, determine the input gray scale, the first gray scale and the second gray scale corresponding to the sub-pixel at the predetermined position, and store the input gray scale, the first gray scale and the second gray scale to form the lookup table.
In an embodiment of the present invention, the ghost relieving apparatus further includes a frame rate control module, configured to perform frame rate control according to the first gray scale and the second gray scale before the voltage conversion module acquires a corresponding first voltage according to the first gray scale and a second voltage according to the second gray scale respectively.
In an embodiment of the present invention, the ghost relieving apparatus further includes a dithering module configured to perform dithering according to the first gray scale and the second gray scale before the voltage conversion module acquires a corresponding first voltage according to the first gray scale and a second voltage according to the second gray scale respectively.
Compared with the prior art, the third and fourth aspects of the present invention have the following beneficial effects: the method and the apparatus of this embodiment adjusts the voltage across the sub-pixel by keeping the Vcom voltage constant. Compared with the original method of adjusting the Vcom voltage, it is possible to more accurately control the symmetry of the positive and negative-polarity pixel voltages in the entire display panel area. That is, the pixel voltage of the entire display panel is symmetrical with respect to Vcom, which effectively reduces the image sticking of the display panel.
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the embodiments of the present application, and those skilled in the art can obtain other drawings according to the drawings without any creative work.
The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. It is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of them. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
Please refer to
The digital-to-analog converter 1 is connected to the first switching circuit 2 and the second switching circuit 3, the gamma chip 4 is connected to the digital-to-analog converter 1 for providing a plurality of reference voltages to the digital-to-analog converter 1.
In an embodiment of the invention, the first switching circuit 2 includes a first switching transistor M1 and a second switching transistor M2. The positive output end Vpout of the digital-to-analog converter 1 is connected to the control end of the first switching transistor M1 and the control end of the second switching transistor M2. The first end of the first switching transistor M1 is connected to receive the first working voltage AVDD, a node formed by connecting the second end of the first switching transistor M1 and the first end of the second switching transistor M2 in series is used as an output end of the positive-polarity data voltage Vi to provide a positive-polarity data voltage Vi to the pixel matrix of the display panel. The second end of the second switching transistor M2 is connected to receive the positive-polarity reference voltage VRPV.
In an embodiment of the invention, the first switching transistor M1 is a P-type transistor, and the second switching transistor M2 is an N-type transistor.
In an embodiment of the invention, the second switching circuit 3 includes a third switching transistor M3 and a fourth switching transistor M4. The negative output end Vnout of the digital-to-analog converter 1 is connected to the control end of the third switching transistor M3 and the control end of the fourth switching transistor M4. The first end of the third switching transistor M3 is connected to receive the negative-polarity reference voltage VRNV. A node formed by the second end of the third switching transistor M3 and the first end of the fourth switching transistor M4 being connected in series is used as an output end of the negative-polarity data voltage Vi+1 to provide a negative-polarity data voltage Vi+1 to the pixel matrix of the display panel. The second end of the fourth switching transistor M4 is connected to receive the second working voltage AGND.
In one embodiment of the invention, the third switching transistor M3 is a P-type transistor, and the fourth switching transistor M4 is an N-type transistor.
In an embodiment of the invention, the positive-polarity reference voltage VRPV is less than the negative-polarity reference voltage VRNV such that a voltage range from the positive-polarity reference voltage VRPV to the first working voltage AVDD and a voltage range from the negative-polarity reference voltage VRNV to the second working voltage AGND have an overlapped range.
The ghost relieving circuit provided by the embodiment of the invention can keep the common voltage Vcom unchanged. By adjusting the positive-polarity reference voltage VRPV and the negative-polarity reference voltage VRNV, the voltage range of the positive-polarity reference voltage VRPV to the first working voltage AVDD and the voltage range of the negative-polarity reference voltage VRNV to the second working voltage AGND have an overlapped range. The pixel voltage of the entire display panel can be symmetrical with respect to the common voltage Vcom, thereby reducing the ghost of the display panel.
Please refer to
Specifically, as shown in
The first end of the first switching transistor M1 is connected to the first working voltage AVDD, a node formed by connecting the second end of the first switching transistor M1 and the first end of the second switching transistor M2 in series is used as an output end of the positive-polarity data voltage Vi to provide a positive-polarity data voltage Vi to the pixel matrix of the display panel. The second end of the second switching transistor M2 is connected to the positive-polarity reference voltage VRPV. The first end of the first switching transistor M1 is a source, and the second end of the first switching transistor M1 is a drain. The first end of the second switching transistor M2 is a drain, and the second end of the second switching transistor M2 is a source.
In one embodiment of the present invention, the Gamma chip 4 provides four reference voltages V1, V2, V3 and V4 to the digital-to-analog converter 1; as an example, the values of V1 to V4 are V1=17V, V2=7.5V, V3=6V, and V4=0.5V, respectively. Furthermore, the first working voltage AVDD>V1 (e.g., >17V), the positive-polarity reference voltage VRPV<V3 (e.g., <6V) and VRPV>AGND, the negative-polarity reference voltage VRNV>V2 (e.g., >7.5V) and VRNV<AVDD, the second working voltage AGND<V4 (e.g., <0.5V). In addition, in
In one embodiment of the invention, the first switching transistor M1 is a P-type transistor and the second switching transistor M2 is an N-type transistor.
In the above, the first end of the third switching transistor M3 is connected to the negative-polarity reference voltage VRNV, a node formed by connecting the second end of the third switching transistor M3 and the first end of the fourth switching transistor 32 in series is used as an output terminal of the negative-polarity data voltage Vi+1 to provide a negative-polarity data voltage Vi+1 to the pixel matrix of the display panel. The second end of the fourth switching transistor 32 is connected to receive the second voltage end of the Gamma chip 4, the first end of the third switching transistor M3 is a source, the second end of the third switching transistor M3 is a drain, the first end of the fourth switching transistor 32 is a drain, the second end of the fourth switching transistor 32 is a source.
In one embodiment of the invention, the third switching transistor M3 is a P-type transistor and the fourth switching transistor M4 is an N-type transistor.
In an embodiment of the invention, the positive-polarity reference voltage VRPV is smaller than the negative-polarity reference voltage VRNV to have an overlapped range of the voltage range of the positive-polarity reference voltage VRPV to the first working voltage AVDD and the voltage range of the negative-polarity reference voltage VRNV to the second working voltage AGND.
More specifically, each sub-pixel corresponds to a positive gray scale and a negative gray scale. After the positive-polarity gray scale and the negative-polarity gray scale are converted into the corresponding positive-polarity data voltage Vi and the negative-polarity data voltage Vi+1, the positive-polarity data voltage Vi corresponds to the positive-polarity reference voltage VRPV, and the negative-polarity data voltage Vi+1 corresponds to the negative-polarity reference voltage VRNV. Wherein, the positive gray scale and the negative gray scale can be determined by testing, or can be obtained by calculation.
Further, as shown in
In summary, the ghost relieving circuit provided by the embodiment of the present invention can keep the common voltage Vcom unchanged. By adjusting the positive-polarity reference voltage and the negative-polarity reference voltage, the voltage range of the positive-polarity reference voltage VRPV to the first working voltage AVDD and the voltage range of the negative-polarity reference voltage VRNV to the second working voltage AGND have an overlapped range, the pixel voltage of the entire display panel can be symmetrical with respect to the common voltage Vcom, thereby reducing the ghost of the display panel.
Referring to
The timing controller 101 is configured to form a scan line control timing, a first data line control timing, and a second data line control timing, the first data line control timing and the second data line control timing are formed respectively according to the first gray scale and the second gray scale formed from the original image gray scale (also known as input image gray scale).
In one embodiment, the timing controller 101 includes a sub-pixel lookup table, and the lookup table is composed of original image gray scales corresponding to sub-pixels at predetermined positions, corresponding first gray scales, and corresponding second gray scales. The first gray scale and the second gray scale are symmetric positive gray scales and negative gray scales. The positive-polarity gray scale and the negative-polarity gray scale are converted into corresponding positive-polarity voltages and negative-polarity voltages. The timing controller 101 is further configured to determine whether the sub-pixel to be displayed corresponding to the gray scale of the original image is the sub-pixel at the predetermined position; if yes, the lookup table is searched according to the gray scale corresponding to the original image of the sub-pixel to be displayed thereby determine the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed; if not, calculate the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed by using an interpolation algorithm according to the sub-pixel lookup table. So far, the first gray scale corresponding to the original image gray scale and the second gray scale are formed by the sub-pixel lookup table. The timing controller 101 forms the first data line control timing and the second data line control timing according to the first gray scale and the second gray scale combined with a display clock period of the original image.
Furthermore, the timing controller 101 is further configured to perform frame rate control and dithering on the sub-pixels of the pixel matrix.
Specifically, the frame rate control is generated by using a color mixing effect in time to generate more gray scale effects, that is, adjusting a time ratio of different gray scales of the sub-pixels in a time period of the plurality of image frames; the dithering is to generate more gray scale effects by the spatial color mixing effect, that is, to adjust the positional arrangement ratios of the different gray scales of the plurality of sub-pixels in the plurality of sub-pixels of the same image frame.
The gate driver 102 is connected to the timing controller 101 for receiving the scan line control timing of the timing controller 101 and generating a scan line voltage signal.
Specifically, the gate driver is a chip on film (COF) type driving module or a gate driver on array (GOA) type driving module.
The source driver 103 is coupled to the timing controller 101 for receiving the first data line control timing and the second data line control timing and generating a first data line voltage signal and a second data line voltage signal respectively. For example, the source driver 103 of the present embodiment has the ghost relieving circuit shown in
The pixel matrix 104 is connected to the gate driver 102 and the source driver 103 for performing image display according to the scan line voltage signal, the first data line voltage signal, and the second data line voltage signal.
Specifically, in the current frame, the scan line voltage signal is input to a gate of a TFT transistor in the pixel matrix 104, the TFT transistor is turned on, and the first data line voltage signal is input to a source of the TFT transistor in the pixel matrix 104 to drive display of the sub-pixel; in the next frame, the scan line voltage signal is input to the gate of the TFT transistor in the pixel matrix 104, the TFT transistor is turned on, and the second data line voltage signal is input to a source of the TFT transistor in the pixel matrix 104 to drive display of the sub-pixel.
In summary, the liquid crystal display panel provided in this embodiment can accurately control the voltage symmetry of the entire pixel matrix 104 by converting the input gray scale of the sub-pixel matrix 104 into two gray scales in the timing controller 101, thereby solving the ghost problem of the display panel.
Please continue to see
(i) Selecting a plurality of sub-pixels in the pixel matrix, and determining first gray scales and second gray scales of the sub-pixels.
Specifically, the first gray scales and the second gray scales are a positive gray scale and a negative gray scale. The positive-polarity gray scale and the negative-polarity gray scale can be converted into corresponding positive-polarity data voltage and negative-polarity data voltage. The first gray scales and the second gray scales may be determined by testing, or may be obtained by calculation.
Further, as shown in
Preferably, in the conventional display mode, the positive gray scale and the negative gray scale corresponding to the input gray scale are mapped to the positive gray scale table, for example, a positive gray scale table with a positive gray scale corresponding to the input gray scale and a positive gray scale with a negative gray scale range of −511 to 511 is mapped to a positive gray scale table of 0 to 1023. The positive gray scale and the negative gray scale corresponding to the gray pixel 255 of the sub-pixel A are determined in the positive gray scale table of 0 to 1023, and the offset of the sub-pixel A input to the gray scale 255 is tested. The positive gray scale and the offset in the positive gray scale table are calculated to obtain the first gray scale corresponding to the input gray scale of 255. The negative gray scale and the offset in the positive gray scale table are calculated to obtain a second gray scale corresponding to the input gray scale of 255. The other sub-pixels obtain the first gray scale and the second gray scale corresponding to the input gray scale with reference to the mode.
(ii) Inputting the gray scales, the first gray scale, and the second gray scale corresponding to the selected sub-pixels to form a lookup table.
Specifically, forming a lookup table for the input gray scale, the first gray scale, and the second gray scale of each sub-pixel according to the first gray scale and the second gray scale corresponding to the gray scale input of each sub-pixel obtained in the step (i).
Further, for example, the range of the input gray scale of the sub-pixel A from 0 to 1023, and according to the step (i), the first gray scale and the second gray scale corresponding to the input gray scales of 0 to 1023 are respectively obtained. The input gray scale, the first gray scale, and the second gray scale form a lookup table, and the other sub-pixels refer to the sub-pixel A to form a lookup table.
(iii) acquiring a first gray scale and a second gray scale according to input gray scales of each sub-pixel in the pixel matrix.
Specifically, determining whether the current sub-pixel in the liquid crystal display panel is a plurality of sub-pixels selected in step (i); if yes, the first gray scale corresponding to the current sub-pixel input gray scale and the second gray scale are searched in the lookup table obtained in the step (ii), and the first gray scale corresponding to the current input pixel gray scale is obtained; if not, according to the lookup table of all the sub-pixels obtained in step (ii), the first gray scale and the second gray scale corresponding to the current input gray scale of the current sub-pixel are calculated by an interpolation algorithm.
Further, for example, different input gray scales of the sub-pixels A to I in the liquid crystal display panel use the sub-pixel A to I lookup table to determine the first gray scale and the second gray scale corresponding to different input gray scales. It is assumed that the sub-pixel K is located in the middle of the sub-pixel A, the sub-pixel B, the sub-pixel D, and the sub-pixel E, the first gray scale and the second gray scale corresponding to the current input gray scale of the sub-pixel K may be interpolated by using the first gray scale and the second gray scale corresponding to the current gray scale in the lookup table of the sub-pixel A, the sub-pixel B, the sub-pixel D and the sub-pixel E, thereby acquiring the first gray scale and the second gray scale corresponding to the current input gray scale of the sub-pixel K.
(iv) Performing frame rate control and dithering operations based on the first gray scale and the second gray scale.
Specifically, as can be seen from the above steps, when determining the first gray scale and the second gray scale of the sub-pixel, the positive gray scale and the negative gray scale in the positive gray scale table need to be asymmetrically offset to obtain the first gray scale and the second gray scale. The number of bits of the first gray scale and the second gray scale may exceed the number of bits that the digital drive circuit can output. Therefore, it is necessary to perform frame rate control and dithering operations on the liquid crystal display panel to compensate for this problem.
The frame rate control (FRC) operation produces more gray scale effects through the color mixing effect over time. For example, the original gray scale range is 0˜511, that is, 9-bit gray scale, and the FRC function is added. By the color mixing effect in time, the gray scale range of 0˜2047 or 11-bit gray scale can be produced. The function principle is as follows: in the time of four consecutive image frames, the ratio of the appearance time of black and white is adjusted, and the viewer can obtain the intermediate gray scale display effects of 1/4 gray, 2/4 gray and 3/4 gray. Although it is a 9-bit gray scale for a single frame, the liquid crystal display device dynamically refreshes the data, and the viewer perceives the 11-bit gray scale.
The dithering operation produces more gray scale effects through spatially mixed color effects. Taking the adjacent four pixel spaces as an example, the black and white color space position arrangement ratio is adjusted, and the viewer can obtain the intermediate gray scale display effects of 1/4 gray, 2/4 gray, and 3/4 gray.
Further, in the embodiment of the present invention, the first gray scale and the second gray scale are respectively subjected to frame rate control and dithering operations. As shown in
The number of gray scales can be increased by frame rate control and dithering operations. The frame rate control improves the resolution of the dithering, and the dithering improves the frame gradation loss of the frame rate control. The two perfectly match and complement each other, so that the best gray scale effect is mixed, and the gray scale transition is naturally smooth.
(v) Acquiring corresponding positive-polarity data voltage and negative-polarity data voltage according to the first gray scale and the second gray scale respectively.
Specifically, using the first gray scale and the second gray scale of each sub-pixel determined in the above steps, by the mapping relationship between the gray scale value and the Gamma curve, the positive-polarity data voltage corresponding to the first gray scale and the negative-polarity data voltage corresponding to the second gray scale can be determined.
(vi) Outputting a positive-polarity data voltage and a negative-polarity data voltage to the pixel matrix 104.
Specifically, the finally obtained positive-polarity pixel voltage and negative-polarity pixel voltage symmetrical with Vcom are input to each sub-pixel to complete display of the pixel matrix. For example, when transmitting the image of the Nth frame, a certain sub-pixel drives the display of the pixel matrix according to the positive-polarity data voltage. Accordingly, when the N+1th frame image is transmitted, the sub-pixel drives the display of the pixel matrix according to the negative-polarity data voltage.
In summary, the ghost relieving method provided by the embodiment obtains the positive-polarity data voltage and the negative-polarity data voltage by processing the input gray scale of the pixel matrix to drive the display of the pixel matrix. Compared with the existing positive-polarity pixel voltage and negative-polarity pixel voltage obtained by adjusting the Vcom voltage, the embodiment can accurately control the area of the entire pixel matrix to achieve optimal pixel voltage symmetry. Finally, the problem of ghost of the display panel is solved.
Please refer to
Step 1, acquiring input gray scales;
Step 2, acquiring first gray scales and second gray scales according to the input gray scales, wherein the first gray scales are, for example, a positive gray scale, and the second gray scales are, for example, a negative gray scale;
Step 3, acquiring corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales, wherein the first voltages are, for example, a positive data voltage, and the second gray scales are, for example, a negative data voltage; and
Step 4, outputting the first voltages and the second voltages to a pixel matrix.
Further, the step 2 may include:
establishing a lookup table for sub-pixels at predetermined positions;
determining whether a sub-pixel to be displayed corresponding to one of the input gray scales is the sub-pixel at the predetermined position;
if yes, searching the lookup table according to the input gray scale of the sub-pixel to be displayed, and determining the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed;
if not, calculating the first gray scale and the second gray scale corresponding to the sub-pixel to be displayed by using an interpolation algorithm according to the lookup table.
Further, the step of establishing a lookup table for sub-pixels at predetermined positions may include:
selecting the sub-pixels at the predetermined positions;
determining input gray scales, first gray scales, and second gray scales corresponding to the sub-pixels at the predetermined positions; and
storing the input gray scales, the first gray scales, and the second gray scales and thereby forming the lookup table.
Further, before the step 3, the method further includes:
performing frame rate control according to the first gray scales and the second gray scales.
Further, before the step 3, the method further includes:
performing dithering according to the first gray scales and the second gray scales.
For specific details of the foregoing various steps in this embodiment, reference may be made to the descriptions of the foregoing embodiments in relation to
Further, the embodiment further provides a ghost relieving apparatus suitable for a display panel, including:
a signal input module, configured to acquire input gray scales;
a gray scale processing module, configured to acquire first gray scales and second gray scales according to the input gray scales;
a voltage conversion module, configured to acquire corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales; and
a signal output module, configured to output the first voltages and the second voltages to a pixel matrix.
The gray scale processing module includes:
a lookup table establishing unit, configured to establish a lookup table for sub-pixels at predetermined positions; and
a sub-pixel determining unit, configured to determine whether current sub-pixels of the liquid crystal display device to be displayed corresponding to the input gray scales are a selected number of the sub-pixels at the predetermined positions; if yes, the lookup table is searched according to the input gray scales of the sub-pixel to be displayed thereby determine the first gray scales and the second gray scales corresponding to the sub-pixel to be displayed; if not, the first gray scales and the second gray scales corresponding to the sub-pixel to be displayed are calculated by using an interpolation algorithm according to the lookup table.
The lookup table establishing unit is configured to select a plurality of sub-pixels at the predetermined positions, determine the input gray scales, the first gray scales and the second gray scales corresponding to the sub-pixels at the predetermined positions, and store the input gray scales, the first gray scales and the second gray scales to form the lookup table.
The ghost relieving apparatus further includes a frame rate control module, configured to perform frame rate control according to the first gray scales and the second gray scales before the voltage conversion module acquires corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales.
The ghost relieving apparatus further includes a dithering module configured to perform dithering according to the first gray scales and the second gray scales before the voltage conversion module acquires corresponding first voltages according to the first gray scales and corresponding second voltages according to the second gray scales.
In summary, the ghost relieving method and the ghost relieving apparatus provided in this embodiment can accurately control the voltage symmetry of the entire pixel matrix by converting the input gray scales of the sub-pixels in the pixel matrix into two gray scales (e.g. positive gray scale and negative gray scale), thereby solving the ghost problem of the display panel.
In addition, it can be understood that the foregoing embodiments are merely illustrative of the present invention. The technical solutions of the various embodiments may be combined and used in any combination without departing from the technical features of the present invention.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions described in the foregoing embodiments may be modified or equivalently substituted for some of the technical features. The modifications and substitutions of the present invention do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810402268.6 | Apr 2018 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6750839 | Hogan | Jun 2004 | B1 |
| 20050024309 | Yamazaki | Feb 2005 | A1 |
| 20070262938 | Kim | Nov 2007 | A1 |
| 20070268233 | Hashimoto | Nov 2007 | A1 |
| 20100085387 | Kim | Apr 2010 | A1 |
| 20110134092 | Lee | Jun 2011 | A1 |
| 20150145758 | Lee | May 2015 | A1 |
| 20170061906 | Lee | Mar 2017 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20190333458 A1 | Oct 2019 | US |
