Patent Application
20170213512
The present invention relates to a display technology field, and more particularly to a GOA circuit based on oxide semiconductor thin film transistor.
The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field.
The Active Matrix Liquid Crystal Display (AMLCD) is the most common liquid crystal display device at present. The Active Matrix Liquid Crystal Display comprises a plurality of pixels, and each pixel is electrically coupled to a Thin Film Transistor (TFT). The gate (Gate) of the TFT is coupled to the horizontal scan line. The drain (Drain) of the TFT is coupled to the data line of the vertical direction. The source (Source) of the TFT is coupled to the pixel electrode. The enough voltage is applied to the level scan line, and all the TFTs electrically coupled to the horizontal scan line are activated. Thus, the signal voltage on the data line can be written into the pixel to control the transmittances of different liquid crystals to achieve the effect of controlling colors and brightness. The GOA (Gate Driver on Array) technology utilizes the array (Array) manufacture process of the thin film transistor liquid crystal display panel according to prior art to manufacture the driving circuit of gate row scan on the TFT array substrate for realizing the driving way of scanning the gates row by row. The GOA technology can reduce the bonding procedure of the external Integrated Circuit (IC) and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products. Indium Gallium Zinc Oxide (IGZO) is an amorphous oxide containing Indium, Gallium and Zinc, and the carrier mobility is 20-30 times of the amorphous silicon thin film transistor, which is capable of magnificently raising the charging/discharging rate of TFT to the pixel electrodes to promote the response speed of the pixels and to realize faster refreshing rate. In the mean time, the line scan rate of the pixels also can be significantly promoted to make the production of the flat panel display with ultra high resolution possible. Besides the amount reduction of the transistors raise the transmission of each pixel. The IGZO display possesses higher efficiency level and the efficiency becomes higher.
With the development of the oxide semiconductor thin film transistor, such as IGZO, the peripheral circuit around the panel based on oxide semiconductor thin film transistor also becomes the focus that people pay lots of attentions. The oxide semiconductor thin film transistor has higher carrier mobility but the threshold voltage thereof is about 0V and the subthreshold range swing is smaller, the voltage Vgs between the gate and the source of many TFT elements as the GOA circuit is in off state generally is 0V. Thus, the design difficulty of the GOA circuit based on the oxide semiconductor thin film transistor will be increased. There will be some function issues happening when the design adaptable to the scan driving circuit for the amorphous silicon semiconductors is applied to the GOA circuit based on the oxide semiconductor thin film transistor. Besides, due to some external factor inductions and the stress effect, there will be a tendency that the threshold voltage diminishes toward minus value to the oxide semiconductor thin film transistor, which may directly result in malfunction of the GOA circuit for the oxide semiconductor thin film transistors. For example, at high temperature, the threshold voltage of the oxide semiconductor thin film transistor will move toward minus value to result in failure of the GOA circuit; similarly, under the function electrical stress function of light irradiation, the threshold voltage of the oxide semiconductor thin film transistor will move toward minus value. Therefore, the influence of the threshold voltage of TFT has to be considered as designing the GOA circuit based on oxide semiconductor thin film transistor.
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An objective of the present invention is to provide a GOA circuit based on oxide semiconductor thin film transistor, capable of preventing that the pull-down holding module cannot be normally deactivated due to that the threshold voltage is forward biased for ensuring normal output of the GOA circuit.
For realizing the aforesaid objective, the present invention provides a GOA circuit based on oxide semiconductor thin film transistor, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module, a pull-up module, a transmission module, a first pull-down module, a bootstrap capacitor module and a pull-down holding module;
N is set to be a positive integer and except the GOA unit circuit of the first stage, in the GOA unit circuit of the Nth stage:
the pull-up controlling module comprises an eleventh thin film transistor, and a gate of the eleventh thin film transistor receives a stage transfer signal of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to a constant high voltage level, and a drain is electrically coupled to a first node;
the pull-up module comprises: a twenty-first thin film transistor, and a gate of the twenty-first thin film transistor is electrically coupled to the first node, and a source is electrically coupled to an mth clock signal, and a drain is electrically coupled to a scan driving signal;
the transmission module comprises: a twenty-second thin film transistor, and a gate of the twenty-second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the mth clock signal, and a drain outputs the stage transfer signal;
the first pull-down module comprises: a fortieth thin film transistor, and both a gate and a source of the fortieth thin film transistor are electrically coupled to the first node, and a drain is electrically coupled to the drain of a forty-first thin film transistor; a forty-first thin film transistor, and a gate of the forty-first thin film transistor is electrically coupled to an m+2th clock signal, and a source is electrically coupled to the drain of the fortieth thin film transistor, and a source receives the scan driving signal;
the bootstrap capacitor module comprises a capacitor, and one end of the capacitor is electrically coupled to the first node, and the other end is electrically coupled to the scan driving signal;
the pull-down holding module at least comprises: a fifty-first thin film transistor, and both a gate and a source of the fifty-first thin film transistor are electrically coupled to the constant high voltage level, and a drain is electrically coupled to a fourth node; a fifty-second thin film transistor, and a gate of the fifty-second thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the fourth node, and a source is electrically coupled to the first negative voltage level; a fifty-third thin film transistor, and a gate of the fifty-third thin film transistor is electrically coupled to the fourth node, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the second node; a fifty-fourth thin film transistor, and a gate of the fifty-fourth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the second node, and a drain is electrically coupled to a fifth node; a seventy-third thin film transistor, and a gate of the seventy-third thin film transistor is electrically coupled to the fourth node, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the fifth node; a seventy-fourth thin film transistor, and a gate of the seventy-fourth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a constant low voltage level, and a drain is electrically coupled to the fifth node; a fifty-fifth thin film transistor, and a gate of the fifty-fifth thin film transistor receives the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to the fourth node, and a drain is electrically coupled to a first negative voltage level; a forty-second thin film transistor, and a gate of the forty-second thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the first node, and a drain is electrically coupled to the third node; a thirty-second thin film transistor, and a gate of the thirty-second thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the scan driving signal, and a drain is electrically coupled to the first negative voltage level; a seventy-fifth thin film transistor, and a gate of the seventy-fifth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the third node, and a drain is electrically coupled to the constant high voltage level; a seventy-sixth thin film transistor, and a gate of the seventy-sixth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the third node, and a drain is electrically coupled to the constant low voltage level;
the constant low voltage level is lower than the first negative voltage level;
all the thin film transistors in the GOA unit circuits of all stages are oxide semiconductor thin film transistors.
The pull-down holding module further comprises: a fifty-sixth thin film transistor, and a gate of the fifty-sixth thin film transistor receives the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage, and a source is coupled to the fifth node, and a drain is electrically coupled to the constant low voltage level.
The pull-down holding module further comprises: a fifty-sixth thin film transistor, and a gate of the fifty-sixth thin film transistor receives the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage, and a source is coupled to the fifth node, and a drain is electrically coupled to the constant low voltage level; a fifty-seventh thin film transistor, and a gate of the fifty-seventh thin film transistor receives the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage, and a source is coupled to the second node, and a drain is electrically coupled to the fifth node.
In the GOA unit circuit of the first stage of the GOA circuit based on oxide semiconductor thin film transistor, the gate of the eleventh thin film transistor receives a scan activation signal, and a gate of the fifty-fifth thin film transistor receives a scan activation signal.
In the GOA unit circuit of the first stage of the GOA circuit based on oxide semiconductor thin film transistor, the gate of the eleventh thin film transistor receives a scan activation signal, and a gate of the fifty-fifth thin film transistor receives a scan activation signal, and a gate of the fifty-sixth thin film transistor receives a scan activation signal.
In the GOA unit circuit of the first stage of the GOA circuit based on oxide semiconductor thin film transistor, the gate of the eleventh thin film transistor receives a scan activation signal, and a gate of the fifty-fifth thin film transistor receives a scan activation signal, and a gate of the fifty-sixth thin film transistor receives a scan activation signal, and a gate of the fifty-seventh thin film transistor receives a scan activation signal.
In the pull-down holding module, the fifty-first thin film transistor, the fifty-second thin film transistor, the fifty-third thin film transistor, the fifty-fourth thin film transistor, the seventy-third thin film transistor, and the seventy-fourth thin film transistor construct a dual inverter, and the fifty-first thin film transistor, the fifty-second thin film transistor, the fifty-third thin film transistor and the fifty-fourth thin film transistor construct a main inverter, and the seventy-third thin film transistor, and the seventy-fourth thin film transistor construct an auxiliary inverter.
The clock signal comprises four clock signals: a first clock signal, a second clock signal, a third clock signal and a fourth clock signal.
As the mth clock signal is the third clock signal, the m+2th clock signal is the first clock signal, and as the mth clock signal is the fourth clock signal, the m+2th clock signal is the second clock signal.
All the thin film transistors in the GOA unit circuits of all stages are IGZO thin film transistors.
The present invention further provides a GOA circuit based on oxide semiconductor thin film transistor, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module, a pull-up module, a transmission module, a first pull-down module, a bootstrap capacitor module and a pull-down holding module;
N is set to be a positive integer and except the GOA unit circuit of the first stage, in the GOA unit circuit of the Nth stage:
the pull-up controlling module comprises an eleventh thin film transistor, and a gate of the eleventh thin film transistor receives a stage transfer signal of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to a constant high voltage level, and a drain is electrically coupled to a first node;
the pull-up module comprises: a twenty-first thin film transistor, and a gate of the twenty-first thin film transistor is electrically coupled to the first node, and a source is electrically coupled to an mth clock signal, and a drain is electrically coupled to a scan driving signal;
the transmission module comprises: a twenty-second thin film transistor, and a gate of the twenty-second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the mth clock signal, and a drain outputs the stage transfer signal;
the first pull-down module comprises: a fortieth thin film transistor, and both a gate and a source of the fortieth thin film transistor are electrically coupled to the first node, and a drain is electrically coupled to the drain of a forty-first thin film transistor; a forty-first thin film transistor, and a gate of the forty-first thin film transistor is electrically coupled to an m+2th clock signal, and a source is electrically coupled to the drain of the fortieth thin film transistor, and a source receives the scan driving signal;
the bootstrap capacitor module comprises a capacitor, and one end of the capacitor is electrically coupled to the first node, and the other end is electrically coupled to the scan driving signal;
the pull-down holding module at least comprises: a fifty-first thin film transistor, and both a gate and a source of the fifty-first thin film transistor are electrically coupled to the constant high voltage level, and a drain is electrically coupled to a fourth node; a fifty-second thin film transistor, and a gate of the fifty-second thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the fourth node, and a source is electrically coupled to the first negative voltage level; a fifty-third thin film transistor, and a gate of the fifty-third thin film transistor is electrically coupled to the fourth node, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the second node; a fifty-fourth thin film transistor, and a gate of the fifty-fourth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the second node, and a drain is electrically coupled to a fifth node; a seventy-third thin film transistor, and a gate of the seventy-third thin film transistor is electrically coupled to the fourth node, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the fifth node; a seventy-fourth thin film transistor, and a gate of the seventy-fourth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a constant low voltage level, and a drain is electrically coupled to the fifth node; a fifty-fifth thin film transistor, and a gate of the fifty-fifth thin film transistor receives the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to the fourth node, and a drain is electrically coupled to a first negative voltage level; a forty-second thin film transistor, and a gate of the forty-second thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the first node, and a drain is electrically coupled to the third node; a thirty-second thin film transistor, and a gate of the thirty-second thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the scan driving signal, and a drain is electrically coupled to the first negative voltage level; a seventy-fifth thin film transistor, and a gate of the seventy-fifth thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the third node, and a drain is electrically coupled to the constant high voltage level; a seventy-sixth thin film transistor, and a gate of the seventy-sixth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the third node, and a drain is electrically coupled to the constant low voltage level;
the constant low voltage level is lower than the first negative voltage level;
all the thin film transistors in the GOA unit circuits of all stages are oxide semiconductor thin film transistors;
wherein the clock signal comprises four clock signals: a first clock signal, a second clock signal, a third clock signal and a fourth clock signal;
wherein as the mth clock signal is the third clock signal, the m+2th clock signal is the first clock signal, and as the mth clock signal is the fourth clock signal, the m+2th clock signal is the second clock signal;
wherein all the thin film transistors in the GOA unit circuits of all stages are IGZO thin film transistors.
The benefits of the present invention are: the present invention provides a GOA circuit based on oxide semiconductor thin film transistor. By adding the fifty-fifth, fifty-sixth, fifty-seventh thin film transistors respectively corresponding to the fourth, fifth, second nodes in the pull-down holding module, all the gates of the fifty-fifth, fifty-sixth, fifty-seventh thin film transistors receive the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage. The fifty-fifth, fifty-sixth, fifty-seventh thin film transistors are controlled with the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage to pull down the voltage levels of the fourth, fifth, second nodes under circumstance that the first node is not completely boosted to rapidly deactivate the pull-down holding module for ensuring the normal boost of the voltage level of the first node. The first node is guaranteed to be high voltage level in the functioning period, and thus, the normal output of the GOA circuit is ensured.
In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention.
In drawings,
For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments.
The present invention provides a GOA circuit based on oxide semiconductor thin film transistor. Please refer to
N is set to be a positive integer and except the GOA unit circuit of the first stage, in the GOA unit circuit of the Nth stage:
the pull-up controlling module 100 comprises: an eleventh thin film transistor T11, and a gate of the eleventh thin film transistor T11 receives a stage transfer signal ST(N-1) of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to a constant high voltage level DCH, and a drain is electrically coupled to a first node Q(N).
The pull-up module 200 comprises: a twenty-first thin film transistor T21, and a gate of the twenty-first thin film transistor T21 is electrically coupled to the first node Q(N), and a source is electrically coupled to an mth clock signal CK(m), and a drain outputs a scan driving signal G(N).
The pull-down module 300 comprises: a twenty-second thin film transistor T22, and a gate of the twenty-second thin film transistor T22 is electrically coupled to the first node Q(N), and a source is electrically coupled to the mth clock signal CK(m), and a drain outputs the stage transfer signal ST(N).
Specifically, the clock signal comprises four clock signals: a first clock signal CK(1), a second clock signal CK(2), a third clock signal CK(3) and a fourth clock signal CK(4).
As the mth clock signal CK(m) is the third clock signal CK(3), the m+2th clock signal CK(m+2) is the first clock signal CK(1), and as the mth clock signal CK(m) is the fourth clock signal CK(4), the m+2th clock signal CK(m+2) is the second clock signal CK(2).
The first pull-down module 400 comprises: a fortieth thin film transistor T40, and both a gate and a source of the fortieth thin film transistor T40 are electrically coupled to the first node Q(N), and a drain is electrically coupled to the drain of a forty-first thin film transistor T41; the forty-first thin film transistor T41, and a gate of the forty-first thin film transistor T41 is electrically coupled to an m+2th clock signal CK(m+2), and a source is electrically coupled to the scan driving signal G(N).
The bootstrap capacitor module 500 comprises: a capacitor Cb, and one end of the capacitor Cb is electrically coupled to the first node Q(N), and the other end is electrically coupled to the scan drive signal G(N).
The pull-down holding module 600 comprises: a fifty-first thin film transistor T51, and both a gate and a source of the fifty-first thin film transistor T51 are electrically coupled to the constant high voltage level DCH, and a drain is electrically coupled to a fourth node S(N); a fifty-second thin film transistor T52, and a gate of the fifty-second thin film transistor T52 is electrically coupled to the first node Q(N), and a drain is electrically coupled to the fourth node S(N), and a source is electrically coupled to the first negative voltage level VSS; a fifty-third thin film transistor T53, and a gate of the fifty-third thin film transistor T53 is electrically coupled to the fourth node S(N), and a source is electrically coupled to the constant high voltage level DCH, and a drain is electrically coupled to the second node P(N); a fifty-fourth thin film transistor T54, and a gate of the fifty-fourth thin film transistor T54 is electrically coupled to the first node Q(N), and a source is electrically coupled to the second node P(N), and a drain is electrically coupled to a fifth node K(N); a seventy-third thin film transistor T73, and a gate of the seventy-third thin film transistor T73 is electrically coupled to the fourth node S(N), and a source is electrically coupled to the constant high voltage level DCH, and a drain is electrically coupled to the fifth node K(N); a seventy-fourth thin film transistor T74, and a gate of the seventy-fourth thin film transistor T74 is electrically coupled to the first node Q(N), and a source is electrically coupled to a constant low voltage level DCL, and a drain is electrically coupled to the fifth node K(N); a fifty-fifth thin film transistor T55, and a gate of the fifty-fifth thin film transistor T55 receives the stage transfer signal ST(N-1) of the GOA unit circuit of the former N−1th stage, and a source is electrically coupled to the fourth node S(N), and a drain is electrically coupled to the first negative voltage level VSS; a forty-second thin film transistor T42, and a gate of the forty-second thin film transistor T42 is electrically coupled to the second node P(N), and a source is electrically coupled to the first node Q(N), and a drain is electrically coupled to the third node T(N); a thirty-second thin film transistor T32, and a gate of the thirty-second thin film transistor T32 is electrically coupled to the second node P(N), and a source is electrically coupled to the scan driving signal G(N), and a drain is electrically coupled to the first negative voltage level VSS; a seventy-fifth thin film transistor T75, and a gate of the seventy-fifth thin film transistor T75 is electrically coupled to the first node Q(N), and a source is electrically coupled to the third node T(N), and a drain is electrically coupled to the constant high voltage level DCH; a seventy-sixth thin film transistor T76, and a gate of the seventy-sixth thin film transistor T76 is electrically coupled to the second node P(N), and a source is electrically coupled to the third node T(N), and a drain is electrically coupled to the constant low voltage level DCL.
Specifically, the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, the fifty-fourth thin film transistor T54, the seventy-third thin film transistor T73, and the seventy-fourth thin film transistor T74 construct a dual inverter F1, and the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53 and the fifty-fourth thin film transistor T54 construct a main inverter, and the seventy-third thin film transistor T73, and the seventy-fourth thin film transistor T74 construct an auxiliary inverter. The constant low voltage level DCL is lower than the first negative voltage level VSS. All the thin film transistors in the GOA unit circuits of all stages are oxide semiconductor thin film transistors. Preferably, the oxide semiconductor thin film transistors are IGZO thin film transistors.
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In the first embodiment, the fifty-fifth thin film transistor T55 is added for the key node, the fourth node S(N) of the pull-down holding module 600. The fifty-fifth thin film transistor T55 is controlled by the stage transfer signal ST(N-1) of the GOA unit circuit of the former N−1th stage to pull down the voltage level of the fourth node S(N) to the first negative voltage level VSS, and thus, to accomplish the voltage pull-down to the fourth node S(N) under circumstance that the first node Q(N) is not completely boosted to rapidly deactivate the pull-down holding module 600. It can prevent that the voltage level of the fourth node S(N) cannot be pulled down to deactivate the pull-down holding module 600 under circumstance that the first node Q(N) is not completely boosted because the threshold voltage of the fifty-fifth thin film transistor T55 is forward biased. Accordingly, the voltage level of first node Q(N) cannot be normally boosted up, and that the voltage level of first node Q(N) cannot be normally boosted up makes that the pull-down holding module 600 cannot be normally deactivated. Ultimately, the issue of the bad performance of the entire GOA circuit occurs thereby.
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In conclusion, the present invention provides a GOA circuit based on oxide semiconductor thin film transistor. By adding the fifty-fifth, fifty-sixth, fifty-seventh thin film transistors respectively corresponding to the fourth, fifth, second nodes in the pull-down holding module, all the gates of the fifty-fifth, fifty-sixth, fifty-seventh thin film transistors receive the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage. The fifty-fifth, fifty-sixth, fifty-seventh thin film transistors are controlled with the stage transfer signal of the GOA unit circuit of the former N−1th stage or the scan driving signal of the GOA unit circuit of the former N−1th stage to pull down the voltage levels of the fourth, fifth, second nodes under circumstance that the first node is not completely boosted to rapidly deactivate the pull-down holding module for ensuring the normal boost of the voltage level of the first node. The first node is guaranteed to be high voltage level in the functioning period, and thus, the normal output of the GOA circuit is ensured.
Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510310266.0 | Jun 2015 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2015/082010 | 6/23/2015 | WO | 00 |
