Patent Grant
10636376
The present application is a National Phase of International Application Number PCT/CN2017/113733, filed on Nov. 30, 2017, and claims the priority of China Application No. 201711147117.2, filed on Nov. 17, 2017.
The disclosure relates to a display technical field, and more particularly to a GOA circuit.
Currently, the liquid crystal display device has been widely used as a display component of electronic devices in various electronic products. The GOA (Gate Driver On Array) circuit is an important part of a liquid crystal display device. The GOA circuit is a technique using the existed process of manufacturing thin film transistor liquid crystal display array to manufacture a gate line scan driving signal circuit on an array substrate to realize a driving method scanning each gate line in sequence.
In accordance with TFT (Thin Film Transistor) type used in a display panel, the display panel based on LTPS (Low Temperature Poly-silicon) technique could be divided into NMOS type panel, PMOS type panel and CMOS type panel having both NMOS type and PMOS type. Similarly, the GOA circuit is divided into NMOS circuit, PMOS circuit and CMOS circuit. Comparing with the CMOS circuit, the NMOS circuit is helpful in increasing yield rate and decreasing cost because masks and procedures for manufacturing a PP (P doping, or Phosphorus ion doping) layer could be saved. Therefore, development of a stable NMOS circuit is a realistic need of this industry. When power is turned off abnormally and the NMOS type GOA circuit cannot effectively achieve the function of All Gate ON (that is, setting all the gate driving signals in the GOA circuit to be enabled to simultaneously scan the liquid crystal display panel), image sticking occurs on the display panel.
Taking forward scanning as an example and assuming that the (n+1)th clock signal received by the TFT NT3 is at high potential at the time when abnormal power off occurs in the GOA circuit shown in
In order to solve problems of the technique mentioned above, the present invention provides a GOA circuit for eliminating image sticking generated when power of the liquid crystal display panel is turned off abnormally to improve user experiences.
The present invention provides a GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: an output control module, a forward-reverse scan control module, a first pull-down circuit, a second pull-down circuit and a pull-up circuit, wherein m≥n≥1;
Preferably, the GOA unit further comprises a voltage stabilizing circuit;
Preferably, the forward-reverse scan control module comprises a first TFT and a second TFT;
Preferably, the third terminal of the third TFT receives a (n+1)th clock signal, and the third terminal of the fourth TFT receives a (n−1)th clock signal.
Preferably, the GOA circuit comprises 4 clock signals comprising a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein, the (n+1)th clock signal is the first clock signal when the nth clock signal is the fourth clock signal, and the (n−1)th clock signal is the fourth clock signal when the nth clock signal is the first clock signal.
Preferably, the GOA unit further comprises a first capacitor, a second capacitor and a tenth TFT;
Preferably, the GOA unit further comprises a twelfth TFT and an eleventh TFT;
Preferably, all the TFT's in the GOA unit are N-channel TFT's.
Preferably, all the clock signals are high potential after power of the liquid crystal display panel is turned off.
The present invention further provides a GOA circuit, which is used in a liquid crystal display panel, comprising m cascaded GOA units, wherein a nth-stage GOA unit comprises: an output control module, a forward-reverse scan control module, a first pull-down circuit, a second pull-down circuit and a pull-up circuit, wherein m≥n≥1;
Preferably, the forward-reverse scan control module comprises a first TFT and a second TFT;
Preferably, the third terminal of the third TFT receives a (n+1)th clock signal, and the third terminal of the fourth TFT receives a (n−1)th clock signal.
Preferably, the GOA circuit comprises 4 clock signals comprising a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, wherein, the (n+1)th clock signal is the first clock signal when the nth clock signal is the fourth clock signal, and the (n−1)th clock signal is the fourth clock signal when the nth clock signal is the first clock signal.
Preferably, the GOA unit further comprises a first capacitor, a second capacitor and a tenth TFT;
Preferably, the GOA unit further comprises a twelfth TFT and an eleventh TFT;
Preferably, all the TFT's in the GOA unit are N-channel TFT's.
Preferably, all the clock signals are high potential after power of the liquid crystal display panel is turned off.
Benefits of the present invention are as follows: The fifth TFT NT5 is turned off by the forward scan control signal U2D and the reverse scan control signal D2U, the high potential signal VGH is prevented from flowing into the seventh TFT NT7, and the low potential signal VGL flows into the gate of the seventh TFT NT7 through the eighth TFT NT8 to turn off the seventh TFT NT7 to prevent the nth gate driving signal G(n) from being pulled down by the low potential signal VGL. At the same time, because the forward scan control signal U2D and the reverse scan control signal D2U are both low potential, the first global control signal GAS1 is set to be high potential to turn on the thirteenth TFT NT13 to pull up the nth gate driving signal G(n) so that the potential of the nth gate driving signal G(n) is prevented from being too low to effectively turn on the TFT of the pixel unit.
Therefore, the present application could fully turn on the pixels of the liquid crystal display panel so that the charges on the pixel electrodes could be released in time and conducted through the data lines of the liquid crystal display panel to eliminate image sticking generated when power of the liquid crystal display panel is turned off to improve user experiences.
In order to make the descriptions of the technique solutions of the embodiments of the present invention or the existed techniques be clearer, the drawings necessary for describing the embodiments or the existed techniques are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and, for those with ordinary skill in this field, other drawings can be obtained from the drawings described below without creative efforts.
The present invention provides a GOA circuit, which is used in a liquid crystal display panel. The GOA circuit comprises m cascaded GOA units. As shown in
The forward-reverse scan control module 300 is used for controlling the GOA circuit to perform a forward scanning or a reverse scanning in accordance with a forward scan control signal U2D or a reverse scan control signal D2U.
The output control module 100 is connected to the forward-reverse scan control module 300 to output a nth gate driving signal G(n) in a duration performing the forward scanning or the reverse scanning by the GOA circuit.
The first pull-down circuit 200 comprises a seventh TFT NT7, a first terminal of the seventh TFT NT7 is connected to the output control module 100, and a second terminal of the seventh TFT NT7 receives a low potential signal VGL.
The second pull-down circuit 500 comprises a third TFT NT3, a fourth TFT NT4 and a fifth TFT NTS. A first terminal of the third TFT NT3 receives the forward scan control signal U2D, a first terminal of the fourth TFT NT4 receives the reverse scan control signal D2U, a second terminal of the third TFT NT3 and a second terminal of the fourth TFT NT4 are connected to a third terminal of the fifth TFT NTS, a third terminal of the third TFT NT3 and a third terminal of the fourth TFT NT4 receive a clock signal, respectively, and the clock signals turn on the third TFT NT3 and the fourth TFT NT4 after power of the liquid crystal display panel is turned off.
A first terminal of the fifth TFT NT5 receives a high potential signal VGH, and a second terminal of the fifth TFT NT5 is connected to a third terminal of the seventh TFT NT7.
The pull-up circuit 400 comprises an eighth TFT NT8 and a thirteenth TFT NT13. A first terminal of the eighth TFT NT8 is connected to the third terminal of the seventh TFT NT7, a second terminal of the eighth TFT NT8 receives the low potential signal VGL, and a third terminal of the eighth TFT NT8 receives a first global control signal GAS1.
A first terminal and a third terminal of the thirteenth TFT NT13 are both connected to the third terminal of the eighth TFT NT8, and a second terminal of the thirteenth TFT NT13 is connected to the first terminal of the seventh TFT NT7.
Wherein, the first terminal is one of source and drain, the second terminal is another one of source and drain, the third terminal is gate, and, after power of the liquid crystal display panel is turned off, the forward scan control signal U2D and the reverse scan control signal D2U are both low potential and the first global control signal GAS1 is high potential.
Furthermore, the GOA unit further comprises a voltage stabilizing circuit 600. The voltage stabilizing circuit 600 comprises a ninth TFT NT9, and the output control module 100 comprises a sixth TFT NT6.
A third terminal of the ninth TFT NT9 receives the high potential signal VGH, a second terminal of the ninth TFT NT9 is connected to a third terminal of the sixth TFT NT6, and a first terminal of the ninth TFT NT9 is connected to the forward-reverse scan control module 300.
A first terminal of the sixth TFT NT6 receives a nth clock signal CK(n), a second terminal of the sixth TFT NT6 is connected to the first terminal of the seventh TFT NT7, and a point connecting the sixth TFT NT6 and the seventh TFT NT7 is used as an output terminal for outputting the nth gate driving signal G(n).
Furthermore, the forward-reverse scan control module 300 comprises a first TFT NT1 and a second TFT NT2.
A first terminal of the first TFT NT1 receives the forward scan control signal U2D, and a second terminal of the first TFT NT1 is connected to the first terminal of the ninth TFT NT9.
A first terminal of the second TFT NT2 receives the reverse scan control signal D2U, and a second terminal of the second TFT NT2 is connected to the second terminal of the first TFT NT1.
Wherein, the third terminal of the first TFT NT1 receives a (n−2)th gate driving signal G(n−2) when n>2, and receives a scan start-up signal when n≤2.
The third terminal of the second TFT NT2 receives a (n+2)th gate driving signal G(n+2) when n≤m−2, and receives the scan start-up signal when n>m−2.
The scan start-up signal is high potential after power of the liquid crystal display panel is turned off.
Furthermore, the third terminal of the third TFT NT3 receives a (n+1)th clock signal CK(n+1), and the third terminal of the fourth TFT NT4 receives a (n−1)th clock signal CK(n−1).
Furthermore, the GOA circuit comprises 4 clock signals comprising a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The (n+1)th clock signal CK(n+1) is the first clock signal when the nth clock signal CK(n) is the fourth clock signal, and the (n−1)th clock signal CK(n−1) is the fourth clock signal when the nth clock signal CK(n) is the first clock signal.
When the second pull-down 500 of the nth-stage GOA unit receives the first clock signal and the third clock signal, the second pull-down 500 of the (n+1)th-stage GOA unit would receive the second clock signal and the fourth clock signal. Therefore, the nth-stage GOA unit and the (n+1)th-stage GOA unit compose a GOA repeating unit.
Furthermore, the GOA unit further comprises a first capacitor, a second capacitor and a tenth TFT NT10.
A third terminal of the tenth TFT NT10 is connected to the second terminal of the fifth TFT NTS, a first terminal of the tenth TFT NT10 is connected to the first terminal of the ninth TFT NT9 and a second terminal of the tenth TFT NT10 receives the low potential signal VGL.
One terminal of the first capacitor is connected to the first terminal of the ninth TFT NT9 and another terminal of the first capacitor receives the low potential signal VGL.
One terminal of the second capacitor is connected to the third terminal of the seventh TFT NT7 and another terminal of the second capacitor is connected to the second terminal of the seventh TFT NT7.
Furthermore, the GOA unit further comprises a twelfth TFT NT12 and an eleventh TFT NT11.
A third terminal of the twelfth TFT NT12 is connected to the second terminal of the first TFT NT1 and the second terminal of the second TFT NT2, a second terminal of the twelfth TFT NT12 receives the low potential signal VGL, and a first terminal of the twelfth TFT NT12 is connected to the third terminal of the seventh TFT NT7.
A third terminal and a second terminal of the eleventh TFT NT11 are connected together to receive a reset signal Reset, and a first terminal of the eleventh TFT NT11 is connected to the third terminal of the seventh TFT NT7.
Furthermore, all the TFT's in the GOA unit are N-channel TFT's. Specifically, all the TFT's from the first TFT NT1 to the thirteenth TFT NT13 are N-channel TFT's.
Furthermore, all the clock signals are high potential after power of the liquid crystal display panel is turned off.
When power of the liquid crystal display panel is turned off, timings of the signals are shown in
As shown in
The GOA circuit in the present invention could utilize not only the forward scan status of the liquid crystal display panel (i.e., the forward scan control signal U2D is high potential and the reverse scan control signal U2D is low potential) but also the reverse scan status (i.e., the forward scan control signal U2D is low potential and the reverse scan control signal U2D is high potential), the TFT's of the pixel units could be turned on line-by-line, and the All Gate ON function could be achieved under the situation that the power of the liquid crystal display panel is turned off abnormally.
In summary, after power of the liquid crystal display panel is turned off, the fifth TFT NT5 is turned off by the forward scan control signal U2D and the reverse scan control signal D2U so that the high potential signal VGH is prevented from flowing into the seventh TFT NT7, and the low potential signal VGL flows into the gate of the seventh TFT NT7 through the eighth TFT NT8 to turn off the seventh TFT NT7 to prevent the nth gate driving signal G(n) from being pulled down by the low potential signal VGL. At the same time, because the forward scan control signal U2D and the reverse scan control signal D2U are both low potential, the first global control signal GAS1 is set to be high potential to turn on the thirteenth TFT NT13 to pull up the nth gate driving signal G(n) so that the potential of the nth gate driving signal G(n) is prevented from being too low to effectively turn on the TFT of the pixel unit.
Therefore, the present application could fully turn on the pixels of the liquid crystal display panel so that the charges on the pixel electrodes could be released in time and conducted through the data lines of the liquid crystal display panel to eliminate image sticking generated when power of the liquid crystal display panel is turned off, so that user experiences are improved.
The foregoing contents are detailed description of the disclosure in conjunction with specific preferred embodiments and concrete embodiments of the disclosure are not limited to these descriptions. For the person skilled in the art of the disclosure, without departing from the concept of the disclosure, simple deductions or substitutions can be made and should be included in the protection scope of the application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017 1 1147117 | Nov 2017 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2017/113733 | 11/30/2017 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2019/095436 | 5/23/2019 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20060017681 | Jang | Jan 2006 | A1 |
| Number | Date | Country |
|---|---|---|
| 105206237 | Dec 2015 | CN |
| 105469766 | Apr 2016 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20200082777 A1 | Mar 2020 | US |
