Patent Application
20080232514
1. Field of the Invention
The invention relates to a GPS signal acquisition circuit. In particular, the GPS signal acquisition circuit only requires low memory storage to perform coherent and incoherent integrations of the GPS signals and maintain high signal sensitivity.
2. Description of Related Art
As shown in
To have high sensitivity, the input signal is over sampled and output of the matched filter correlation engine 60, as shown in
The coherent integration signals (sum1, sum2, . . . ) output by the coherent integrator 61 can be further processed by an absolute-value circuit (ABS) before being sent to an incoherent integrator 62. The absolute-value circuit ensures that the data do not cancel each other out while doing the incoherent integrations due to their positive and negative nature. As shown in the drawing, the coherent integration signals (sum1, sum2, . . . ) are accumulated by the incoherent integrator 62 to generate an incoherent integration signal. The peak signal can be readily extracted from the incoherent integration output for subsequent signal processing.
Under the above-mentioned structure, to detect weak signals contained in the over sampled data output by the matched filter correlation engine 60, either the coherent integrator 61 or the incoherent integrator 62, have to possess a high memory storage to execute the data accumulation. For example, the coherent integrator 61 has to use 4092 word×12 bit of memory. The incoherent integrator 62 has to use 4092 word×20 bit of memory.
Moreover, the signal processing of the GPS receiver often utilizes multiple sets of such search engine in parallel to speed up acquisition of weak signals. In other words, multiple groups of coherent integrators 61 and incoherent integrators 62 are used; multiple groups of large memory storage units are needed in making of a GPS receiver chip, and the cost is relatively high.
In view of the foregoing drawbacks, an objective of the invention is to reduce memory requirement in GPS signal processing while maintaining high sensitivity in signal detection. It is desirable to use only low memory storage to accomplish the coherent and incoherent integration processing for the GPS signal, and still be able to detect weak signal and its offset position.
To achieve the above-mentioned objective, the invention includes: a correlation engine, a decimator, a coherent integrator and an incoherent integrator.
The correlation engine outputs a correlation-processed GPS signal. The signal is grouped into several periodic frames. Each frame has N×1023 sampled values.
The decimator sums M samples coming out of the correlation engine and output the summed result for further processing by the coherent integrator; M is a divisor of N×1023. Then the number of samples within a frame period in the decimated output is reduced by a factor of M, and the number of words of memory required for subsequent coherent and incoherent processing is greatly reduced.
The coherent integrator performs coherent accumulation of the decimated output and generates a coherently integrated signal.
The incoherent integrator performs incoherent accumulation of the coherently integrated signals to produce an incoherently integrated signal.
By inserting a decimator between the correlation engine and the coherent integrator, the data size for subsequent computation can be greatly reduced. The coherent integrator and the incoherent integrator use a much smaller amount of memory to accomplish the data accumulation tasks. The value and position of the weak peak can still be detected.
A circuit block diagram of a first embodiment is shown in
GPS signal coming off a GPS satellite consists of 1.023 MHz pseudo-random (PN) code being modulated by 50 Hz data bit and translated to a carrier frequency of 1575.42 MHz. Each satellite has a unique PN code with period of 1023 chips. A typical GPS receiver, as shown in
Within the digital signal processing section of the GPS receiver baseband, remaining carrier frequency offset is removed and PN code offset is to be found to formulate the pseudo-range equation in order to resolve position of the GPS receiver. To detect the correct code offset, it is done traditionally using a serial correlator. The serial correlator sequentially correlates a locally generated PN code with the incoming signal. If the signal is strong, correlating for one period of PN code of 1 millisecond would generate a large value in the correlator output when phase of locally generated PN code matches the phase of same PN code embedded in the incoming signal. If the result is less than a pre-determined threshold, the locally generated PN code is shifted 1 chip and the serial correlator correlates for another PN code period of 1 millisecond repeatedly until accumulated value larger than the pre-determined threshold is found. The signal is then declared detected and the code phase offset is used to formulate pseudo-range value.
A sequential correlator typically searches for one code phase each millisecond with presence of strong signal. Since there are 1023 possible code phases with the GPS PN code, it could take up to 1.023 second to search through all 1023 code phases. When the received signal is weak, coherent integration of N millisecond is required for signal detection (N=1 . . . 10); and the search speed becomes 11N. For signal weaker than possibly detectable using coherent integration, combination of coherent integration and incoherent integration must be used; and the search process then becomes very long.
There is match-filter type of parallel correlator architecture that is capable of searching all 1023 code phases per millisecond and yielding speed up of nearly a thousand-fold. The matched filter, with the coherent integrator 61, and the incoherent integrator 62, as shown in
When the signal is weak, the correlation peak in the matched filter correlation engine output is nearly buried in noise. Since the noise in successive 1-millisecond frames is uncorrelated but the correlation peak is correlated, adding successive frames together in place and integrating coherently will reinforce the correlation peak but lower variance of the noise, which makes the correlation peak more detectable. Due to 20-millisecond data bit modulation, coherent integration processing is usually performed for up to 10 milliseconds. If the signal is still too weak to be detectable after the coherent integration processing, an incoherent integration by removing sign-effect of the data bit on the coherently summed output and adding the successive incoherent integrator output will further reinforce the correlation peak. Example showing how coherent integration and incoherent integration reinforce the weak correlation peak in the matched filter correlation engine output of
To achieve high sensitivity, the GPS signal is over sampled and correlated with over sampled version of the PN code sequence within the matched filter correlation engine, and then the over sampled correlated result is output for further processing. Over sampling by factor of 2 or 4 requires 2-times or 4-times the storage space in subsequent coherent and incoherent signal processing, which is quite significant.
To reduce subsequent memory storage requirement, output of correlation engine processed GPS signal, containing N×1023 samples per millisecond within a PN code period, is connected to a decimator 20 circuit. The decimator 20 sums M samples coming out of the correlation engine 10 and outputs the summed result for further processing by the coherent integrator 30 and the incoherent integrator 40; M is a small divisor of N×1023. Then the number of samples within a frame period in the decimated output is reduced by the factor of M, and the number of words of memory required for subsequent coherent and incoherent processing is greatly reduced.
In
With respect to
In addition to the above-mentioned accumulation method, the decimator 20 can accomplish using additional operations. For example, the accumulated result can be further divided by 2 or by 4. In such cases, the result can be represented with fewer bits. The absolute circuit 50 to remove effect of data bit modulation may also be replaced with some other equivalent circuit that removes the sign; one possibility is a squaring circuit.
In the prior art shown in
Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
