Gradient-based approach to sample-time mismatch error calibration in a two-channel time-interleaved analog-to-digital converter

Abstract

Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Description

BACKGROUND

Time-interleaved Analog-to-Digital Converters (TIADC) have received considerable attention in the recent past in applications that require very high sample rates, i.e., sample rates that cannot be achieved by a single present-day ADC. In a TIADC employing M ADCs, each ADC operates at F_S/M where F_S is the sampling rate of the TIADC. The output from each TIADC is combined at F_S using a commutator to produce a sample rate converter operating at F_S. Ideally, the slower ADCs should have the same offset, gain, and uniform sample instants. In practice, however, due to component mismatches, this requirement is difficult to achieve. The differences in the offset values of the slower ADCs produce tones at kF_S/M, for k=0, 1, 2, . . . , irrespective of the input signal. The differences in the gain values of the ADCs produce spurious (or unwanted) signals at ±F_in+kF_S/M, for k=1, 2, . . . , where F_in is any frequency of the input signal. Similarly, the non-uniformity of sampling instants of each ADC with respect to the TIADC sampling frequency produce spurious signals at exactly the same location as the spurs due to gain mismatch. However, the spurs due to the sample-time mismatch are orthogonal to those due to the gain mismatch. Consequently, the resulting spurious signals due to offset, gain and sample-time mismatches degrade the performance of the TIADC system significantly, thus making the estimation and correction of these errors imperative to improve performance.

SUMMARY

In a preferred embodiment, phase error is corrected in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by an input signal. The input signal is first converted with two Time-Interleaved Analog to Digital Converters (TIADC) cores, to provide to a set of two ADC outputs as first and second digital signals. The outputs of the TIADC cores are interleaved to form a digital converted representation of the input signal. A sample time error (also referred to as a phase error) is then estimated from the first and second digital signals. The phase correction is then carried out using the phase error estimate, irrespective of a Nyquist zone occupied by the input signal. The correction signal is then applied to a sample time correction input of at least one of the TIADC cores.

In one implementation, the correction signal is determined from a sign of the gradient of the sample time error. The sign of the gradient of the sample time error may be further processed by a filter, such as a Finite Impulse Response filter, before applying it to the phase correction input.

The approach lends itself to a mixed signal solution such that the phase error estimate can be determined digitally, but the correction signal still applied as an analog value output as from a Phase Look Up Table (PLUT). In a specific implementation, the correction signal is determined from a Phase Look Up Table (PLUT) where

${\mathrm{PLUT}}^k=N_i+\lfloor {\mu }^k\rfloor$ ${\mu }^{k+1}={\mu }^k-\mathrm{sign}\left(e_{\mathrm{phase}}^k\left(\Delta t\right)\right)\mathrm{sign}\left(m_s^k\right){\mu }_{\mathrm{phase}}^k$ $\begin{array}{c}{\mu }_{\mathrm{phase}}^{k+1}=\max \left(\frac{{\mu }_{\mathrm{phase}}^k}{2},{\mu }_{\mathrm{phasemin}}\right)\mathrm{if}\mathrm{mod}\left(k,k_p\right)\\ =0\end{array}$ where N_i is an initial address offset of the PLUT, μ^k denotes a variable at the k^th iteration, and μ_phase^k denotes a step size at the k^th iteration, μ_phase⁰=μ_phasemax, k_p is any arbitrary positive number, and e_phase(Δt_k) is an estimate of the phase error at iteration k.

Any of several known algorithms to provide the initial estimate of the phase error can be used. One such sample-time error estimator was disclosed in U.S. Pat. No. 7,839,323 entitled “Error Estimation and Correction in a Two-Channel Time Interleaved Analog to Digital Converter”, filed Apr. 7, 2009, which is hereby incorporated by reference in its entirety. Other mismatch error correction algorithms may also be used, however.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.

FIG. 1 illustrates a spectrum of an input signal occupying a first Nyquist zone.

FIG. 2 illustrates variation of e_phase(Δt) with Δt for the input signal illustrated in FIG. 1.

FIG. 3 illustrates a spectrum of an input signal occupying a second Nyquist zone.

FIG. 4 illustrates variation of e_phase(Δt) with Δt for the signal shown in FIG. 3.

FIG. 5 is a schematic of a Two-Channel Time Interleaved of sample-time mismatch correction.

FIG. 6 illustrates a block diagram of an adaptive phase error algorithm.

FIG. 7 illustrates variation of PLUT^k with iteration k when the input signal is in the first Nyquist zone.

FIG. 8 illustrates variation of PLUT^k with iteration k when the input signal is in the second Nyquist zone.

FIG. 9 illustrates variation of PLUT^k with iteration k when the input signal switches between first and second Nyquist zones.

FIG. 10 illustrates use of the TIADC in a digital transceiver.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A description of example embodiments follows. While the invention is defined solely by the claims presented at the end of this document and therefore may be susceptible to embodiment in different forms, there is shown in the drawings, and will be described herein in detail, one or more specific embodiments, with the understanding that the present disclosure is to be considered but one exemplification of the principles of the invention. It is also to be understood that there is no intent to limit the invention to that which is specifically illustrated and described herein. Therefore, any references to the “invention” which may occur in this document are to be interpreted only as a reference to one particular example embodiment of but one aspect of the invention(s) claimed.

A Time-Interleaved Analog-to-Digital Converter (TIADC) employs multiple analog-to-digital converters (ADCs) to achieve high sampling rates. Thus, in a TIADC employing M such ADCs, each ADC operates at F_S/M where F_S is the sampling rate of the TIADC. Ideally, the slower ADCs should have the same offset, gain, and uniform sample instants. In practice, however, due to component mismatches, this requirement is difficult to achieve. The differences in the offset values of the slower ADCs produce tones at kF_S/M, for k=0, 1, 2, . . . , irrespective of the input signal. The differences in the gain values of the ADCs produce spurious (or unwanted) signals at ±F_in+kF_S/M, for k=1, 2, . . . , where F_in is any frequency of the input signal. Similarly, the non-uniformity of sampling instants of each ADC with respect to the TIADC sampling frequency produce spurious signals at exactly the same location as the spurs due to gain mismatch. However, the spurs due to the sample-time mismatch are orthogonal to those due to the gain mismatch. Consequently, the resulting spurious signals due to offset, gain and sample-time mismatches degrade the performance of the TIADC system significantly, thus making the estimation and correction of these errors imperative to improve performance.

Here the focus is on a two-channel TIADC system wherein the sample-time (also referred to herein as phase) mismatch error is estimated and corrected. Expressions for the phase error have been developed wherein it is shown that the phase error produces image spurs reflected around the Nyquist frequency. In developing expressions for the phase error, it is assumed that the gain and offset mismatch errors have been corrected. For the sake of exposition, the relevant expressions are developed for a single sinusoidal input signal. It is also shown that the amplitude of this tone is commensurate with the amount of the phase error.

The expression for the phase error involves the cross-correlation between the two ADCs which is related to the phase mismatch between the two ADCs. It will be shown that the phase error depends on the Nyquist zone of the input signal. For instance, if the signal is in the first Nyquist zone, the slope of the phase error could be positive (negative) while the slope becomes negative (positive) when the signal occupies the second Nyquist zone. In applications where the input spectrum occupies different Nyquist zones at various time instants, the phase error slope toggles between negative and positive values. Consequently, any adaptation that is designed for a certain phase error slope tends to diverge when the sign of the phase error slope changes.

Here is presented an algorithm for phase correction that estimates the slope of the phase error continuously and accordingly changes the direction of adaptation of the algorithm. While the adaptive algorithm is essentially based on the sign of the phase error, the sense of adaptation is based on the sign of the slope estimate of the phase error. In other words, if the adaptive algorithm follows one direction of movement when the phase error slope is positive, it can be made to move in the opposite direction when the phase error slope is negative. In this way, the adaptive algorithm will always converge irrespective of the Nyquist zone of the input signal. The input signal to the two-channel TIADC system is itself the training signal and the estimation and correction of the phase error is carried out in the background. In other words, the adaptation is performed using a blind adaptive technique. The entire adaptation is, in a preferred embodiment, a mixed-signal process wherein the estimation of the phase error is carried out in the digital domain while the correction is carried out in the analog domain. Without loss of generality, assume that the estimation information in the digital domain is transferred to an appropriate correction in the analog domain by way of a look-up table (LUT). In the adaptation loop, for instance, a certain address to the LUT is calculated based on the phase error, in conjunction with the slope of the phase error, and the value corresponding to that address in the LUT is used in an appropriate analog circuit in the two-channel TIADC system to effect the correction.

Phase Error Correction

In this section, a two-channel TIADC system is considered with phase error only. It is assumed that the gain and phase mismatch errors have been corrected. Additionally, an input signal is assumed of the form x(t)=cos(2πF_it+φ), where F_i is an arbitrary input frequency and φ is an arbitrary phase.

The output of the two-channel TIADC system is given by

$\begin{array}{cc}y\left(n\right)=\{\begin{array}{cc}\cos \left(2\pi F_i\mathrm{nT}+\varphi \right)& n=\mathrm{even}\\ \cos \left(2\pi F_i\mathrm{nT}+\Delta t+\varphi \right)& n=\mathrm{odd}\end{array}& \left(1\right)\end{array}$ where T=1/F_S and F_S is the sampling frequency of the two-channel TIADC system. Combining the even and odd time instants in the above equation,

$\begin{array}{cc}y\left(n\right)=\cos \left(2\pi F_i\left[\mathrm{nT}+\frac{\Delta t}{2}-{\left(-1\right)}^2\frac{\Delta t}{2}\right]+\varphi \right)& \left(2\right)\end{array}$

Assume that the outputs corresponding to even time instants are output from ADC1 while those corresponding to odd time instants are output from ADC2. In other words, ADC1 samples the input signal at time instants 2nT while ADC2 samples the input signal at time instants (2n+1)T+Δt. Consequently, Δt is the sample-time error. It should be mentioned that there is no loss of generality in grouping the total phase in one of the outputs.

The above equation (2) can thus be expanded as

$\begin{array}{cc}y\left(n\right)=\cos \left(2\pi F_i\left[\mathrm{nT}+\frac{\Delta t}{2}\right]+\varphi \right)\cos \left({\left(-1\right)}^n\pi F_i\Delta t\right)+\sin \left(2\pi F_i\left[\mathrm{nT}+\frac{\Delta t}{2}\right]+\varphi \right)\sin \left({\left(-1\right)}^n\pi F_i\Delta t\right)& \left(3\right)\end{array}$

It can be seen that cos((−1)ⁿπF_iΔt)=cos(πF_iΔt). Since sin( ) is an odd function, with (−1)ⁿ=cos(nπ), then sin((−1)ⁿπF_iΔt)=cos(nπ)sin(πF_iΔt). Using sin(a)cos(nπ)=sin(a−nπ) and nπ=πF_SnT, the above equation can be written as

$\begin{array}{cc}\begin{array}{cc}y\left(n\right)=& \cos \left(\pi F_i\Delta t\right)\cos \left(2\pi F_i\mathrm{nT}+\pi F_i\Delta t+\varphi \right)+\\ & \sin \left(\pi F_i\Delta t\right)\sin \left(2\pi F_i\mathrm{nT}+\pi F_i\Delta t-\pi F_s\mathrm{nT}+\varphi \right)\\ =& \cos \left(\pi F_i\Delta t\right)\cos \left(2\pi F_i\mathrm{nT}+\pi F_i\Delta t+\varphi \right)+\\ & \sin \left(\pi F_i\Delta t\right)\sin \left(\left(2\pi F_i-\pi F_s\right)\mathrm{nT}+\pi F_i\Delta t+\varphi \right)\end{array}& \left(4\right)\end{array}$

Assuming that Δt is very small compared to T, cos(πF_iΔt)≈1 and sin(πF_iΔt)≈πF_iΔt. Consequently,

$\begin{array}{cc}\begin{array}{cc}y\left(n\right)\approx & \cos \left(2\pi F_i\mathrm{nT}+\pi F_i\Delta t+\varphi \right)+\\ & \left(\pi F_i\Delta t\right)\sin \left(\left(2\pi F_i-\pi F_s\right)\mathrm{nT}+\pi F_i\Delta t+\varphi \right)\\ \approx & \underset{\underset{\mathrm{Input}}{︸}}{\cos \left(2\pi F_i\mathrm{nT}+\pi F_i\Delta t+\varphi \right)}\end{array}& \left(5\right)\\ -\underset{\underset{\mathrm{Image}}{︸}}{\left(\pi F_i\Delta t\right)\sin \left(\left(\pi F_s-2\pi F_i\right)\mathrm{nT}-\pi F_i\Delta t-\varphi \right)}& \left(6\right)\end{array}$

It can now be seen from the above equation that the phase error produces an image tone with an amplitude proportional to the sample mismatch timing Δt.

As is well known, a correlation between two sequences provides information about the time delay between them. Towards this end, define two sequences, y₁(n) and y₂(n), as the outputs from ADC1 and ADC2, respectively. Consequentlyy₁(n)=y(2n)  (7)y₂(n)=y(2n+1)  (8)Now define a phase error as a function of the timing mismatch as

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=1}^{N-1}\{y_1\left(n-1-k\right)y_z\left(n-1-k\right)-\\ & y_2\left(n-1-k\right)y_1\left(n-k\right)\}\\ =& \frac{1}{N}\sum _{k=1}^{N-1}{y}_2\left(n-1-k\right)\left\{y_1\left(n-1-k\right)-y_1\left(n-k\right)\right\}\end{array}& \left(9\right)\end{array}$ where N is the number of samples from both ADCs used in the evaluation of e_phase(Δt). The above equation can also be written as

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=0}^{N-2}\left\{y_1\left(n-k\right)y_2\left(n-k\right)y_1\left(n-1-k\right)\right\}\\ =& \frac{1}{N}\sum _{k=0}^{N-2}{y}_2\left(n-k\right)\left\{y_1\left(n-k\right)-y_1\left(n-1-k\right)\right\}\end{array}& \left(10\right)\end{array}$

An alternative expression for the phase error given by

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=1}^{N-1}{\left\{y_1\left(n-1-k\right)-y_2\left(n-1-k\right)\right\}}^2-\\ & {\left\{y_2\left(n-1-k\right)-y_1\left(n-k\right)\right\}}^2\end{array}& \left(11\right)\end{array}$ also provides information about the phase error between the two ADCs. Again Eqn 11 can also be written as

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=0}^{N-2}{\left\{y_1\left(n-k\right)-y_2\left(n-k\right)\right\}}^2-\\ & {\left\{y_2\left(n-k\right)-y_1\left(n-1-k\right)\right\}}^2\end{array}& \left(12\right)\end{array}$

Yet another expression for the phase error can written as

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=1}^{N-1}\left|y_1\left(n-1-k\right)-y_2\left(n-1-k\right)\right|-\\ & \left|y_2\left(n-1-k\right)-y_1\left(n-k\right)\right|\end{array}& \left(13\right)\end{array}$ or, alternatively,

$\begin{array}{cc}\begin{array}{cc}{e}_{\mathrm{phase}}\left(\Delta t\right)=& \frac{1}{N}\sum _{k=0}^{N-2}\left|y_1\left(n-k\right)-y_2\left(n-k\right)\right|-\\ & \left|y_2\left(n-k\right)-y_1\left(n-1-k\right)\right|\end{array}& \left(14\right)\end{array}$

Now look at the variation of the phase error with sampling time mismatch in different Nyquist zones. As an example, consider a sinusoidal signal of 90 MHz with a sampling frequency F_S=500 MHz. It can be noted that the input signal is in the first Nyquist zone. The spectrum of such a signal is shown in FIG. 1. In this spectrum is also seen a strong tone at 160 MHz. This is an image spur created due to sample-time mismatch.

For the sake of exposition, choose the phase error equation characterized by Eqn. 9. FIG. 2 shows the variation of e_phase(Δt) with Δt as a fraction of the sampling time of the TIADC for this signal. Next, consider a signal in the second Nyquist zone. For this, choose a sinusoidal signal of 290 MHz with the same sampling frequency mentioned earlier. The spectrum of the aliased signal is shown in FIG. 3. The strong tone at 40 MHz is the image spur due to sample-time mismatch.

FIG. 4 shows the variation of e_phase(Δt) for the signal in the second Nyquist zone. As can be seen from FIG. 4, the slope of the phase error is opposite to that of the phase error shown in FIG. 2.

Now assume an adaptive algorithm based on the sign of the phase error, viz., sign(e_phase(Δt)). Looking at FIG. 2, it can be seen that the adaptive algorithm will move to the right when sign(e_phase(Δt)) is negative and move to the left when sign(e_phase(Δt)) is positive. In this way, the adaptive algorithm will converge to a timing mismatch value for which e_phase(Δt)≈0. Now apply this algorithm for the case when the input signal is in the second Nyquist zone.

From FIG. 4 it can also be seen that an adaptive algorithm will “move to the right” when sign(e_phase(Δt)) is negative and move to the left when sign(e_phase(Δt)) is positive. This results in divergence of the algorithm. Thus, the adaptive algorithm should take into account the slope of the phase error. Towards this end, presented here is a method of evaluating the slope of the phase error using a technique called gradient (or slope) filtering.

Assume P values of e_phase(Δt_k) corresponding to Δt_k are available. Using the procedure from linear regression, one can fit a line through these points with an equation given by e_p=a+mΔt where a is the intercept given by

$\begin{array}{cc}a=\frac{\begin{array}{c}\left({\sum }_k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\right)\left({\sum }_k\Delta t_k^2\right)-\\ \left({\sum }_k\Delta t_k\right)\left({\sum }_k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\Delta t_k\right)\end{array}}{P\left({\sum }_k\Delta t_k^2\right)-{\left({\sum }_k\Delta t_k\right)}^2}& \left(15\right)\end{array}$ and the slope m given by

$\begin{array}{cc}m=\frac{\begin{array}{c}P\left({\sum }_k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\Delta t_k\right)-\\ \left({\sum }_k\Delta t_k\right)\left({\sum }_k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\right)\end{array}}{P\left({\sum }_k\Delta t_k^2\right)-{\left({\sum }_k\Delta t_k\right)}^2}& \left(16\right)\end{array}$

It should be mentioned that what really is of interest here is the sign of m since the direction of adaptation is controlled by it. Thus, irrespective of the Nyquist zone of the input signal, an adaptive algorithm based on the product of sign(e_phase(Δt_k)) and sign(m) will always converge.

By choosing an anti-symmetric distribution of Δt_k around zero, Σ_kΔt_k=0. Thus Eqn. 16 can be written as

$\begin{array}{cc}m=\frac{{\sum }_k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\Delta t_k}{{\sum }_k\Delta t_k^2}& \left(17\right)\end{array}$

The denominator in the above equation is always positive and hence the sign of m can be written as

$\begin{array}{cc}{m}_s=\mathrm{sig}n\left(m\right)=\mathrm{sig}n\left(\sum _k{e}_{\mathrm{phase}}\left(\Delta t_k\right)\Delta t_k\right)& \left(18\right)\end{array}$

Therefore, knowing P ordered pair values of (e_phase(Δt_k), Δt_k), one can obtain the sign of m. If one chooses P to be odd,

$\begin{array}{cc}\Delta t_k=k-\frac{P-1}{2},\mathrm{for}k=0,1,\cdots ,P-1& \left(19\right)\end{array}$

On the other hand if P is chosen to be even,Δt_k=2k−(P−1), for k=0, 1, . . . , P−1  (20)

It can be noted that the values of Δt_k for both odd and even values of P are anti-symmetric and can thus form the coefficients of a linear-phase finite impulse response (FIR) filter. Consequently only half the values of Δt_k are sufficient to obtain the sign of m. Also, from a practical implementation perspective, the value of P should be kept small in order for the adaptive algorithm to quickly adjust to changes in the sign of the phase error slope.

It is now possible to provide an adaptive algorithm based on the product of the signs of (e_phase(Δt_k) and m to compensate sample time mismatch errors.

Algorithm for Sample Time Mismatch

A simple schematic for a two-channel TIADC that implements sample-time correction is shown in FIG. 5. The clock circuitry 150 is such that two ADC cores, viz., ADC1102-1 and ADC2102-2, sample the input signal 101 at F_S/2. In other words, for a clock running at F_S, ADC1102-1 samples at odd sample clock instants (say) while ADC2102-2 samples the input signal 101 at even sample clock instants. The samples from ADC1102-1 and ADC2102-2 are collected by a Digital Signal Processor (DSP) 122 and the phase error is evaluated at regular intervals. The DSP 122 then runs an adaptive algorithm determining the sign of the phase error in conjunction with the sign of the gradient of the phase error to feed a Phase Look Up Table (LUT) 118 with a sample time correction input.

A block diagram that effects the adaptive algorithm in shown in FIG. 6. Generally speaking, the output of the adaptive algorithm forms the address to the Phase LUT (PLUT) 118. The output of the PLUT 118 then directly or indirectly provides the corresponding sample-time correction to the clock and sample-time correction circuitry 150.

Assume the size of PLUT 118 to be N_phase. If the maximum phase mismatch between the two ADCs 102-1, 102-2 is ±X_p, then the entries of the PLUT 118 will directly or indirectly cover the range [−X_p, X_p] units. The distribution of the entries in PLUT 118 can be linear, logarithmic or based on any other distribution depending upon the characteristics of the analog circuits effecting the correction.

Let PLUT^k denote the address of PLUT 118 at the k^th iteration. Let μ^k denote a variable at the k^th iteration, and let μ_phase^k denote a step size for the adaptive algorithm at the k^th iteration. Here, assumeμ_phase^kε[μ_phasemin,μ_phasemax]  (21)where μ_phasemin and μ_phasemax are the minimum and maximum values, respectively, of μ_phase^k. The adaptive algorithm for correcting the phase error can thus be written as

$\begin{array}{cc}{\mathrm{PLUT}}^k=N_i+\lfloor {\mu }^k\rfloor & \left(22\right)\\ {\mu }^{k+1}={\mu }^k-\mathrm{sig}n\left(e_{\mathrm{phase}}^k\left(\Delta t\right)\right)\mathrm{sig}n\left(m_s^k\right){\mu }_{\mathrm{phase}}^k& \left(23\right)\\ \begin{array}{c}{\mu }_{\mathrm{phase}}^{k+1}=\max \left(\frac{{\mu }_{\mathrm{phase}}^k}{2},{\mu }_{\mathrm{phasemin}}\right)\mathrm{if}\mathrm{mod}\left(k,k_p\right)\\ =0\end{array}& \left(24\right)\end{array}$ where N_i is the initial address of the PLUT (say N_phase/2), μ⁰=0, μ_phase⁰=μ_phase and k_p is any arbitrary positive number.

The value of N_i also serves as a bias for the address input to the PLUT 118. Since the address of the PLUT ranges from 0 to N_phase−1, only positive values of are allowed. Thus μ^k can be negative or positive while N_i is chosen such that PLUT^kε[0 N_phase−1]. It should be mentioned that e_phase^k(Δt) is evaluated using Eqn. 9 and m_S^k is evaluated using Eqn. 18. Since PLUT^k refers to an address of PLUT, the update happens only when μ^k changes by an integer value in Eqn. 22. Consequently m_S^k is also evaluated at such instants when μ^k changes by an integer value. At convergence, PLUT^k indicates the optimal address of PLUT that results in the minimum value of e_phase(Δt).

More particularly now, the algorithm uses the values e_phase(Δt_k) 202 and a running sum of the values of the slope m 203 (e.g., e_phase(Δt_k)Δt_k) as inputs. Next, a pair of sign blocks 204, 205 determine the signs of the phase and slope of the phase. The signs are multiplied (which can be implemented by XOR block 208) and them multiplied 210 again by a Phase LUT step size amount, μ^k.

This signal is then fed to a filter implemented by the sum block 212 and delay 214. This arrangement provides a Finite Impulse Response (FIR) filter; it will be understood that other types of digital filters can be used, such as Infinite Impulse Response (IIR), combination FIR/IIR or other type of digital filters. A FIX block 216 then selects the integer part (e.g., the fixed point part) of the floating point filter output. These integer values are then summed 218 with N_i to determine the input address to the PLUT 118.

Experimental Results

Presented next are some experimental results based on the output of a two-channel TIADC integrated circuit. In the first experiment, a sinusoidal signal with a frequency of 90 MHz was used. The sampling frequency of the two-channel TIADC system was 500 MHz. The adaptive algorithm mentioned above was then run on the output of the two ADCs.

FIG. 7 shows the convergence of PLUT^k with iteration k, assuming N_phase=256 and P=5. As can be seen from the figure, the PLUT^k converges to a value between 127 and 128, which are the addresses corresponding to the vicinity of the minimum value of e_phase(Δt). In order to verify the convergence, it can be noted from FIG. 2 that e_phase(Δt) cross zero between 127 and 128. This confirms the convergence of the adaptive algorithm.

In the second experiment, a sinusoidal signal with a frequency of 290 MHz was used as the input. As can be noted, the input signal is in the second Nyquist zone. FIG. 8 shows the convergence of PLUT^k with iteration k. In this figure it can be seen that the algorithm diverges first before converging to the minimum value of e_phase(Δt), which corresponds to an address location of the PLUT between 122 and 123. The reason for divergence is that it requires P values of e_phase(Δt) before the gradient of the phase error is evaluated. Once the slope is evaluated, the adaptive algorithm then moves in the correct direction to converge. This convergence can be verified from FIG. 4 where e_phase(Δt) crosses zero between these address values.

The robustness of this algorithm is seen when the input signal switches Nyquist zones. For this experiment, the input signal was a 90 MHz tone for sometime and then switched to a 290 MHz tone. FIG. 9 shows the convergence of PLUT^k with iteration k. It can be seen that the algorithm settles to a PLUT address between 127 and 128 as long as the input is a 90 MHz tone. When the input changes from 90 MHz tone to a 290 MHz tone, the algorithm first moves in the wrong direction for a maximum of P points before it moves in the correct direction. This is because it needs a maximum of P phase error values to evaluate the gradient of the phase error. Once the correct direction is established, the algorithm moves towards the optimal address of PLUT, which is around 123. It can thus be seen that the adaptive algorithm is robust irrespective of the Nyquist zone occupied by the input signal.

Use in a Digital System

The above teachings with respect to analog to digital converters have wide application in the filed of electronic devices and systems. One example system is a digital signal transceiver. In such a system, the receiver may include front end analog signal processing components such as amplifiers, filters, and downconverters. A time interleaved analog to digital converter uses two or more subunit converters to provide a digital signal representative of the received signal(s) of interest. Digitizing the entire receive bandwidth of interest may require a very high sampling rate; therefore, an interleaved system as described above may provide advantages over other conversion techniques.

FIG. 10 shows one such example transceiver system 1200 connected to transmit and receive a Radio Frequency (RF) signal. The RF signal may be a wireless signal received from an antenna or maybe received on a wire such as from a coaxial, optical fiber, or its like. The transceiver 1200 transmits data to and receives data from a digital device 1211 such as a computer, telephone, television, camera or any number of digital devices.

The transceiver 1200 shown in FIG. 10 uses a wideband, time-interleaved, analog-to-digital converter (ADC) 1206 as taught herein to digitize received signals. The output from the wideband ADC 1206 can be tuned digitally, rather than with analog tuners, resulting in lower power consumption compared to alternative methods.

More particularly, in the example system 1200, signals are coupled via a diplexer 1202, which separates downstream (received) signals 1220 from upstream (transmitted) signals 1222. The diplexer 1202 directs the received signal to a variable-gain amplifier (VGA) 1204, which amplifies the received signal before transmitting it through a filter 1205 to a wideband ADC 1206. The time-interleaved ADC 1206 digitizes the received signal, then passes the digitized signal 1240 to a digital tuner and demodulator 1208. These demodulated signals may then be fed through access control 1210 and then to a digital interface 1270.

A complete digital transceiver 1200 also typically includes corresponding transmit components such as modulator 1216, digital to a converter 1218 and amplifier 1224. A CPU internal to the transceiver 1200 may further control its operation. It should also be understood that other components not shown here, such as up converters and down converters may form part of transceiver 1200.

Those of skill will further appreciate that the various illustrative components, logical blocks, signal processing blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed above may be implemented as analog or digital electronic hardware, or as computer software, or as combinations of the same. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The various illustrative components, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with general purpose processors, digital signal processors (DSPs) or other logic devices, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be any conventional processor, controller, microcontroller, state machine or the like. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in software or firmware modules executed by a processor, or in a combination thereof. A software product may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

CONCLUSION

In this disclosure a robust method for correcting the phase error in a two-channel TIADC system that is independent of the Nyquist zone occupied by the input signal has been described. The adaptive algorithm is based on estimating the gradient of the phase error using a filter. The coefficients of the filter can be derived from a simplified expression of linear regression. The direction of the adaptation is controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value irrespective of the Nyquist zone occupied by the input signal. The efficacy of the adaptive algorithm was shown by way of experimental results based on a two-channel TIADC.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

1. A method comprising: analog-to-digital (ADC) converting an analog input signal to provide to a set of two ADC outputs as first and second digital signals;estimating a sample time error from the first and second digital signals;determining a correction signal from the sample time error regardless of a Nyquist zone occupied by the analog input signal; andapplying the correction signal to the analog-to-digital converting step.

2. The method of claim 1 wherein the step of determining the correction signal comprises estimating a gradient of the sample time error.

3. The method of claim 2 wherein determining the correction signal further comprises determining a sign of the gradient of the sample time error.

4. The method of claim 3 wherein determining the correction signal further comprises filtering the sign of the gradient of the sample time error.

5. The method of claim 1 wherein the sample time error is a digital value and the correction signal is an analog signal.

6. The method of claim 1 further comprising: looking up the correction signal in stored value lookup table.

7. The method of claim 1 wherein the step of determining the correction signal from the sample time value regardless of a Nyquist zone occupied by the analog input signal is determined from a gradient of the sample time error, and that gradient is then used in determining the correction signal.

8. The method of claim 1 wherein the step of determining a correction signal error further comprises: storing correction values in a Phase Look Up Table (PLUT) where

9. The method of claim 8 further comprising: filtering an input to the PLUT.

10. The method of claim 1 additionally comprising: interleaving the first and second digital signals to form a digital converter representation of the analog input signal.

11. The method of claim 4 wherein the filtering step is a Finite Impulse Response (FIR) filtering step.

12. An apparatus comprising: two or more Time-Interleaved Analog to Digital Converter (TIADC) cores, providing a set of two ADC outputs as first and second digital signals, at least one of the TIADC cores having a correction input;a signal interleaver for combining the first and second digital signals to form a digital converted representation of the input signal;a digital signal processing operator, for estimating a phase error estimate from the first and second digital signals to provide a phase error estimate; anddetermining a correction signal from the phase error estimate regardless of a Nyquist zone occupied by the input signal; andthe correction signal being connected to the sample time correction input of at least one of the TIADC cores.

13. An apparatus comprising: two or more Time-Interleaved Analog to Digital Converter (TIADC) cores, providing a set of two ADC outputs as first and second digital signals, at least one of the TIADC cores having a correction input;a signal interleaver for combining the first and second digital signals to form a digital converted representation of the input signal;a digital signal processing operator, for estimating a phase error estimate from the first and second digital signals to provide a phase error estimate; anddetermining a correction signal from the phase error estimate regardless of a Nyquist zone occupied by the input signal; andthe correction signal being connected to the sample time correction input of at least one of the TIADC cores,the apparatus additionally comprising:a slope detector, for determining a slope of the phase error estimate.

14. The apparatus of claim 13 further comprising: a sign operation to determine a sign of the slop of the phase error estimate.

15. The apparatus of claim 14 further comprising: a Finite Impulse Response (FIR) filter for filtering a sign of the gradient of the phase error.

16. The apparatus of claim 13 wherein the phase error estimate is a digital value and the correction signal is an analog signal.

17. The apparatus of claim 13 additionally comprising a Look Up Table for providing the correction signal.

18. The apparatus of claim 13 additionally wherein the correction value is determined by slope detector that further determines a value indicative of a Nyquist zone occupied by the input signal from a slope of the phase error estimate.

19. The apparatus of claim 13 additionally comprising a Phase Look Up Table (PLUT) for determining the correction signal where

20. The apparatus of claim 19 additionally comprising a filter for processing an input to the PLUT.

21. A programmable computer product for use with a multiple channel time interleaved analog to digital converter, wherein first and second digital signals are interleaved to form a digital converted representation of an input signal, the product comprising one or more programmable data processing machines that retrieve instructions stored on a non-transitioning computer readable medium and the one or more programmable data processing machines executing the the instructions, the instructions for: receiving first and second digital signals;estimating a sample time error from the first and second digital signals;determining a correction signal from the sample time error regardless of a Nyquist zone occupied by the input signal; andoutputting the correction signal.

22. A communication system comprising: a communication signal receiver, for receiving an input signal;an analog to digital converter (ADC) connected to the receiver, for producing a digital input signal; anda demodulator, for digitally demodulating the digital input signal;

23. The method of claim 1 wherein the Nyquist zone occupied by the analog signal input includes at least one of a) a first range of frequencies below one-half of a sampling frequency, FS, andb) a second range of frequencies above one-half of the sampling frequency, FS.

24. The apparatus of claim 12 wherein the Nyquist zone occupied by the input signal includes one or more of a) a first range of frequencies below one-half of a sampling frequency, FS, andb) a second range of frequencies above one-half of the sampling frequency, FS.